code refactoring for Vivado compatibility
This commit is contained in:
Blaise Tine
225
hw/rtl/Vortex.sv
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225
hw/rtl/Vortex.sv
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`include "VX_define.vh"
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module Vortex (
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`SCOPE_IO_Vortex
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// Clock
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input wire clk,
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input wire reset,
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// Memory request
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output wire mem_req_valid,
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output wire mem_req_rw,
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output wire [`VX_MEM_BYTEEN_WIDTH-1:0] mem_req_byteen,
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output wire [`VX_MEM_ADDR_WIDTH-1:0] mem_req_addr,
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output wire [`VX_MEM_DATA_WIDTH-1:0] mem_req_data,
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output wire [`VX_MEM_TAG_WIDTH-1:0] mem_req_tag,
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input wire mem_req_ready,
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// Memory response
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input wire mem_rsp_valid,
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input wire [`VX_MEM_DATA_WIDTH-1:0] mem_rsp_data,
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input wire [`VX_MEM_TAG_WIDTH-1:0] mem_rsp_tag,
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output wire mem_rsp_ready,
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// Status
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output wire busy
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);
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`STATIC_ASSERT((`L3_ENABLE == 0 || `NUM_CLUSTERS > 1), ("invalid parameter"))
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wire [`NUM_CLUSTERS-1:0] per_cluster_mem_req_valid;
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wire [`NUM_CLUSTERS-1:0] per_cluster_mem_req_rw;
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wire [`NUM_CLUSTERS-1:0][`L2_MEM_BYTEEN_WIDTH-1:0] per_cluster_mem_req_byteen;
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wire [`NUM_CLUSTERS-1:0][`L2_MEM_ADDR_WIDTH-1:0] per_cluster_mem_req_addr;
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wire [`NUM_CLUSTERS-1:0][`L2_MEM_DATA_WIDTH-1:0] per_cluster_mem_req_data;
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wire [`NUM_CLUSTERS-1:0][`L2_MEM_TAG_WIDTH-1:0] per_cluster_mem_req_tag;
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wire [`NUM_CLUSTERS-1:0] per_cluster_mem_req_ready;
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wire [`NUM_CLUSTERS-1:0] per_cluster_mem_rsp_valid;
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wire [`NUM_CLUSTERS-1:0][`L2_MEM_DATA_WIDTH-1:0] per_cluster_mem_rsp_data;
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wire [`NUM_CLUSTERS-1:0][`L2_MEM_TAG_WIDTH-1:0] per_cluster_mem_rsp_tag;
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wire [`NUM_CLUSTERS-1:0] per_cluster_mem_rsp_ready;
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wire [`NUM_CLUSTERS-1:0] per_cluster_busy;
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for (genvar i = 0; i < `NUM_CLUSTERS; i++) begin
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`RESET_RELAY (cluster_reset);
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VX_cluster #(
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.CLUSTER_ID(i)
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) cluster (
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`SCOPE_BIND_Vortex_cluster(i)
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.clk (clk),
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.reset (cluster_reset),
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.mem_req_valid (per_cluster_mem_req_valid [i]),
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.mem_req_rw (per_cluster_mem_req_rw [i]),
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.mem_req_byteen (per_cluster_mem_req_byteen[i]),
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.mem_req_addr (per_cluster_mem_req_addr [i]),
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.mem_req_data (per_cluster_mem_req_data [i]),
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.mem_req_tag (per_cluster_mem_req_tag [i]),
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.mem_req_ready (per_cluster_mem_req_ready [i]),
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.mem_rsp_valid (per_cluster_mem_rsp_valid [i]),
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.mem_rsp_data (per_cluster_mem_rsp_data [i]),
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.mem_rsp_tag (per_cluster_mem_rsp_tag [i]),
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.mem_rsp_ready (per_cluster_mem_rsp_ready [i]),
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.busy (per_cluster_busy [i])
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);
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end
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assign busy = (| per_cluster_busy);
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if (`L3_ENABLE) begin
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`ifdef PERF_ENABLE
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VX_perf_cache_if perf_l3cache_if();
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`endif
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`RESET_RELAY (l3_reset);
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VX_cache #(
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.CACHE_ID (`L3_CACHE_ID),
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.CACHE_SIZE (`L3_CACHE_SIZE),
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.CACHE_LINE_SIZE (`L3_CACHE_LINE_SIZE),
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.NUM_BANKS (`L3_NUM_BANKS),
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.NUM_PORTS (`L3_NUM_PORTS),
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.WORD_SIZE (`L3_WORD_SIZE),
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.NUM_REQS (`L3_NUM_REQS),
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.CREQ_SIZE (`L3_CREQ_SIZE),
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.CRSQ_SIZE (`L3_CRSQ_SIZE),
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.MSHR_SIZE (`L3_MSHR_SIZE),
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.MRSQ_SIZE (`L3_MRSQ_SIZE),
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.MREQ_SIZE (`L3_MREQ_SIZE),
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.WRITE_ENABLE (1),
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.CORE_TAG_WIDTH (`L2_MEM_TAG_WIDTH),
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.CORE_TAG_ID_BITS (0),
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.MEM_TAG_WIDTH (`L3_MEM_TAG_WIDTH),
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.NC_ENABLE (1)
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) l3cache (
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`SCOPE_BIND_Vortex_l3cache
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.clk (clk),
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.reset (l3_reset),
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`ifdef PERF_ENABLE
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.perf_cache_if (perf_l3cache_if),
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`endif
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// Core request
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.core_req_valid (per_cluster_mem_req_valid),
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.core_req_rw (per_cluster_mem_req_rw),
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.core_req_byteen (per_cluster_mem_req_byteen),
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.core_req_addr (per_cluster_mem_req_addr),
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.core_req_data (per_cluster_mem_req_data),
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.core_req_tag (per_cluster_mem_req_tag),
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.core_req_ready (per_cluster_mem_req_ready),
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// Core response
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.core_rsp_valid (per_cluster_mem_rsp_valid),
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.core_rsp_data (per_cluster_mem_rsp_data),
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.core_rsp_tag (per_cluster_mem_rsp_tag),
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.core_rsp_ready (per_cluster_mem_rsp_ready),
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`UNUSED_PIN (core_rsp_tmask),
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// Memory request
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.mem_req_valid (mem_req_valid),
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.mem_req_rw (mem_req_rw),
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.mem_req_byteen (mem_req_byteen),
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.mem_req_addr (mem_req_addr),
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.mem_req_data (mem_req_data),
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.mem_req_tag (mem_req_tag),
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.mem_req_ready (mem_req_ready),
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// Memory response
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.mem_rsp_valid (mem_rsp_valid),
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.mem_rsp_data (mem_rsp_data),
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.mem_rsp_tag (mem_rsp_tag),
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.mem_rsp_ready (mem_rsp_ready)
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);
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end else begin
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`RESET_RELAY (mem_arb_reset);
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VX_mem_arb #(
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.NUM_REQS (`NUM_CLUSTERS),
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.DATA_WIDTH (`L3_MEM_DATA_WIDTH),
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.ADDR_WIDTH (`L3_MEM_ADDR_WIDTH),
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.TAG_IN_WIDTH (`L2_MEM_TAG_WIDTH),
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.TYPE ("R"),
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.BUFFERED_REQ (1),
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.BUFFERED_RSP (1)
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) mem_arb (
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.clk (clk),
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.reset (mem_arb_reset),
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// Core request
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.req_valid_in (per_cluster_mem_req_valid),
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.req_rw_in (per_cluster_mem_req_rw),
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.req_byteen_in (per_cluster_mem_req_byteen),
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.req_addr_in (per_cluster_mem_req_addr),
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.req_data_in (per_cluster_mem_req_data),
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.req_tag_in (per_cluster_mem_req_tag),
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.req_ready_in (per_cluster_mem_req_ready),
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// Memory request
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.req_valid_out (mem_req_valid),
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.req_rw_out (mem_req_rw),
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.req_byteen_out (mem_req_byteen),
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.req_addr_out (mem_req_addr),
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.req_data_out (mem_req_data),
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.req_tag_out (mem_req_tag),
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.req_ready_out (mem_req_ready),
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// Core response
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.rsp_valid_out (per_cluster_mem_rsp_valid),
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.rsp_data_out (per_cluster_mem_rsp_data),
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.rsp_tag_out (per_cluster_mem_rsp_tag),
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.rsp_ready_out (per_cluster_mem_rsp_ready),
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// Memory response
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.rsp_valid_in (mem_rsp_valid),
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.rsp_tag_in (mem_rsp_tag),
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.rsp_data_in (mem_rsp_data),
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.rsp_ready_in (mem_rsp_ready)
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);
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end
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`SCOPE_ASSIGN (reset, reset);
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`SCOPE_ASSIGN (mem_req_fire, mem_req_valid && mem_req_ready);
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`SCOPE_ASSIGN (mem_req_addr, `TO_FULL_ADDR(mem_req_addr));
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`SCOPE_ASSIGN (mem_req_rw, mem_req_rw);
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`SCOPE_ASSIGN (mem_req_byteen, mem_req_byteen);
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`SCOPE_ASSIGN (mem_req_data, mem_req_data);
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`SCOPE_ASSIGN (mem_req_tag, mem_req_tag);
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`SCOPE_ASSIGN (mem_rsp_fire, mem_rsp_valid && mem_rsp_ready);
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`SCOPE_ASSIGN (mem_rsp_data, mem_rsp_data);
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`SCOPE_ASSIGN (mem_rsp_tag, mem_rsp_tag);
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`SCOPE_ASSIGN (busy, busy);
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`ifdef DBG_PRINT_MEM
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always @(posedge clk) begin
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if (mem_req_valid && mem_req_ready) begin
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if (mem_req_rw)
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dpi_trace("%d: MEM Wr Req: addr=%0h, tag=%0h, byteen=%0h data=%0h\n", $time, `TO_FULL_ADDR(mem_req_addr), mem_req_tag, mem_req_byteen, mem_req_data);
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else
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dpi_trace("%d: MEM Rd Req: addr=%0h, tag=%0h, byteen=%0h\n", $time, `TO_FULL_ADDR(mem_req_addr), mem_req_tag, mem_req_byteen);
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end
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if (mem_rsp_valid && mem_rsp_ready) begin
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dpi_trace("%d: MEM Rsp: tag=%0h, data=%0h\n", $time, mem_rsp_tag, mem_rsp_data);
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end
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end
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`endif
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`ifndef NDEBUG
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always @(posedge clk) begin
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$fflush(); // flush stdout buffer
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end
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`endif
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endmodule
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