Merge branch 'master' of https://github.gatech.edu/casl/Vortex

Flubber_FPGA_Startup_Guide.md

@@ -0,0 +1,68 @@
+# Flubber FPGA Startup and Configuration Guide 
+
+Flubber OPAE setup
+------------------
+
+    $ source /opt/inteldevstack/init_env_user.sh
+    $ export OPAE_HOME=/opt/opae/1.1.2
+    $ export PATH=$OPAE_HOME/bin:$PATH
+    $ export C_INCLUDE_PATH=$OPAE_HOME/include:$C_INCLUDE_PATH
+    $ export LIBRARY_PATH=$OPAE_HOME/lib:$LIBRARY_PATH
+    $ export LD_LIBRARY_PATH=$OPAE_HOME/lib:$LD_LIBRARY_PATH
+    $ export RISCV_TOOLCHAIN_PATH=/opt/riscv-gnu-toolchain
+    $ export PATH=:/opt/verilator/bin:$PATH
+    $ export VERILATOR_ROOT=/opt/verilator
+
+
+Flubber OPAE build
+------------------
+
+The Flubber FPGA has to following configuration options:
+- 1 core fpga (fpga-1c)
+- 2 cores fpga (fpga-2c)
+- 4 cores fpga (fpga-4c)
+- 8 cores fpga (fpga-8c)
+- 16 cores fpga (fpga-16c)
+    $ cd hw/syn/opae
+    $ make fpga-`# of cores`c
+Example: `make fpga-4c`
+
+A new folder *build_fpga_`# of cores`c* will be created and the build will start and take ~30-45 min to complete.
+
+Flubber Config Build Progress
+-----------------------------
+
+You could check the last 10 lines in the build log for possible errors until build completion.
+    $ tail -n 10 ./build_fpga_`# of cores`c/build.log
+Example: `tail -n 10 ./build_fpga_4c/build.log`
+
+Check if the build is still running by looking for quartus_sh, quartus_syn, or quartus_fit programs.
+    $ ps -u `username`
+
+If the build fails and you need to restart it, clean up the build folder using the following command:
+    $ make clean-fpga-`# of cores`c
+Example: `make clean-fpga-4c`
+
+The file `vortex_afu.gbs` should exist when the build is done:
+    $ ls -lsa ./build_fpga_`# of cores`c/vortex_afu.gbs
+
+Signing the bitstream and Programming the FPGA
+----------------------------------------------
+
+    $ cd ./build_fpga_`# of cores`c/
+    $ PACSign PR -t UPDATE -H openssl_manager -i vortex_afu.gbs -o vortex_afu_unsigned_ssl.gbs
+    $ fpgasupdate vortex_afu_unsigned_ssl.gbs
+
+FPGA sample test running OpenCL sgemm kernel
+--------------------------------------------
+
+Run the following from the Vortex root directory
+    $ ./ci/blackbox.sh --driver=fpga --app=sgemm --args="-n64"
+
+Build Script Configuration
+--------------------------
+
+Inside the ci folder there is a script called `blackbox.sh` which runs different tests on the Vortex processor with different configurations. Run:
+    $ ./ci/blackbox.sh --help
+To see the different configuration options available.
+The most important ones are `--driver`, which runs the Vortex test on either the fpga, rtlsim, vlsim, or simx simulators, and `--perf`, which enables the profiling counters for each core.

driver/opae/Makefile

@@ -109,10 +109,7 @@ clean-asesim:
 clean-vlsim:
 	$(MAKE) -C vlsim clean
 
-clean:
-	clean-fpga
-	clean-asesim
-	clean-vlsim
+clean: clean-fpga clean-asesim clean-vlsim
 
 ifneq ($(MAKECMDGOALS),clean)
     -include .depend

driver/opae/vlsim/verilator.vlt

@@ -7,3 +7,4 @@ lint_off -rule UNUSED -file "../../../hw/rtl/fp_cores/fpnew/*"
 lint_off -rule LITENDIAN -file "../../../hw/rtl/fp_cores/fpnew/*"
 lint_off -rule IMPORTSTAR -file "../../../hw/rtl/fp_cores/fpnew/*"
 lint_off -rule PINCONNECTEMPTY -file "../../../hw/rtl/fp_cores/fpnew/*"
+lint_off -file "../rtl/fp_cores/fpnew/*"

driver/opae/vlsim/vortex_afu_shim.sv

@@ -1,5 +1,5 @@
-`include "vortex_afu.vh"
 `include "VX_define.vh"
+`include "vortex_afu.vh"
 /* verilator lint_off IMPORTSTAR */ 
 import ccip_if_pkg::*;
 import local_mem_cfg_pkg::*;

driver/rtlsim/verilator.vlt

@@ -7,3 +7,4 @@ lint_off -rule UNUSED -file "../../hw/rtl/fp_cores/fpnew/*"
 lint_off -rule LITENDIAN -file "../../hw/rtl/fp_cores/fpnew/*"
 lint_off -rule IMPORTSTAR -file "../../hw/rtl/fp_cores/fpnew/*"
 lint_off -rule PINCONNECTEMPTY -file "../../hw/rtl/fp_cores/fpnew/*"
+lint_off -file "../rtl/fp_cores/fpnew/*"

hw/rtl/VX_alu_unit.v

@@ -13,6 +13,9 @@ module VX_alu_unit #(
     VX_branch_ctl_if    branch_ctl_if,
     VX_commit_if        alu_commit_if    
 );   
+
+    `UNUSED_PARAM (CORE_ID)
+    
     reg [`NUM_THREADS-1:0][31:0]  alu_result;    
     wire [`NUM_THREADS-1:0][31:0] add_result;   
     wire [`NUM_THREADS-1:0][32:0] sub_result;

hw/rtl/VX_core.v

@@ -73,27 +73,23 @@ module VX_core #(
     VX_dcache_core_req_if #(
         .NUM_REQS(`DNUM_REQUESTS), 
         .WORD_SIZE(`DWORD_SIZE), 
-        .CORE_TAG_WIDTH(`DCORE_TAG_WIDTH),
-        .CORE_TAG_ID_BITS(`DCORE_TAG_ID_BITS)
+        .CORE_TAG_WIDTH(`DCORE_TAG_WIDTH)
     ) dcache_core_req_if();
 
     VX_dcache_core_rsp_if #(
         .NUM_REQS(`DNUM_REQUESTS), 
         .WORD_SIZE(`DWORD_SIZE), 
-        .CORE_TAG_WIDTH(`DCORE_TAG_WIDTH),
-        .CORE_TAG_ID_BITS(`DCORE_TAG_ID_BITS)
+        .CORE_TAG_WIDTH(`DCORE_TAG_WIDTH)
     ) dcache_core_rsp_if();
     
     VX_icache_core_req_if #(
         .WORD_SIZE(`IWORD_SIZE), 
-        .CORE_TAG_WIDTH(`ICORE_TAG_WIDTH),
-        .CORE_TAG_ID_BITS(`ICORE_TAG_ID_BITS)
+        .CORE_TAG_WIDTH(`ICORE_TAG_WIDTH)
     ) icache_core_req_if();
 
     VX_icache_core_rsp_if #(
         .WORD_SIZE(`IWORD_SIZE), 
-        .CORE_TAG_WIDTH(`ICORE_TAG_WIDTH),
-        .CORE_TAG_ID_BITS(`ICORE_TAG_ID_BITS)
+        .CORE_TAG_WIDTH(`ICORE_TAG_WIDTH)
     ) icache_core_rsp_if();
     
     VX_pipeline #(

hw/rtl/VX_decode.v

@@ -15,6 +15,7 @@ module VX_decode  #(
     VX_wstall_if        wstall_if,
     VX_join_if          join_if
 );
+    `UNUSED_PARAM (CORE_ID)
     `UNUSED_VAR (clk)
     `UNUSED_VAR (reset)
     

hw/rtl/VX_fpu_unit.v

@@ -17,6 +17,8 @@ module VX_fpu_unit #(
     input wire[`NUM_WARPS-1:0] csr_pending,
     output wire[`NUM_WARPS-1:0] pending
 ); 
+
+    `UNUSED_PARAM (CORE_ID)    
     localparam FPUQ_BITS = `LOG2UP(`FPUQ_SIZE);
 
     wire ready_in;

hw/rtl/VX_gpr_stage.v

@@ -13,6 +13,8 @@ module VX_gpr_stage #(
     // outputs
     VX_gpr_rsp_if   gpr_rsp_if
 );
+
+    `UNUSED_PARAM (CORE_ID)
     `UNUSED_VAR (reset)    
 
     // ensure r0 never gets written, which can happen before the reset

hw/rtl/VX_gpu_unit.v

@@ -15,6 +15,8 @@ module VX_gpu_unit #(
     VX_warp_ctl_if  warp_ctl_if,
     VX_commit_if    gpu_commit_if
 );
+
+    `UNUSED_PARAM (CORE_ID)
     `UNUSED_VAR (clk)
     `UNUSED_VAR (reset)
 

hw/rtl/VX_ibuffer.v

@@ -13,6 +13,9 @@ module VX_ibuffer #(
     // outputs
     VX_decode_if  ibuf_deq_if
 );
+
+    `UNUSED_PARAM (CORE_ID)
+    
     localparam DATAW   = `NUM_THREADS + 32 + `EX_BITS + `OP_BITS + `FRM_BITS + 1 + (`NR_BITS * 4) + 32 + 1 + 1 + `NUM_REGS;
     localparam SIZE    = 3;
     localparam ADDRW   = $clog2(SIZE);

hw/rtl/VX_icache_stage.v

@@ -18,6 +18,8 @@ module VX_icache_stage #(
     // reponse
     VX_ifetch_rsp_if        ifetch_rsp_if
 );
+
+    `UNUSED_PARAM (CORE_ID)
     `UNUSED_VAR (reset)
 
     wire icache_req_fire = icache_req_if.valid && icache_req_if.ready;

hw/rtl/VX_lsu_unit.v

@@ -20,6 +20,8 @@ module VX_lsu_unit #(
     VX_commit_if    st_commit_if
 );
 
+    `UNUSED_PARAM (CORE_ID)
+    
     wire                          req_valid;
     wire [`NUM_THREADS-1:0]       req_tmask;
     wire [`NUM_THREADS-1:0][31:0] req_addr;       

hw/rtl/VX_mem_unit.v

@@ -43,29 +43,25 @@ module VX_mem_unit # (
     VX_dcache_core_req_if #(
         .NUM_REQS       (`DNUM_REQUESTS), 
         .WORD_SIZE      (`DWORD_SIZE), 
-        .CORE_TAG_WIDTH   (`DCORE_TAG_WIDTH),
-        .CORE_TAG_ID_BITS (`DCORE_TAG_ID_BITS)
+        .CORE_TAG_WIDTH (`DCORE_TAG_WIDTH)
     ) dcache_req_if();
 
     VX_dcache_core_rsp_if #(
         .NUM_REQS       (`DNUM_REQUESTS), 
         .WORD_SIZE      (`DWORD_SIZE), 
-        .CORE_TAG_WIDTH   (`DCORE_TAG_WIDTH),
-        .CORE_TAG_ID_BITS (`DCORE_TAG_ID_BITS)
+        .CORE_TAG_WIDTH (`DCORE_TAG_WIDTH)
     ) dcache_rsp_if();
 
     VX_dcache_core_req_if #(
         .NUM_REQS       (`DNUM_REQUESTS), 
         .WORD_SIZE      (`DWORD_SIZE), 
-        .CORE_TAG_WIDTH   (`DCORE_TAG_WIDTH),
-        .CORE_TAG_ID_BITS (`DCORE_TAG_ID_BITS)
+        .CORE_TAG_WIDTH (`DCORE_TAG_WIDTH)
     ) smem_req_if();
 
     VX_dcache_core_rsp_if #(
         .NUM_REQS       (`DNUM_REQUESTS), 
         .WORD_SIZE      (`DWORD_SIZE), 
-        .CORE_TAG_WIDTH   (`DCORE_TAG_WIDTH),
-        .CORE_TAG_ID_BITS (`DCORE_TAG_ID_BITS)
+        .CORE_TAG_WIDTH (`DCORE_TAG_WIDTH)
     ) smem_rsp_if();
 
     VX_databus_arb databus_arb (   

hw/rtl/VX_pipeline.v

@@ -63,8 +63,7 @@ module VX_pipeline #(
     VX_dcache_core_req_if #(
         .NUM_REQS(`NUM_THREADS), 
         .WORD_SIZE(4), 
-        .CORE_TAG_WIDTH(`DCORE_TAG_WIDTH),
-        .CORE_TAG_ID_BITS(`DCORE_TAG_ID_BITS)
+        .CORE_TAG_WIDTH(`DCORE_TAG_WIDTH)
     ) dcache_core_req_if();
 
     assign dcache_req_valid  = dcache_core_req_if.valid;
@@ -82,8 +81,7 @@ module VX_pipeline #(
     VX_dcache_core_rsp_if #(
         .NUM_REQS(`NUM_THREADS), 
         .WORD_SIZE(4), 
-        .CORE_TAG_WIDTH(`DCORE_TAG_WIDTH),
-        .CORE_TAG_ID_BITS(`DCORE_TAG_ID_BITS)
+        .CORE_TAG_WIDTH(`DCORE_TAG_WIDTH)
     ) dcache_core_rsp_if();
 
     assign dcache_core_rsp_if.valid = dcache_rsp_valid;
@@ -97,8 +95,7 @@ module VX_pipeline #(
 
     VX_icache_core_req_if #(
         .WORD_SIZE(4), 
-        .CORE_TAG_WIDTH(`ICORE_TAG_WIDTH),
-        .CORE_TAG_ID_BITS(`ICORE_TAG_ID_BITS)
+        .CORE_TAG_WIDTH(`ICORE_TAG_WIDTH)
     ) icache_core_req_if();       
 
     assign icache_req_valid  = icache_core_req_if.valid;
@@ -112,8 +109,7 @@ module VX_pipeline #(
 
     VX_icache_core_rsp_if #(
         .WORD_SIZE(4), 
-        .CORE_TAG_WIDTH(`ICORE_TAG_WIDTH),
-        .CORE_TAG_ID_BITS(`ICORE_TAG_ID_BITS)
+        .CORE_TAG_WIDTH(`ICORE_TAG_WIDTH)
     ) icache_core_rsp_if();    
 
     assign icache_core_rsp_if.valid = icache_rsp_valid;

hw/rtl/VX_platform.vh

@@ -33,6 +33,10 @@
                               /* verilator lint_on DECLFILENAME */ \
                               /* verilator lint_on IMPLICIT */
 
+`define UNUSED_PARAM(x)  /* verilator lint_off UNUSED */ \
+                         localparam  __``x = x; \
+                         /* verilator lint_on UNUSED */
+
 `define UNUSED_VAR(x) always @(x) begin end
 
 `define UNUSED_PIN(x)  /* verilator lint_off PINCONNECTEMPTY */ \

hw/rtl/VX_warp_sched.v

@@ -18,6 +18,9 @@ module VX_warp_sched #(
 
     output wire         busy
 );
+
+    `UNUSED_PARAM (CORE_ID)
+
     wire                    join_fall;
     wire [31:0]             join_pc;
     wire [`NUM_THREADS-1:0] join_tm;

hw/rtl/VX_writeback.v

@@ -15,6 +15,9 @@ module VX_writeback #(
     // outputs
     VX_writeback_if writeback_if
 );
+
+    `UNUSED_PARAM (CORE_ID)
+    
     wire ld_valid  = ld_commit_if.valid && ld_commit_if.wb;    
     wire fpu_valid = fpu_commit_if.valid && fpu_commit_if.wb;
     wire csr_valid = csr_commit_if.valid && csr_commit_if.wb;

hw/rtl/afu/vortex_afu.sv

@@ -1,5 +1,5 @@
+`include "VX_define.vh"
 `ifndef NOPAE
-`include "platform_if.vh"
 import local_mem_cfg_pkg::*;
 `include "afu_json_info.vh"
 `else
@@ -10,8 +10,6 @@ import local_mem_cfg_pkg::*;
 /* verilator lint_on IMPORTSTAR */ 
 `endif
 
-`include "VX_define.vh"
-
 module vortex_afu #(
   parameter NUM_LOCAL_MEM_BANKS = 2
 ) (
@@ -993,6 +991,9 @@ VX_scope #(
   .bus_write(cmd_scope_write)
 );
 
+`else
+  `UNUSED_PARAM (MMIO_SCOPE_READ)
+  `UNUSED_PARAM (MMIO_SCOPE_WRITE)
 `endif
 
 endmodule

hw/rtl/afu/vortex_afu.vh

@@ -1,14 +1,18 @@
 `ifndef __VORTEX_AFU__
 `define __VORTEX_AFU__
 
+`IGNORE_WARNINGS_BEGIN
 `include "ccip_if_pkg.sv"
+`IGNORE_WARNINGS_END
 
 `define PLATFORM_PROVIDES_LOCAL_MEMORY
 `define PLATFORM_PARAM_LOCAL_MEMORY_ADDR_WIDTH      26
 `define PLATFORM_PARAM_LOCAL_MEMORY_DATA_WIDTH      512
 `define PLATFORM_PARAM_LOCAL_MEMORY_BURST_CNT_WIDTH 4
 
+`IGNORE_WARNINGS_BEGIN
 `include "local_mem_cfg_pkg.sv"
+`IGNORE_WARNINGS_END
 
 `define AFU_ACCEL_NAME "vortex_afu"
 `define AFU_ACCEL_UUID 128'h35f9452b_25c2_434c_93d5_6f8c60db361c

hw/rtl/cache/VX_bank.v

@@ -22,8 +22,6 @@ module VX_bank #(
     parameter CREQ_SIZE                     = 1, 
     // Miss Reserv Queue Knob
     parameter MSHR_SIZE                     = 1, 
-    // DRAM Response Queue Size
-    parameter DRSQ_SIZE                     = 1, 
     // DRAM Request Queue Size
     parameter DREQ_SIZE                     = 1,
 
@@ -92,6 +90,8 @@ module VX_bank #(
     input wire [`LINE_SELECT_BITS-1:0]  flush_addr
 );
 
+    `UNUSED_PARAM (CORE_TAG_ID_BITS)
+    
 `ifdef DBG_CACHE_REQ_INFO
     /* verilator lint_off UNUSED */
     wire [31:0]         debug_pc_sel, debug_pc_st0,  debug_pc_st1;
@@ -421,7 +421,6 @@ module VX_bank #(
     VX_miss_resrv #(
         .BANK_ID            (BANK_ID),
         .CACHE_ID           (CACHE_ID),
-        .CORE_TAG_ID_BITS   (CORE_TAG_ID_BITS),
         .CACHE_LINE_SIZE    (CACHE_LINE_SIZE),
         .NUM_BANKS          (NUM_BANKS),
         .NUM_PORTS          (NUM_PORTS),

hw/rtl/cache/VX_cache.v

@@ -165,8 +165,7 @@ module VX_cache #(
     VX_flush_ctrl #( 
         .CACHE_SIZE (CACHE_SIZE),
         .CACHE_LINE_SIZE (CACHE_LINE_SIZE),
-        .NUM_BANKS       (NUM_BANKS),
-        .WORD_SIZE       (WORD_SIZE)
+        .NUM_BANKS  (NUM_BANKS)
     ) flush_ctrl (
         .clk       (clk),
         .reset     (reset),
@@ -294,7 +293,6 @@ module VX_cache #(
             .NUM_REQS           (NUM_REQS),
             .CREQ_SIZE          (CREQ_SIZE),
             .MSHR_SIZE          (MSHR_SIZE),
-            .DRSQ_SIZE          (DRSQ_SIZE),
             .DREQ_SIZE          (DREQ_SIZE),
             .WRITE_ENABLE       (WRITE_ENABLE),
             .CORE_TAG_WIDTH     (CORE_TAG_WIDTH),                

hw/rtl/cache/VX_data_access.v

@@ -38,6 +38,10 @@ module VX_data_access #(
     input wire [CACHE_LINE_SIZE-1:0]    byteen,
     input wire [`CACHE_LINE_WIDTH-1:0]  wdata
 );
+
+    `UNUSED_PARAM (CACHE_ID)
+    `UNUSED_PARAM (BANK_ID)
+    `UNUSED_PARAM (WORD_SIZE)
     `UNUSED_VAR (reset)
     `UNUSED_VAR (readen)
 

hw/rtl/cache/VX_flush_ctrl.v

@@ -6,9 +6,7 @@ module VX_flush_ctrl #(
     // Size of line inside a bank in bytes
     parameter CACHE_LINE_SIZE   = 1, 
     // Number of banks
-    parameter NUM_BANKS         = 1, 
-    // Size of a word in bytes
-    parameter WORD_SIZE         = 1
+    parameter NUM_BANKS         = 1
 ) (
     input wire  clk,
     input wire  reset,

hw/rtl/cache/VX_miss_resrv.v

@@ -19,9 +19,7 @@ module VX_miss_resrv #(
     parameter MSHR_SIZE         = 1, 
     parameter ALM_FULL          = (MSHR_SIZE-1),
     // core request tag size
-    parameter CORE_TAG_WIDTH    = 1,
-    // size of tag id in core request tag
-    parameter CORE_TAG_ID_BITS  = 0
+    parameter CORE_TAG_WIDTH    = 1
 ) (
     input wire clk,
     input wire reset,
@@ -58,6 +56,8 @@ module VX_miss_resrv #(
     // dequeue
     input wire                          dequeue
 );
+    `UNUSED_PARAM (CACHE_ID)
+    `UNUSED_PARAM (BANK_ID)
     localparam ADDRW = $clog2(MSHR_SIZE);
 
     reg [MSHR_SIZE-1:0][`LINE_ADDR_WIDTH-1:0] addr_table;

hw/rtl/cache/VX_shared_mem.v

@@ -49,6 +49,8 @@ module VX_shared_mem #(
 );
 
     `STATIC_ASSERT(NUM_BANKS <= NUM_REQS, ("invalid value"))
+    `UNUSED_PARAM (CACHE_ID)
+    `UNUSED_PARAM (CORE_TAG_ID_BITS)
 
     localparam CACHE_LINE_SIZE = WORD_SIZE;
 

hw/rtl/cache/VX_tag_access.v

@@ -31,6 +31,9 @@ module VX_tag_access #(
     input wire                          is_flush,
     output wire                         tag_match
 );
+
+    `UNUSED_PARAM (CACHE_ID)
+    `UNUSED_PARAM (BANK_ID)
     `UNUSED_VAR (reset)
     `UNUSED_VAR (lookup)
 

hw/rtl/interfaces/VX_dcache_core_req_if.v

@@ -6,8 +6,7 @@
 interface VX_dcache_core_req_if #(
     parameter NUM_REQS       = 1,
     parameter WORD_SIZE      = 1,
-    parameter CORE_TAG_WIDTH   = 1,
-    parameter CORE_TAG_ID_BITS = 0
+    parameter CORE_TAG_WIDTH = 1
 ) ();
 
     wire [NUM_REQS-1:0]                         valid;

hw/rtl/interfaces/VX_dcache_core_rsp_if.v

@@ -6,8 +6,7 @@
 interface VX_dcache_core_rsp_if #(
     parameter NUM_REQS       = 1,
     parameter WORD_SIZE      = 1,
-    parameter CORE_TAG_WIDTH   = 1,
-    parameter CORE_TAG_ID_BITS = 0
+    parameter CORE_TAG_WIDTH = 1
 ) ();
 
     wire [NUM_REQS-1:0]                     valid;    

hw/rtl/interfaces/VX_icache_core_req_if.v

@@ -5,8 +5,7 @@
 
 interface VX_icache_core_req_if #(
     parameter WORD_SIZE      = 1,
-    parameter CORE_TAG_WIDTH   = 1,
-    parameter CORE_TAG_ID_BITS = 0
+    parameter CORE_TAG_WIDTH = 1
 ) ();
 
     wire                        valid;

hw/rtl/interfaces/VX_icache_core_rsp_if.v

@@ -5,8 +5,7 @@
 
 interface VX_icache_core_rsp_if #(
     parameter WORD_SIZE      = 1,
-    parameter CORE_TAG_WIDTH   = 1,
-    parameter CORE_TAG_ID_BITS = 0
+    parameter CORE_TAG_WIDTH = 1
 ) ();
 
     wire                        valid;    

hw/rtl/libs/VX_dp_ram.v

@@ -8,7 +8,6 @@ module VX_dp_ram #(
     parameter BUFFERED = 0,
     parameter RWCHECK  = 1,
     parameter ADDRW    = $clog2(SIZE),
-    parameter SIZEW    = $clog2(SIZE+1),
     parameter FASTRAM  = 0,
     parameter INITZERO = 0
 ) ( 

hw/rtl/libs/VX_fixed_arbiter.v

@@ -14,6 +14,7 @@ module VX_fixed_arbiter #(
     output wire                     grant_valid
   );
 
+    `UNUSED_PARAM (LOCK_ENABLE)
     `UNUSED_VAR (clk)
     `UNUSED_VAR (reset)
     `UNUSED_VAR (enable)

hw/rtl/libs/VX_skid_buffer.v

@@ -4,8 +4,7 @@ module VX_skid_buffer #(
     parameter DATAW          = 1,
     parameter PASSTHRU       = 0,
     parameter NOBACKPRESSURE = 0,
-    parameter BUFFERED       = 0,
-    parameter FASTRAM        = 1
+    parameter BUFFERED       = 0
 ) ( 
     input  wire             clk,
     input  wire             reset,

hw/rtl/libs/VX_sp_ram.v

@@ -8,7 +8,6 @@ module VX_sp_ram #(
     parameter BUFFERED = 0,
     parameter RWCHECK  = 1,
     parameter ADDRW    = $clog2(SIZE),
-    parameter SIZEW    = $clog2(SIZE+1),
     parameter FASTRAM  = 0,
     parameter INITZERO = 0
 ) ( 

hw/simulate/verilator.vlt

@@ -7,3 +7,4 @@ lint_off -rule UNUSED -file "../rtl/fp_cores/fpnew/*"
 lint_off -rule LITENDIAN -file "../rtl/fp_cores/fpnew/*"
 lint_off -rule IMPORTSTAR -file "../rtl/fp_cores/fpnew/*"
 lint_off -rule PINCONNECTEMPTY -file "../rtl/fp_cores/fpnew/*"
+lint_off -file "../rtl/fp_cores/fpnew/*"