From 073964fdf7666e931af6dd6be41dbb1b43fc7e1b Mon Sep 17 00:00:00 2001 From: Blaise Tine Date: Fri, 12 Feb 2021 08:52:06 -0800 Subject: [PATCH] minor update --- hw/rtl/VX_config.vh | 2 +- hw/rtl/VX_csr_arb.v | 3 ++- hw/rtl/fp_cores/VX_fp_div.v | 16 +++++++++++++--- hw/rtl/fp_cores/VX_fp_sqrt.v | 16 +++++++++++++--- hw/rtl/libs/VX_stream_arbiter.v | 2 +- hw/syn/opae/README | 21 +++------------------ hw/syn/opae/vortex_afu.qsf | 29 +++++++++++++---------------- hw/syn/quartus/project.tcl | 29 +++++++++++++---------------- 8 files changed, 59 insertions(+), 59 deletions(-) diff --git a/hw/rtl/VX_config.vh b/hw/rtl/VX_config.vh index 4d1f5f9d..17e73064 100644 --- a/hw/rtl/VX_config.vh +++ b/hw/rtl/VX_config.vh @@ -313,7 +313,7 @@ // Miss Handling Register Size `ifndef DMSHR_SIZE -`define DMSHR_SIZE `LSUQ_SIZE +`define DMSHR_SIZE (`LSUQ_SIZE / 2) `endif // DRAM Request Queue Size diff --git a/hw/rtl/VX_csr_arb.v b/hw/rtl/VX_csr_arb.v index cd5e0079..2dc24028 100644 --- a/hw/rtl/VX_csr_arb.v +++ b/hw/rtl/VX_csr_arb.v @@ -66,7 +66,8 @@ module VX_csr_arb #( VX_stream_arbiter #( .NUM_REQS (NUM_REQS), .DATAW (RSP_DATAW), - .BUFFERED (BUFFERED_RSP) + .BUFFERED (BUFFERED_RSP), + .TYPE ("X") // fixed arbitration ) rsp_arb ( .clk (clk), .reset (reset), diff --git a/hw/rtl/fp_cores/VX_fp_div.v b/hw/rtl/fp_cores/VX_fp_div.v index 20150aab..69c8e93a 100644 --- a/hw/rtl/fp_cores/VX_fp_div.v +++ b/hw/rtl/fp_cores/VX_fp_div.v @@ -29,7 +29,17 @@ module VX_fp_div #( wire stall = ~ready_out && valid_out; wire enable = ~stall; - for (genvar i = 0; i < LANES; i++) begin + for (genvar i = 0; i < LANES; i++) begin + + wire fdiv_reset; + VX_reset_relay #( + .NUM_NODES(1) + ) reset_relay ( + .clk (clk), + .reset (reset), + .reset_o (fdiv_reset) + ); + `ifdef VERILATOR reg [31:0] r; fflags_t f; @@ -45,7 +55,7 @@ module VX_fp_div #( .RESETW (1) ) shift_req_dpi ( .clk (clk), - .reset (reset), + .reset (fdiv_reset), .enable (enable), .data_in (r), .data_out (result[i]) @@ -53,7 +63,7 @@ module VX_fp_div #( `else acl_fdiv fdiv ( .clk (clk), - .areset (reset), + .areset (fdiv_reset), .en (enable), .a (dataa[i]), .b (datab[i]), diff --git a/hw/rtl/fp_cores/VX_fp_sqrt.v b/hw/rtl/fp_cores/VX_fp_sqrt.v index 1b9df6a9..869da516 100644 --- a/hw/rtl/fp_cores/VX_fp_sqrt.v +++ b/hw/rtl/fp_cores/VX_fp_sqrt.v @@ -28,7 +28,17 @@ module VX_fp_sqrt #( wire stall = ~ready_out && valid_out; wire enable = ~stall; - for (genvar i = 0; i < LANES; i++) begin + for (genvar i = 0; i < LANES; i++) begin + + wire fsqrt_reset; + VX_reset_relay #( + .NUM_NODES(1) + ) reset_relay ( + .clk (clk), + .reset (reset), + .reset_o (fsqrt_reset) + ); + `ifdef VERILATOR reg [31:0] r; fflags_t f; @@ -44,7 +54,7 @@ module VX_fp_sqrt #( .RESETW (1) ) shift_req_dpi ( .clk (clk), - .reset (reset), + .reset (fsqrt_reset), .enable (enable), .data_in (r), .data_out (result[i]) @@ -52,7 +62,7 @@ module VX_fp_sqrt #( `else acl_fsqrt fsqrt ( .clk (clk), - .areset (reset), + .areset (fsqrt_reset), .en (enable), .a (dataa[i]), .q (result[i]) diff --git a/hw/rtl/libs/VX_stream_arbiter.v b/hw/rtl/libs/VX_stream_arbiter.v index 8aac0467..587a7435 100644 --- a/hw/rtl/libs/VX_stream_arbiter.v +++ b/hw/rtl/libs/VX_stream_arbiter.v @@ -16,7 +16,7 @@ module VX_stream_arbiter #( output wire valid_out, output wire [DATAW-1:0] data_out, input wire ready_out - ); +); localparam LOG_NUM_REQS = $clog2(NUM_REQS); diff --git a/hw/syn/opae/README b/hw/syn/opae/README index 7208c785..c7dea1fb 100644 --- a/hw/syn/opae/README +++ b/hw/syn/opae/README @@ -23,10 +23,10 @@ cd build_fpga && qsub-synth tail -n 10 ./build_fpga_1c/build.log # Check if the job is submitted to the queue and running. Status should be R -qstat | grep tinebp +qstat | grep # Constantly monitoring the job submitted to the queue. Stop this using Ctrl+C -watch ‘qstat | grep tinebp’ +watch ‘qstat | grep ’ # ## Executing on FPGA @@ -90,14 +90,6 @@ tar -cvjf trace.vcd.tar.bz2 trace.vcd run.log tar -zxvf vortex.vcd.tar.gz tar -xvf vortex.vcd.tar.bz2 -# launch Gtkwave -gtkwave ./build_ase_1c/work/vortex.vcd & - -# kill process by Users -ps -u tinebp -kill -9 -ps -u tinebp | grep "blackbox" | awk '{print $1}' | xargs kill -9 - # fixing device resource busy issue when deleting /build_ase_1c/ lsof +D build_ase_1c @@ -113,11 +105,4 @@ make -C top1 clean && make -C top1 > top1/build.log 2>&1 & make -C top2 clean && make -C top2 > top2/build.log 2>&1 & make -C top8 clean && make -C top8 > top8/build.log 2>&1 & make -C top16 clean && make -C top16 > top16/build.log 2>&1 & -make -C top32 clean && make -C top32 > top32/build.log 2>&1 & - -# How to calculate the maximum operating frequency? -200 Mhz -> period = 1/200x10^6 = 5ns -if slack = +1.664 -> minimal period = 5-1.664 = 3.336 -> fmax = 1/3.336 = 300 Mhz - -# build rtlsim from driver tests -make -C ../../rtlsim clean && reset && make -C ../../rtlsim \ No newline at end of file +make -C top32 clean && make -C top32 > top32/build.log 2>&1 & \ No newline at end of file diff --git a/hw/syn/opae/vortex_afu.qsf b/hw/syn/opae/vortex_afu.qsf index 438748ed..bb90d95c 100644 --- a/hw/syn/opae/vortex_afu.qsf +++ b/hw/syn/opae/vortex_afu.qsf @@ -10,19 +10,16 @@ set_global_assignment -name VERILOG_MACRO NDEBUG set_global_assignment -name MESSAGE_DISABLE 16818 set_global_assignment -name TIMEQUEST_DO_REPORT_TIMING ON -#set_global_assignment -name OPTIMIZATION_TECHNIQUE BALANCED -#set_global_assignment -name OPTIMIZATION_MODE "AGGRESSIVE PERFORMANCE" -#set_global_assignment -name FITTER_EFFORT "STANDARD FIT" -#set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS" -#set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL MAXIMUM -#set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON -#set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 -#set_global_assignment -name MAX_CORE_JUNCTION_TEMP 100 -#set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" -#set_global_assignment -name ROUTER_CLOCKING_TOPOLOGY_ANALYSIS ON -#set_global_assignment -name ROUTER_LCELL_INSERTION_AND_LOGIC_DUPLICATION ON -#set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL ON -#set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS ON -#set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON -#set_global_assignment -name POWER_USE_TA_VALUE 65 -#set_global_assignment -name SEED 1 \ No newline at end of file +set_global_assignment -name OPTIMIZATION_TECHNIQUE SPEED +set_global_assignment -name OPTIMIZATION_MODE "AGGRESSIVE PERFORMANCE" +set_global_assignment -name FITTER_EFFORT "STANDARD FIT" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON +set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL MAXIMUM +set_global_assignment -name ROUTER_CLOCKING_TOPOLOGY_ANALYSIS ON +set_global_assignment -name ROUTER_LCELL_INSERTION_AND_LOGIC_DUPLICATION ON +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS ON +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 100 +set_global_assignment -name SEED 1 \ No newline at end of file diff --git a/hw/syn/quartus/project.tcl b/hw/syn/quartus/project.tcl index a1573cf4..f8ba436c 100644 --- a/hw/syn/quartus/project.tcl +++ b/hw/syn/quartus/project.tcl @@ -45,22 +45,19 @@ set_global_assignment -name ALLOW_ANY_RAM_SIZE_FOR_RECOGNITION ON set_global_assignment -name USE_HIGH_SPEED_ADDER ON set_global_assignment -name MUX_RESTRUCTURE ON -#set_global_assignment -name OPTIMIZATION_TECHNIQUE SPEED -#set_global_assignment -name OPTIMIZATION_MODE "AGGRESSIVE PERFORMANCE" -#set_global_assignment -name FITTER_EFFORT "STANDARD FIT" -#set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS" -#set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL MAXIMUM -#set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON -#set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 -#set_global_assignment -name MAX_CORE_JUNCTION_TEMP 100 -#set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" -#set_global_assignment -name ROUTER_CLOCKING_TOPOLOGY_ANALYSIS ON -#set_global_assignment -name ROUTER_LCELL_INSERTION_AND_LOGIC_DUPLICATION ON -#set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL ON -#set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS ON -#set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON -#set_global_assignment -name POWER_USE_TA_VALUE 65 -#set_global_assignment -name SEED 1 +set_global_assignment -name OPTIMIZATION_TECHNIQUE SPEED +set_global_assignment -name OPTIMIZATION_MODE "AGGRESSIVE PERFORMANCE" +set_global_assignment -name FITTER_EFFORT "STANDARD FIT" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON +set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL MAXIMUM +set_global_assignment -name ROUTER_CLOCKING_TOPOLOGY_ANALYSIS ON +set_global_assignment -name ROUTER_LCELL_INSERTION_AND_LOGIC_DUPLICATION ON +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS ON +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 100 +set_global_assignment -name SEED 1 switch $opts(family) { "Arria 10" {