simx multicore fix
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@@ -21,6 +21,7 @@ Core::Core(const SimContext& ctx, const ArchDef &arch, Word id)
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, arch_(arch)
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, decoder_(arch)
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, mmu_(0, arch.wsize(), true)
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, smem_(RAM_PAGE_SIZE)
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, tex_units_(NUM_TEX_UNITS, this)
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, warps_(arch.num_warps())
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, barriers_(arch.num_barriers(), 0)
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@@ -380,7 +381,12 @@ Word Core::icache_read(Addr addr, Size size) {
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Word Core::dcache_read(Addr addr, Size size) {
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Word data;
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mmu_.read(&data, addr, size, 0);
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auto type = get_addr_type(addr, size);
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if (type == AddrType::Shared) {
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smem_.read(&data, addr & (SMEM_SIZE-1), size);
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} else {
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mmu_.read(&data, addr, size, 0);
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}
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return data;
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}
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@@ -389,7 +395,12 @@ void Core::dcache_write(Addr addr, Word data, Size size) {
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&& addr <= (IO_COUT_ADDR + IO_COUT_SIZE - 1)) {
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this->writeToStdOut(addr, data);
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} else {
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mmu_.write(&data, addr, size, 0);
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auto type = get_addr_type(addr, size);
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if (type == AddrType::Shared) {
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smem_.write(&data, addr & (SMEM_SIZE-1), size);
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} else {
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mmu_.write(&data, addr, size, 0);
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}
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}
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}
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