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few updates

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This commit is contained in:
Blaise Tine
2020-06-23 09:28:24 -07:00
parent f80e7c31de
commit 0a01385a2c
24 changed files with 228 additions and 226 deletions
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94
hw/rtl/VX_scope.vh
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@@ -4,6 +4,17 @@
`ifdef SCOPE
`define SCOPE_SIGNALS_DATA_LIST \
scope_dram_req_addr, \
scope_dram_req_rw, \
scope_dram_req_byteen, \
scope_dram_req_data, \
scope_dram_req_tag, \
scope_dram_rsp_data, \
scope_dram_rsp_tag, \
scope_snp_req_addr, \
scope_snp_req_invalidate, \
scope_snp_req_tag, \
scope_snp_rsp_tag, \
scope_icache_req_warp_num, \
scope_icache_req_addr, \
scope_icache_req_tag, \
@@ -18,17 +29,6 @@
scope_dcache_req_tag, \
scope_dcache_rsp_data, \
scope_dcache_rsp_tag, \
scope_dram_req_addr, \
scope_dram_req_rw, \
scope_dram_req_byteen, \
scope_dram_req_data, \
scope_dram_req_tag, \
scope_dram_rsp_data, \
scope_dram_rsp_tag, \
scope_snp_req_addr, \
scope_snp_req_invalidate, \
scope_snp_req_tag, \
scope_snp_rsp_tag, \
scope_decode_warp_num, \
scope_decode_curr_PC, \
scope_decode_is_jal, \
@@ -45,14 +45,6 @@
`define SCOPE_SIGNALS_UPD_LIST \
scope_icache_req_valid, \
scope_icache_req_ready, \
scope_icache_rsp_valid, \
scope_icache_rsp_ready, \
scope_dcache_req_valid, \
scope_dcache_req_ready, \
scope_dcache_rsp_valid, \
scope_dcache_rsp_ready, \
scope_dram_req_valid, \
scope_dram_req_ready, \
scope_dram_rsp_valid, \
@@ -61,6 +53,14 @@
scope_snp_req_ready, \
scope_snp_rsp_valid, \
scope_snp_rsp_ready, \
scope_icache_req_valid, \
scope_icache_req_ready, \
scope_icache_rsp_valid, \
scope_icache_rsp_ready, \
scope_dcache_req_valid, \
scope_dcache_req_ready, \
scope_dcache_rsp_valid, \
scope_dcache_rsp_ready, \
scope_decode_valid, \
scope_execute_valid, \
scope_writeback_valid, \
@@ -68,13 +68,27 @@
scope_memory_delay, \
scope_exec_delay, \
scope_gpr_stage_delay, \
scope_busy, \
scope_idram_req_valid, \
scope_idram_req_ready, \
scope_idram_rsp_valid, \
scope_idram_rsp_ready
scope_busy
`define SCOPE_SIGNALS_DECL \
wire scope_dram_req_valid; \
wire [31:0] scope_dram_req_addr; \
wire scope_dram_req_rw; \
wire [15:0] scope_dram_req_byteen; \
wire [31:0] scope_dram_req_data; \
wire [`VX_DRAM_TAG_WIDTH-1:0] scope_dram_req_tag; \
wire scope_dram_req_ready; \
wire scope_dram_rsp_valid; \
wire [31:0] scope_dram_rsp_data; \
wire [`VX_DRAM_TAG_WIDTH-1:0] scope_dram_rsp_tag; \
wire scope_dram_rsp_ready; \
wire scope_snp_req_valid; \
wire [31:0] scope_snp_req_addr; \
wire scope_snp_req_invalidate; \
wire [`VX_SNP_TAG_WIDTH-1:0] scope_snp_req_tag; \
wire scope_snp_req_ready; \
wire scope_snp_rsp_valid; \
wire [`VX_SNP_TAG_WIDTH-1:0] scope_snp_rsp_tag; \
wire scope_icache_req_valid; \
wire [`NW_BITS-1:0] scope_icache_req_warp_num; \
wire [31:0] scope_icache_req_addr; \
@@ -97,24 +111,6 @@
wire [31:0] scope_dcache_rsp_data; \
wire [`DCORE_TAG_WIDTH-1:0] scope_dcache_rsp_tag; \
wire scope_dcache_rsp_ready; \
wire scope_dram_req_valid; \
wire [31:0] scope_dram_req_addr; \
wire scope_dram_req_rw; \
wire [15:0] scope_dram_req_byteen; \
wire [31:0] scope_dram_req_data; \
wire [`VX_DRAM_TAG_WIDTH-1:0] scope_dram_req_tag; \
wire scope_dram_req_ready; \
wire scope_dram_rsp_valid; \
wire [31:0] scope_dram_rsp_data; \
wire [`VX_DRAM_TAG_WIDTH-1:0] scope_dram_rsp_tag; \
wire scope_dram_rsp_ready; \
wire scope_snp_req_valid; \
wire [31:0] scope_snp_req_addr; \
wire scope_snp_req_invalidate; \
wire [`VX_SNP_TAG_WIDTH-1:0] scope_snp_req_tag; \
wire scope_snp_req_ready; \
wire scope_snp_rsp_valid; \
wire [`VX_SNP_TAG_WIDTH-1:0] scope_snp_rsp_tag; \
wire scope_busy; \
wire scope_snp_rsp_ready; \
wire scope_schedule_delay; \
@@ -136,11 +132,7 @@
wire [`NW_BITS-1:0] scope_writeback_warp_num; \
wire [1:0] scope_writeback_wb; \
wire [4:0] scope_writeback_rd; \
wire [31:0] scope_writeback_data; \
wire scope_idram_req_valid; \
wire scope_idram_req_ready; \
wire scope_idram_rsp_valid; \
wire scope_idram_rsp_ready;
wire [31:0] scope_writeback_data;
`define SCOPE_SIGNALS_ISTAGE_IO \
output wire scope_icache_req_valid, \
@@ -171,10 +163,6 @@
`define SCOPE_SIGNALS_CORE_IO \
`define SCOPE_SIGNALS_ICACHE_IO \
output wire scope_idram_req_valid, \
output wire scope_idram_req_ready, \
output wire scope_idram_rsp_valid, \
output wire scope_idram_rsp_ready,
`define SCOPE_SIGNALS_PIPELINE_IO \
output wire scope_busy, \
@@ -230,10 +218,6 @@
`define SCOPE_SIGNALS_CORE_BIND \
`define SCOPE_SIGNALS_ICACHE_BIND \
.scope_idram_req_valid (scope_idram_req_valid), \
.scope_idram_req_ready (scope_idram_req_ready), \
.scope_idram_rsp_valid (scope_idram_rsp_valid), \
.scope_idram_rsp_ready (scope_idram_rsp_ready),
`define SCOPE_SIGNALS_PIPELINE_BIND \
.scope_busy (scope_busy), \