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ibuffer addition

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This commit is contained in:
Blaise Tine
2020-08-22 00:22:04 -07:00
parent 6c12391338
commit 0b355f228e
80 changed files with 1811 additions and 1528 deletions
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140
hw/rtl/VX_fpu_unit.v
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@@ -9,59 +9,81 @@ module VX_fpu_unit #(
// inputs
VX_fpu_req_if fpu_req_if,
VX_csr_to_fpu_if csr_to_fpu_if,
// outputs
VX_fpu_to_cmt_if fpu_commit_if
);
VX_fpu_req_if fpu_req_tmp_if();
);
localparam FPUQ_BITS = `LOG2UP(`FPUQ_SIZE);
// resolve dynamic FRM
wire [`FRM_BITS-1:0] frm, frm_tmp;
assign csr_to_fpu_if.wid = fpu_req_if.wid;
assign frm = (fpu_req_if.frm == `FRM_DYN) ? csr_to_fpu_if.frm : fpu_req_if.frm;
wire ready_in;
wire valid_out;
wire ready_out;
// use a skid buffer since fpcore has realtime backpressure
VX_elastic_buffer #(
.DATAW (`ISTAG_BITS + `NW_BITS + 32 + `FPU_BITS + `FRM_BITS + (3 * `NUM_THREADS * 32)),
.SIZE (0)
) input_buffer (
.clk (clk),
.reset (reset),
.valid_in (fpu_req_if.valid),
.ready_in (fpu_req_if.ready),
.data_in ({fpu_req_if.issue_tag, fpu_req_if.wid, fpu_req_if.curr_PC, fpu_req_if.op, frm, fpu_req_if.rs1_data, fpu_req_if.rs2_data, fpu_req_if.rs3_data}),
.data_out ({fpu_req_tmp_if.issue_tag, fpu_req_tmp_if.wid, fpu_req_tmp_if.curr_PC, fpu_req_tmp_if.op, frm_tmp, fpu_req_tmp_if.rs1_data, fpu_req_tmp_if.rs2_data, fpu_req_tmp_if.rs3_data}),
.ready_out (fpu_req_tmp_if.ready),
.valid_out (fpu_req_tmp_if.valid)
wire [`NW_BITS-1:0] rsp_wid;
wire [`NUM_THREADS-1:0] rsp_thread_mask;
wire [31:0] rsp_curr_PC;
wire [`NR_BITS-1:0] rsp_rd;
wire rsp_wb;
wire has_fflags;
fflags_t [`NUM_THREADS-1:0] fflags;
wire [`NUM_THREADS-1:0][31:0] result;
wire [FPUQ_BITS-1:0] tag_in, tag_out;
wire fpuq_full;
wire fpuq_push = fpu_req_if.valid && fpu_req_if.ready;
wire fpuq_pop = valid_out && ready_out;
VX_cam_buffer #(
.DATAW (`NW_BITS + `NUM_THREADS + 32 + `NR_BITS + 1),
.SIZE (`FPUQ_SIZE)
) mul_queue (
.clk (clk),
.reset (reset),
.acquire_slot (fpuq_push),
.write_addr (tag_in),
.read_addr (tag_out),
.release_addr (tag_out),
.write_data ({fpu_req_if.wid, fpu_req_if.thread_mask, fpu_req_if.curr_PC, fpu_req_if.rd, fpu_req_if.wb}),
.read_data ({rsp_wid, rsp_thread_mask, rsp_curr_PC, rsp_rd, rsp_wb}),
.release_slot (fpuq_pop),
.full (fpuq_full)
);
wire valid_in = fpu_req_if.valid && ~fpuq_full;
// can accept new request?
assign fpu_req_if.ready = ready_in && ~fpuq_full;
`ifdef SYNTHESIS
VX_fp_fpga fp_core (
VX_fp_fpga #(
.TAGW (FPUQ_BITS)
) fp_core (
.clk (clk),
.reset (reset),
.valid_in (fpu_req_tmp_if.valid),
.ready_in (fpu_req_tmp_if.ready),
.valid_in (valid_in),
.ready_in (ready_in),
.tag_in (fpu_req_tmp_if.issue_tag),
.tag_in (tag_in),
.op (fpu_req_tmp_if.op),
.frm (frm_tmp),
.op (fpu_req_if.op),
.frm (fpu_req_if.frm),
.dataa (fpu_req_tmp_if.rs1_data),
.datab (fpu_req_tmp_if.rs2_data),
.datac (fpu_req_tmp_if.rs3_data),
.result (fpu_commit_if.data),
.dataa (fpu_req_if.rs1_data),
.datab (fpu_req_if.rs2_data),
.datac (fpu_req_if.rs3_data),
.result (result),
.has_fflags (fpu_commit_if.has_fflags),
.fflags (fpu_commit_if.fflags),
.has_fflags (has_fflags),
.fflags (fflags),
.tag_out (fpu_commit_if.issue_tag),
.tag_out (tag_out),
.ready_out (1'b1),
.valid_out (fpu_commit_if.valid)
.ready_out (ready_out),
.valid_out (valid_out)
);
`else
@@ -70,33 +92,49 @@ module VX_fpu_unit #(
.FMULADD (1),
.FDIVSQRT (1),
.FNONCOMP (1),
.FCONV (1)
.FCONV (1),
.TAGW (FPUQ_BITS)
) fp_core (
.clk (clk),
.reset (reset),
.valid_in (fpu_req_tmp_if.valid),
.ready_in (fpu_req_tmp_if.ready),
.valid_in (valid_in),
.ready_in (ready_in),
.tag_in (fpu_req_tmp_if.issue_tag),
.tag_in (tag_in),
.op (fpu_req_tmp_if.op),
.frm (frm_tmp),
.op (fpu_req_if.op),
.frm (fpu_req_if.frm),
.dataa (fpu_req_tmp_if.rs1_data),
.datab (fpu_req_tmp_if.rs2_data),
.datac (fpu_req_tmp_if.rs3_data),
.result (fpu_commit_if.data),
.dataa (fpu_req_if.rs1_data),
.datab (fpu_req_if.rs2_data),
.datac (fpu_req_if.rs3_data),
.result (result),
.has_fflags (fpu_commit_if.has_fflags),
.fflags (fpu_commit_if.fflags),
.has_fflags (has_fflags),
.fflags (fflags),
.tag_out (fpu_commit_if.issue_tag),
.tag_out (tag_out),
.ready_out (1'b1),
.valid_out (fpu_commit_if.valid)
.ready_out (ready_out),
.valid_out (valid_out)
);
`endif
wire stall_out = ~fpu_commit_if.ready && fpu_commit_if.valid;
VX_generic_register #(
.N(1 + `NW_BITS + `NUM_THREADS + 32 + `NR_BITS + 1 + (`NUM_THREADS * 32) + 1 + (`NUM_THREADS * `FFG_BITS))
) fpu_reg (
.clk (clk),
.reset (reset),
.stall (stall_out),
.flush (1'b0),
.in ({valid_out, rsp_wid, rsp_thread_mask, rsp_curr_PC, rsp_rd, rsp_wb, result, has_fflags, fflags}),
.out ({fpu_commit_if.valid, fpu_commit_if.wid, fpu_commit_if.thread_mask, fpu_commit_if.curr_PC, fpu_commit_if.rd, fpu_commit_if.wb, fpu_commit_if.data, fpu_commit_if.has_fflags, fpu_commit_if.fflags})
);
assign ready_out = ~stall_out;
endmodule