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ibuffer addition

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This commit is contained in:
Blaise Tine
2020-08-22 00:22:04 -07:00
parent 6c12391338
commit 0b355f228e
80 changed files with 1811 additions and 1528 deletions
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91
hw/rtl/fp_cores/VX_fp_fpga.v
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@@ -1,14 +1,16 @@
`include "VX_define.vh"
`include "dspba_library_ver.sv"
module VX_fp_fpga (
module VX_fp_fpga #(
parameter TAGW = 1
) (
input wire clk,
input wire reset,
input wire valid_in,
output wire ready_in,
input wire [`ISTAG_BITS-1:0] tag_in,
input wire [TAGW-1:0] tag_in,
input wire [`FPU_BITS-1:0] op,
input wire [`FRM_BITS-1:0] frm,
@@ -21,7 +23,7 @@ module VX_fp_fpga (
output wire has_fflags,
output fflags_t [`NUM_THREADS-1:0] fflags,
output wire [`ISTAG_BITS-1:0] tag_out,
output wire [TAGW-1:0] tag_out,
input wire ready_out,
output wire valid_out
@@ -31,7 +33,7 @@ module VX_fp_fpga (
wire [NUM_FPC-1:0] per_core_ready_in;
wire [NUM_FPC-1:0][`NUM_THREADS-1:0][31:0] per_core_result;
wire [NUM_FPC-1:0][`ISTAG_BITS-1:0] per_core_tag_out;
wire [NUM_FPC-1:0][TAGW-1:0] per_core_tag_out;
wire [NUM_FPC-1:0] per_core_ready_out;
wire [NUM_FPC-1:0] per_core_valid_out;
@@ -62,7 +64,10 @@ module VX_fp_fpga (
endcase
end
VX_fp_noncomp fp_noncomp (
VX_fp_noncomp #(
.TAGW (TAGW),
.LANES(`NUM_THREADS)
) fp_noncomp (
.clk (clk),
.reset (reset),
.valid_in (valid_in && (core_select == 0)),
@@ -80,7 +85,10 @@ module VX_fp_fpga (
.valid_out (per_core_valid_out[0])
);
VX_fp_add fp_add (
VX_fp_add #(
.TAGW (TAGW),
.LANES(`NUM_THREADS)
) fp_add (
.clk (clk),
.reset (reset),
.valid_in (valid_in && (core_select == 1)),
@@ -94,7 +102,10 @@ module VX_fp_fpga (
.valid_out (per_core_valid_out[1])
);
VX_fp_sub fp_sub (
VX_fp_sub #(
.TAGW (TAGW),
.LANES(`NUM_THREADS)
) fp_sub (
.clk (clk),
.reset (reset),
.valid_in (valid_in && (core_select == 2)),
@@ -108,7 +119,10 @@ module VX_fp_fpga (
.valid_out (per_core_valid_out[2])
);
VX_fp_mul fp_mul (
VX_fp_mul #(
.TAGW (TAGW),
.LANES(`NUM_THREADS)
) fp_mul (
.clk (clk),
.reset (reset),
.valid_in (valid_in && (core_select == 3)),
@@ -122,7 +136,10 @@ module VX_fp_fpga (
.valid_out (per_core_valid_out[3])
);
VX_fp_madd fp_madd (
VX_fp_madd #(
.TAGW (TAGW),
.LANES(`NUM_THREADS)
) fp_madd (
.clk (clk),
.reset (reset),
.valid_in (valid_in && (core_select == 4)),
@@ -138,7 +155,10 @@ module VX_fp_fpga (
.valid_out (per_core_valid_out[4])
);
VX_fp_msub fp_msub (
VX_fp_msub #(
.TAGW (TAGW),
.LANES(`NUM_THREADS)
) fp_msub (
.clk (clk),
.reset (reset),
.valid_in (valid_in && (core_select == 5)),
@@ -154,7 +174,10 @@ module VX_fp_fpga (
.valid_out (per_core_valid_out[5])
);
VX_fp_div fp_div (
VX_fp_div #(
.TAGW (TAGW),
.LANES(`NUM_THREADS)
) fp_div (
.clk (clk),
.reset (reset),
.valid_in (valid_in && (core_select == 6)),
@@ -168,7 +191,10 @@ module VX_fp_fpga (
.valid_out (per_core_valid_out[6])
);
VX_fp_sqrt fp_sqrt (
VX_fp_sqrt #(
.TAGW (TAGW),
.LANES(`NUM_THREADS)
) fp_sqrt (
.clk (clk),
.reset (reset),
.valid_in (valid_in && (core_select == 7)),
@@ -181,7 +207,10 @@ module VX_fp_fpga (
.valid_out (per_core_valid_out[7])
);
VX_fp_ftoi fp_ftoi (
VX_fp_ftoi #(
.TAGW (TAGW),
.LANES(`NUM_THREADS)
) fp_ftoi (
.clk (clk),
.reset (reset),
.valid_in (valid_in && (core_select == 8)),
@@ -194,7 +223,10 @@ module VX_fp_fpga (
.valid_out (per_core_valid_out[8])
);
VX_fp_ftou fp_ftou (
VX_fp_ftou #(
.TAGW (TAGW),
.LANES(`NUM_THREADS)
) fp_ftou (
.clk (clk),
.reset (reset),
.valid_in (valid_in && (core_select == 9)),
@@ -207,7 +239,10 @@ module VX_fp_fpga (
.valid_out (per_core_valid_out[9])
);
VX_fp_itof fp_itof (
VX_fp_itof #(
.TAGW (TAGW),
.LANES(`NUM_THREADS)
) fp_itof (
.clk (clk),
.reset (reset),
.valid_in (valid_in && (core_select == 10)),
@@ -220,7 +255,10 @@ module VX_fp_fpga (
.valid_out (per_core_valid_out[10])
);
VX_fp_utof fp_utof (
VX_fp_utof #(
.TAGW (TAGW),
.LANES(`NUM_THREADS)
) fp_utof (
.clk (clk),
.reset (reset),
.valid_in (valid_in && (core_select == 11)),
@@ -248,21 +286,10 @@ module VX_fp_fpga (
assign per_core_ready_out[i] = ready_out && (i == fp_index);
end
wire tmp_valid = fp_valid;
wire [`ISTAG_BITS-1:0] tmp_tag = per_core_tag_out[fp_index];
wire [`NUM_THREADS-1:0][31:0] tmp_result = per_core_result[fp_index];
wire tmp_has_fflags = fpnew_has_fflags && (fp_index == 0);
fflags_t [`NUM_THREADS-1:0] tmp_flags = fpnew_fflags;
VX_generic_register #(
.N(1 + `ISTAG_BITS + (`NUM_THREADS * 32) + 1 + `FFG_BITS)
) nc_reg (
.clk (clk),
.reset (reset),
.stall (stall),
.flush (1'b0),
.in ({tmp_valid, tmp_tag, tmp_result, tmp_has_fflags, tmp_fflags}),
.out ({valid_out, tag_out, result, has_fflags, fflags})
);
assign valid_out = fp_valid;
assign tag_out = per_core_tag_out[fp_index];
assign result = per_core_result[fp_index];
assign has_fflags = fpnew_has_fflags && (fp_index == 0);
assign fflags = fpnew_fflags;
endmodule

55
hw/rtl/fp_cores/VX_fp_noncomp.v
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@@ -1,25 +1,28 @@
`include "VX_define.vh"
module VX_fp_noncomp (
module VX_fp_noncomp #(
parameter TAGW = 1,
parameter LANES = 1
) (
input wire clk,
input wire reset,
output wire ready_in,
input wire valid_in,
input wire [`ISTAG_BITS-1:0] tag_in,
input wire [TAGW-1:0] tag_in,
input wire [`FPU_BITS-1:0] op,
input wire [`FRM_BITS-1:0] frm,
input wire [`NUM_THREADS-1:0][31:0] dataa,
input wire [`NUM_THREADS-1:0][31:0] datab,
output wire [`NUM_THREADS-1:0][31:0] result,
input wire [LANES-1:0][31:0] dataa,
input wire [LANES-1:0][31:0] datab,
output wire [LANES-1:0][31:0] result,
output wire has_fflags,
output fflags_t [`NUM_THREADS-1:0] fflags,
output fflags_t [LANES-1:0] fflags,
output wire [`ISTAG_BITS-1:0] tag_out,
output wire [TAGW-1:0] tag_out,
input wire ready_out,
output wire valid_out
@@ -35,21 +38,21 @@ module VX_fp_noncomp (
SIG_NAN = 32'h00000100,
QUT_NAN = 32'h00000200;
wire [`NUM_THREADS-1:0] a_sign, b_sign;
wire [`NUM_THREADS-1:0][7:0] a_exponent, b_exponent;
wire [`NUM_THREADS-1:0][22:0] a_mantissa, b_mantissa;
fp_type_t [`NUM_THREADS-1:0] a_type, b_type;
wire [LANES-1:0] a_sign, b_sign;
wire [LANES-1:0][7:0] a_exponent, b_exponent;
wire [LANES-1:0][22:0] a_mantissa, b_mantissa;
fp_type_t [LANES-1:0] a_type, b_type;
wire [`NUM_THREADS-1:0] a_smaller, ab_equal;
wire [LANES-1:0] a_smaller, ab_equal;
reg [`NUM_THREADS-1:0][31:0] fclass_mask; // generate a 10-bit mask for integer reg
reg [`NUM_THREADS-1:0][31:0] fminmax_res; // result of fmin/fmax
reg [`NUM_THREADS-1:0][31:0] fsgnj_res; // result of sign injection
reg [`NUM_THREADS-1:0][31:0] fcmp_res; // result of comparison
reg [`NUM_THREADS-1:0][ 4:0] fcmp_excp; // exception of comparison
reg [LANES-1:0][31:0] fclass_mask; // generate a 10-bit mask for integer reg
reg [LANES-1:0][31:0] fminmax_res; // result of fmin/fmax
reg [LANES-1:0][31:0] fsgnj_res; // result of sign injection
reg [LANES-1:0][31:0] fcmp_res; // result of comparison
reg [LANES-1:0][ 4:0] fcmp_excp; // exception of comparison
// Setup
for (genvar i = 0; i < `NUM_THREADS; i++) begin
for (genvar i = 0; i < LANES; i++) begin
assign a_sign[i] = dataa[i][31];
assign a_exponent[i] = dataa[i][30:23];
assign a_mantissa[i] = dataa[i][22:0];
@@ -75,7 +78,7 @@ module VX_fp_noncomp (
end
// FCLASS
for (genvar i = 0; i < `NUM_THREADS; i++) begin
for (genvar i = 0; i < LANES; i++) begin
always @(*) begin
if (a_type[i].is_normal) begin
fclass_mask[i] = a_sign[i] ? NEG_NORM : POS_NORM;
@@ -99,7 +102,7 @@ module VX_fp_noncomp (
end
// Min/Max
for (genvar i = 0; i < `NUM_THREADS; i++) begin
for (genvar i = 0; i < LANES; i++) begin
always @(*) begin
if (a_type[i].is_nan && b_type[i].is_nan)
fminmax_res[i] = {1'b0, 8'hff, 1'b1, 22'd0}; // canonical qNaN
@@ -118,7 +121,7 @@ module VX_fp_noncomp (
end
// Sign Injection
for (genvar i = 0; i < `NUM_THREADS; i++) begin
for (genvar i = 0; i < LANES; i++) begin
always @(*) begin
case (op)
`FPU_SGNJ: fsgnj_res[i] = { b_sign[i], a_exponent[i], a_mantissa[i]};
@@ -130,7 +133,7 @@ module VX_fp_noncomp (
end
// Comparison
for (genvar i = 0; i < `NUM_THREADS; i++) begin
for (genvar i = 0; i < LANES; i++) begin
always @(*) begin
case (frm)
`FRM_RNE: begin
@@ -176,8 +179,8 @@ module VX_fp_noncomp (
reg tmp_valid;
reg tmp_has_fflags;
fflags_t [`NUM_THREADS-1:0] tmp_fflags;
reg [`NUM_THREADS-1:0][31:0] tmp_result;
fflags_t [LANES-1:0] tmp_fflags;
reg [LANES-1:0][31:0] tmp_result;
always @(*) begin
case (op)
@@ -191,7 +194,7 @@ module VX_fp_noncomp (
endcase
end
for (genvar i = 0; i < `NUM_THREADS; i++) begin
for (genvar i = 0; i < LANES; i++) begin
always @(*) begin
tmp_valid = 1'b1;
case (op)
@@ -228,7 +231,7 @@ module VX_fp_noncomp (
assign ready_in = ~stall;
VX_generic_register #(
.N(1 + `ISTAG_BITS + (`NUM_THREADS * 32) + 1 + (`NUM_THREADS * `FFG_BITS))
.N(1 + TAGW + (LANES * 32) + 1 + (LANES * `FFG_BITS))
) nc_reg (
.clk (clk),
.reset (reset),

16
hw/rtl/fp_cores/VX_fpnew.v
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@@ -3,6 +3,7 @@
`include "defs_div_sqrt_mvp.sv"
module VX_fpnew #(
parameter TAGW = 1,
parameter FMULADD = 1,
parameter FDIVSQRT = 1,
parameter FNONCOMP = 1,
@@ -14,7 +15,7 @@ module VX_fpnew #(
input wire valid_in,
output wire ready_in,
input wire [`ISTAG_BITS-1:0] tag_in,
input wire [TAGW-1:0] tag_in,
input wire [`FPU_BITS-1:0] op,
input wire [`FRM_BITS-1:0] frm,
@@ -27,7 +28,7 @@ module VX_fpnew #(
output wire has_fflags,
output fflags_t [`NUM_THREADS-1:0] fflags,
output wire [`ISTAG_BITS-1:0] tag_out,
output wire [TAGW-1:0] tag_out,
input wire ready_out,
output wire valid_out
@@ -66,7 +67,7 @@ module VX_fpnew #(
wire fpu_ready_in, fpu_valid_in;
wire fpu_ready_out, fpu_valid_out;
reg [`ISTAG_BITS-1:0] fpu_tag_in, fpu_tag_out;
reg [TAGW-1:0] fpu_tag_in, fpu_tag_out;
reg [2:0][`NUM_THREADS-1:0][31:0] fpu_operands;
@@ -77,9 +78,6 @@ module VX_fpnew #(
wire [`NUM_THREADS-1:0][31:0] fpu_result;
fpnew_pkg::status_t [0:`NUM_THREADS-1] fpu_status;
wire is_class_op, is_class_op_out;
assign is_class_op = (op == `FPU_CLASS);
reg [FOP_BITS-1:0] fpu_op;
reg [`FRM_BITS-1:0] fpu_rnd;
reg fpu_op_mod;
@@ -136,7 +134,7 @@ module VX_fpnew #(
fpnew_top #(
.Features (FPU_FEATURES),
.Implementation (FPU_IMPLEMENTATION),
.TagType (logic[`ISTAG_BITS+1+1-1:0])
.TagType (logic[TAGW+1+1-1:0])
) fpnew_core (
.clk_i (clk),
.rst_ni (1'b1),
@@ -148,13 +146,13 @@ module VX_fpnew #(
.dst_fmt_i (fpnew_pkg::fp_format_e'(fpu_dst_fmt)),
.int_fmt_i (fpnew_pkg::int_format_e'(fpu_int_fmt)),
.vectorial_op_i (1'b0),
.tag_i ({fpu_tag_in, fpu_has_fflags, is_class_op}),
.tag_i ({fpu_tag_in, fpu_has_fflags}),
.in_valid_i (fpu_valid_in),
.in_ready_o (fpu_ready_in),
.flush_i (reset),
.result_o (fpu_result[0]),
.status_o (fpu_status[0]),
.tag_o ({fpu_tag_out, fpu_has_fflags_out, is_class_op_out}),
.tag_o ({fpu_tag_out, fpu_has_fflags_out}),
.out_valid_o (fpu_valid_out),
.out_ready_i (fpu_ready_out),
`UNUSED_PIN (busy_o)

19
hw/rtl/fp_cores/altera/VX_fp_add.v
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@@ -1,19 +1,22 @@
`include "VX_define.vh"
module VX_fp_add (
module VX_fp_add #(
parameter TAGW = 1,
parameter LANES = 1
) (
input wire clk,
input wire reset,
output wire ready_in,
input wire valid_in,
input wire [`ISTAG_BITS-1:0] tag_in,
input wire [TAGW-1:0] tag_in,
input wire [`NUM_THREADS-1:0][31:0] dataa,
input wire [`NUM_THREADS-1:0][31:0] datab,
output wire [`NUM_THREADS-1:0][31:0] result,
input wire [LANES-1:0][31:0] dataa,
input wire [LANES-1:0][31:0] datab,
output wire [LANES-1:0][31:0] result,
output wire [`ISTAG_BITS-1:0] tag_out,
output wire [TAGW-1:0] tag_out,
input wire ready_out,
output wire valid_out
@@ -22,7 +25,7 @@ module VX_fp_add (
wire enable = ~stall;
assign ready_in = enable;
for (genvar i = 0; i < `NUM_THREADS; i++) begin
for (genvar i = 0; i < LANES; i++) begin
twentynm_fp_mac mac_fp_wys (
// inputs
.accumulate(),
@@ -65,7 +68,7 @@ module VX_fp_add (
end
VX_shift_register #(
.DATAW(`ISTAG_BITS + 1),
.DATAW(TAGW + 1),
.DEPTH(1)
) shift_reg (
.clk(clk),

19
hw/rtl/fp_cores/altera/VX_fp_div.v
View File

@@ -1,19 +1,22 @@
`include "VX_define.vh"
module VX_fp_div (
module VX_fp_div #(
parameter TAGW = 1,
parameter LANES = 1
) (
input wire clk,
input wire reset,
output wire ready_in,
input wire valid_in,
input wire [`ISTAG_BITS-1:0] tag_in,
input wire [TAGW-1:0] tag_in,
input wire [`NUM_THREADS-1:0][31:0] dataa,
input wire [`NUM_THREADS-1:0][31:0] datab,
output wire [`NUM_THREADS-1:0][31:0] result,
input wire [LANES-1:0][31:0] dataa,
input wire [LANES-1:0][31:0] datab,
output wire [LANES-1:0][31:0] result,
output wire [`ISTAG_BITS-1:0] tag_out,
output wire [TAGW-1:0] tag_out,
input wire ready_out,
output wire valid_out
@@ -22,7 +25,7 @@ module VX_fp_div (
wire enable = ~stall;
assign ready_in = enable;
for (genvar i = 0; i < `NUM_THREADS; i++) begin
for (genvar i = 0; i < LANES; i++) begin
acl_fp_div fdiv (
.clk (clk),
.areset (1'b0),
@@ -34,7 +37,7 @@ module VX_fp_div (
end
VX_shift_register #(
.DATAW(`ISTAG_BITS + 1),
.DATAW(TAGW + 1),
.DEPTH(`LATENCY_FDIV)
) shift_reg (
.clk(clk),

17
hw/rtl/fp_cores/altera/VX_fp_ftoi.v
View File

@@ -1,18 +1,21 @@
`include "VX_define.vh"
module VX_fp_ftoi (
module VX_fp_ftoi #(
parameter TAGW = 1,
parameter LANES = 1
) (
input wire clk,
input wire reset,
output wire ready_in,
input wire valid_in,
input wire [`ISTAG_BITS-1:0] tag_in,
input wire [TAGW-1:0] tag_in,
input wire [`NUM_THREADS-1:0][31:0] dataa,
output wire [`NUM_THREADS-1:0][31:0] result,
input wire [LANES-1:0][31:0] dataa,
output wire [LANES-1:0][31:0] result,
output wire [`ISTAG_BITS-1:0] tag_out,
output wire [TAGW-1:0] tag_out,
input wire ready_out,
output wire valid_out
@@ -21,7 +24,7 @@ module VX_fp_ftoi (
wire enable = ~stall;
assign ready_in = enable;
for (genvar i = 0; i < `NUM_THREADS; i++) begin
for (genvar i = 0; i < LANES; i++) begin
acl_fp_ftoi ftoi (
.clk (clk),
.areset (1'b0),
@@ -32,7 +35,7 @@ module VX_fp_ftoi (
end
VX_shift_register #(
.DATAW(`ISTAG_BITS + 1),
.DATAW(TAGW + 1),
.DEPTH(`LATENCY_FTOI)
) shift_reg (
.clk(clk),

17
hw/rtl/fp_cores/altera/VX_fp_ftou.v
View File

@@ -1,18 +1,21 @@
`include "VX_define.vh"
module VX_fp_ftou (
module VX_fp_ftou #(
parameter TAGW = 1,
parameter LANES = 1
) (
input wire clk,
input wire reset,
output wire ready_in,
input wire valid_in,
input wire [`ISTAG_BITS-1:0] tag_in,
input wire [TAGW-1:0] tag_in,
input wire [`NUM_THREADS-1:0][31:0] dataa,
output wire [`NUM_THREADS-1:0][31:0] result,
input wire [LANES-1:0][31:0] dataa,
output wire [LANES-1:0][31:0] result,
output wire [`ISTAG_BITS-1:0] tag_out,
output wire [TAGW-1:0] tag_out,
input wire ready_out,
output wire valid_out
@@ -21,7 +24,7 @@ module VX_fp_ftou (
wire enable = ~stall;
assign ready_in = enable;
for (genvar i = 0; i < `NUM_THREADS; i++) begin
for (genvar i = 0; i < LANES; i++) begin
acl_fp_ftou ftou (
.clk (clk),
.areset (1'b0),
@@ -32,7 +35,7 @@ module VX_fp_ftou (
end
VX_shift_register #(
.DATAW(`ISTAG_BITS + 1),
.DATAW(TAGW + 1),
.DEPTH(`LATENCY_FTOU)
) shift_reg (
.clk(clk),

17
hw/rtl/fp_cores/altera/VX_fp_itof.v
View File

@@ -1,18 +1,21 @@
`include "VX_define.vh"
module VX_fp_itof (
module VX_fp_itof #(
parameter TAGW = 1,
parameter LANES = 1
) (
input wire clk,
input wire reset,
output wire ready_in,
input wire valid_in,
input wire [`ISTAG_BITS-1:0] tag_in,
input wire [TAGW-1:0] tag_in,
input wire [`NUM_THREADS-1:0][31:0] dataa,
output wire [`NUM_THREADS-1:0][31:0] result,
input wire [LANES-1:0][31:0] dataa,
output wire [LANES-1:0][31:0] result,
output wire [`ISTAG_BITS-1:0] tag_out,
output wire [TAGW-1:0] tag_out,
input wire ready_out,
output wire valid_out
@@ -21,7 +24,7 @@ module VX_fp_itof (
wire enable = ~stall;
assign ready_in = enable;
for (genvar i = 0; i < `NUM_THREADS; i++) begin
for (genvar i = 0; i < LANES; i++) begin
acl_fp_itof itof (
.clk (clk),
.areset (1'b0),
@@ -32,7 +35,7 @@ module VX_fp_itof (
end
VX_shift_register #(
.DATAW(`ISTAG_BITS + 1),
.DATAW(TAGW + 1),
.DEPTH(`LATENCY_ITOF)
) shift_reg (
.clk(clk),

27
hw/rtl/fp_cores/altera/VX_fp_madd.v
View File

@@ -1,22 +1,25 @@
`include "VX_define.vh"
module VX_fp_madd (
module VX_fp_madd #(
parameter TAGW = 1,
parameter LANES = 1
) (
input wire clk,
input wire reset,
output wire ready_in,
input wire valid_in,
input wire [`ISTAG_BITS-1:0] tag_in,
input wire [TAGW-1:0] tag_in,
input wire [`NUM_THREADS-1:0][31:0] dataa,
input wire [`NUM_THREADS-1:0][31:0] datab,
input wire [`NUM_THREADS-1:0][31:0] datac,
output wire [`NUM_THREADS-1:0][31:0] result,
input wire [LANES-1:0][31:0] dataa,
input wire [LANES-1:0][31:0] datab,
input wire [LANES-1:0][31:0] datac,
output wire [LANES-1:0][31:0] result,
input wire negate,
output wire [`ISTAG_BITS-1:0] tag_out,
output wire [TAGW-1:0] tag_out,
input wire ready_out,
output wire valid_out
@@ -24,11 +27,11 @@ module VX_fp_madd (
wire enable0, enable1;
assign ready_in = enable0 && enable1;
wire [`NUM_THREADS-1:0][31:0] result_st0, result_st1;
wire [`ISTAG_BITS-1:0] out_tag_st0, out_tag_st1;
wire [LANES-1:0][31:0] result_st0, result_st1;
wire [TAGW-1:0] out_tag_st0, out_tag_st1;
wire in_valid_st0, out_valid_st0, out_valid_st1;
for (genvar i = 0; i < `NUM_THREADS; i++) begin
for (genvar i = 0; i < LANES; i++) begin
twentynm_fp_mac mac_fp_wys0 (
// inputs
.accumulate(),
@@ -111,7 +114,7 @@ module VX_fp_madd (
end
VX_shift_register #(
.DATAW(`ISTAG_BITS + 1 + 1),
.DATAW(TAGW + 1 + 1),
.DEPTH(1)
) shift_reg0 (
.clk(clk),
@@ -122,7 +125,7 @@ module VX_fp_madd (
);
VX_shift_register #(
.DATAW(`ISTAG_BITS + 1),
.DATAW(TAGW + 1),
.DEPTH(1)
) shift_reg1 (
.clk(clk),

27
hw/rtl/fp_cores/altera/VX_fp_msub.v
View File

@@ -1,22 +1,25 @@
`include "VX_define.vh"
module VX_fp_msub (
module VX_fp_msub #(
parameter TAGW = 1,
parameter LANES = 1
) (
input wire clk,
input wire reset,
output wire ready_in,
input wire valid_in,
input wire [`ISTAG_BITS-1:0] tag_in,
input wire [TAGW-1:0] tag_in,
input wire [`NUM_THREADS-1:0][31:0] dataa,
input wire [`NUM_THREADS-1:0][31:0] datab,
input wire [`NUM_THREADS-1:0][31:0] datac,
output wire [`NUM_THREADS-1:0][31:0] result,
input wire [LANES-1:0][31:0] dataa,
input wire [LANES-1:0][31:0] datab,
input wire [LANES-1:0][31:0] datac,
output wire [LANES-1:0][31:0] result,
input wire negate,
output wire [`ISTAG_BITS-1:0] tag_out,
output wire [TAGW-1:0] tag_out,
input wire ready_out,
output wire valid_out
@@ -24,11 +27,11 @@ module VX_fp_msub (
wire enable0, enable1;
assign ready_in = enable0 && enable1;
wire [`NUM_THREADS-1:0][31:0] result_st0, result_st1;
wire [`ISTAG_BITS-1:0] out_tag_st0, out_tag_st1;
wire [LANES-1:0][31:0] result_st0, result_st1;
wire [TAGW-1:0] out_tag_st0, out_tag_st1;
wire in_valid_st0, out_valid_st0, out_valid_st1;
for (genvar i = 0; i < `NUM_THREADS; i++) begin
for (genvar i = 0; i < LANES; i++) begin
twentynm_fp_mac mac_fp_wys0 (
// inputs
.accumulate(),
@@ -111,7 +114,7 @@ module VX_fp_msub (
end
VX_shift_register #(
.DATAW(`ISTAG_BITS + 1 + 1),
.DATAW(TAGW + 1 + 1),
.DEPTH(1)
) shift_reg0 (
.clk(clk),
@@ -122,7 +125,7 @@ module VX_fp_msub (
);
VX_shift_register #(
.DATAW(`ISTAG_BITS + 1),
.DATAW(TAGW + 1),
.DEPTH(1)
) shift_reg1 (
.clk(clk),

19
hw/rtl/fp_cores/altera/VX_fp_mul.v
View File

@@ -1,19 +1,22 @@
`include "VX_define.vh"
module VX_fp_mul (
module VX_fp_mul #(
parameter TAGW = 1,
parameter LANES = 1
) (
input wire clk,
input wire reset,
output wire ready_in,
input wire valid_in,
input wire [`ISTAG_BITS-1:0] tag_in,
input wire [TAGW-1:0] tag_in,
input wire [`NUM_THREADS-1:0][31:0] dataa,
input wire [`NUM_THREADS-1:0][31:0] datab,
output wire [`NUM_THREADS-1:0][31:0] result,
input wire [LANES-1:0][31:0] dataa,
input wire [LANES-1:0][31:0] datab,
output wire [LANES-1:0][31:0] result,
output wire [`ISTAG_BITS-1:0] tag_out,
output wire [TAGW-1:0] tag_out,
input wire ready_out,
output wire valid_out
@@ -22,7 +25,7 @@ module VX_fp_mul (
wire enable = ~stall;
assign ready_in = enable;
for (genvar i = 0; i < `NUM_THREADS; i++) begin
for (genvar i = 0; i < LANES; i++) begin
twentynm_fp_mac mac_fp_wys (
// inputs
.accumulate(),
@@ -65,7 +68,7 @@ module VX_fp_mul (
end
VX_shift_register #(
.DATAW(`ISTAG_BITS + 1),
.DATAW(TAGW + 1),
.DEPTH(1)
) shift_reg (
.clk(clk),

17
hw/rtl/fp_cores/altera/VX_fp_sqrt.v
View File

@@ -1,18 +1,21 @@
`include "VX_define.vh"
module VX_fp_sqrt (
module VX_fp_sqrt #(
parameter TAGW = 1,
parameter LANES = 1
) (
input wire clk,
input wire reset,
output wire ready_in,
input wire valid_in,
input wire [`ISTAG_BITS-1:0] tag_in,
input wire [TAGW-1:0] tag_in,
input wire [`NUM_THREADS-1:0][31:0] dataa,
output wire [`NUM_THREADS-1:0][31:0] result,
input wire [LANES-1:0][31:0] dataa,
output wire [LANES-1:0][31:0] result,
output wire [`ISTAG_BITS-1:0] tag_out,
output wire [TAGW-1:0] tag_out,
input wire ready_out,
output wire valid_out
@@ -21,7 +24,7 @@ module VX_fp_sqrt (
wire enable = ~stall;
assign ready_in = enable;
for (genvar i = 0; i < `NUM_THREADS; i++) begin
for (genvar i = 0; i < LANES; i++) begin
acl_fp_sqrt fsqrt (
.clk (clk),
.areset (1'b0),
@@ -32,7 +35,7 @@ module VX_fp_sqrt (
end
VX_shift_register #(
.DATAW(`ISTAG_BITS + 1),
.DATAW(TAGW + 1),
.DEPTH(`LATENCY_FSQRT)
) shift_reg (
.clk(clk),

19
hw/rtl/fp_cores/altera/VX_fp_sub.v
View File

@@ -1,19 +1,22 @@
`include "VX_define.vh"
module VX_fp_sub (
module VX_fp_sub #(
parameter TAGW = 1,
parameter LANES = 1
) (
input wire clk,
input wire reset,
output wire ready_in,
input wire valid_in,
input wire [`ISTAG_BITS-1:0] tag_in,
input wire [TAGW-1:0] tag_in,
input wire [`NUM_THREADS-1:0][31:0] dataa,
input wire [`NUM_THREADS-1:0][31:0] datab,
output wire [`NUM_THREADS-1:0][31:0] result,
input wire [LANES-1:0][31:0] dataa,
input wire [LANES-1:0][31:0] datab,
output wire [LANES-1:0][31:0] result,
output wire [`ISTAG_BITS-1:0] tag_out,
output wire [TAGW-1:0] tag_out,
input wire ready_out,
output wire valid_out
@@ -22,7 +25,7 @@ module VX_fp_sub (
wire enable = ~stall;
assign ready_in = enable;
for (genvar i = 0; i < `NUM_THREADS; i++) begin
for (genvar i = 0; i < LANES; i++) begin
twentynm_fp_mac mac_fp_wys (
// inputs
.accumulate(),
@@ -65,7 +68,7 @@ module VX_fp_sub (
end
VX_shift_register #(
.DATAW(`ISTAG_BITS + 1),
.DATAW(TAGW + 1),
.DEPTH(1)
) shift_reg (
.clk(clk),

17
hw/rtl/fp_cores/altera/VX_fp_utof.v
View File

@@ -1,18 +1,21 @@
`include "VX_define.vh"
module VX_fp_utof (
module VX_fp_utof #(
parameter TAGW = 1,
parameter LANES = 1
) (
input wire clk,
input wire reset,
output wire ready_in,
input wire valid_in,
input wire [`ISTAG_BITS-1:0] tag_in,
input wire [TAGW-1:0] tag_in,
input wire [`NUM_THREADS-1:0][31:0] dataa,
output wire [`NUM_THREADS-1:0][31:0] result,
input wire [LANES-1:0][31:0] dataa,
output wire [LANES-1:0][31:0] result,
output wire [`ISTAG_BITS-1:0] tag_out,
output wire [TAGW-1:0] tag_out,
input wire ready_out,
output wire valid_out
@@ -21,7 +24,7 @@ module VX_fp_utof (
wire enable = ~stall;
assign ready_in = enable;
for (genvar i = 0; i < `NUM_THREADS; i++) begin
for (genvar i = 0; i < LANES; i++) begin
acl_fp_utof utof (
.clk (clk),
.areset (1'b0),
@@ -32,7 +35,7 @@ module VX_fp_utof (
end
VX_shift_register #(
.DATAW(`ISTAG_BITS + 1),
.DATAW(TAGW + 1),
.DEPTH(`LATENCY_UTOF)
) shift_reg (
.clk(clk),