From 0bec734532936978d9345ce0de3a00f5b16368bd Mon Sep 17 00:00:00 2001
From: Blaise Tine <tinebp@yahoo.com>
Date: Thu, 15 Jul 2021 14:16:05 -0700
Subject: [PATCH] icache readonly optimization

---
 hw/rtl/cache/VX_bank.v        | 2 +-
 hw/rtl/cache/VX_data_access.v | 6 ++++--
 2 files changed, 5 insertions(+), 3 deletions(-)

diff --git a/hw/rtl/cache/VX_bank.v b/hw/rtl/cache/VX_bank.v
index d82ef98d..13dfc32c 100644
--- a/hw/rtl/cache/VX_bank.v
+++ b/hw/rtl/cache/VX_bank.v
@@ -247,7 +247,7 @@ module VX_bank #(
             mrsq_enable || flush_enable,
             mshr_enable ? 1'b0 : creq_rw,
             mshr_enable ? mshr_addr : (mem_rsp_valid ? mem_rsp_addr : (flush_enable ? `LINE_ADDR_WIDTH'(flush_addr) : creq_addr)),
-            mem_rsp_valid ? mem_rsp_data : creq_line_data,
+            (mem_rsp_valid || !WRITE_ENABLE) ? mem_rsp_data : creq_line_data,
             mshr_enable ? mshr_wsel : creq_wsel,
             mshr_enable ? mshr_byteen : creq_byteen,
             mshr_enable ? mshr_tid : creq_tid,
diff --git a/hw/rtl/cache/VX_data_access.v b/hw/rtl/cache/VX_data_access.v
index 265fa327..9bfaf4c7 100644
--- a/hw/rtl/cache/VX_data_access.v
+++ b/hw/rtl/cache/VX_data_access.v
@@ -45,16 +45,18 @@ module VX_data_access #(
     `UNUSED_VAR (reset)
     `UNUSED_VAR (readen)
 
+    localparam BYTEENW = WRITE_ENABLE ? CACHE_LINE_SIZE : 1;
+
     wire [`LINE_SELECT_BITS-1:0] line_addr;
     wire [CACHE_LINE_SIZE-1:0] byte_enable;
     
     assign line_addr = addr[`LINE_SELECT_BITS-1:0];
-    assign byte_enable = (WRITE_ENABLE && !is_fill) ? byteen : {CACHE_LINE_SIZE{1'b1}};
+    assign byte_enable = is_fill ? {CACHE_LINE_SIZE{1'b1}} : byteen;
 
     VX_sp_ram #(
         .DATAW   (CACHE_LINE_SIZE * 8),
         .SIZE    (`LINES_PER_BANK),
-        .BYTEENW (CACHE_LINE_SIZE),
+        .BYTEENW (BYTEENW),
         .RWCHECK (1)
     ) data_store (
         .clk(clk),