wu-arch/vortex
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

opae rtl fixes

Browse Source
This commit is contained in:
Blaise Tine
2020-05-17 20:29:42 -07:00
parent 26f9fc96c3
commit 11ace25f27
9 changed files with 66 additions and 38 deletions
Download Patch File Download Diff File Expand all files Collapse all files

12
hw/rtl/cache/VX_bank.v vendored
View File

@@ -244,9 +244,6 @@ module VX_bank #(
wire st2_pending_hazard_st1e;
wire force_request_miss_st1e;
wire[`LINE_ADDR_WIDTH-1:0] miss_add_addr;
wire[`BASE_ADDR_BITS-1:0] miss_add_wsel;
wire[`WORD_WIDTH-1:0] miss_add_data;
wire[`REQS_BITS-1:0] miss_add_tid;
wire[`REQ_TAG_WIDTH-1:0] miss_add_tag;
wire[`BYTE_EN_BITS-1:0] miss_add_mem_read;
@@ -386,6 +383,7 @@ module VX_bank #(
wire is_snp_st1e;
wire snp_to_mrvq_st1e;
wire mrvq_init_ready_state_st1e;
wire miss_add_because_miss;
assign is_snp_st1e = is_snp_st1[STAGE_1_CYCLES-1];
@@ -482,7 +480,7 @@ module VX_bank #(
`DEBUG_END
// Enqueue to miss reserv if it's a valid miss
wire miss_add_because_miss = valid_st2 && !is_snp_st2 && miss_st2;
assign miss_add_because_miss = valid_st2 && !is_snp_st2 && miss_st2;
wire miss_add_because_pending = snp_to_mrvq_st2;
wire miss_add_unqual = (miss_add_because_miss || miss_add_because_pending);
@@ -494,9 +492,9 @@ module VX_bank #(
|| dwbq_push_stall
|| dram_fill_req_stall);
wire miss_add_addr = addr_st2;
wire miss_add_wsel = wsel_st2;
wire miss_add_data = writeword_st2;
wire [`LINE_ADDR_WIDTH-1:0] miss_add_addr = addr_st2;
wire [`BASE_ADDR_BITS-1:0] miss_add_wsel = wsel_st2;
wire [`WORD_WIDTH-1:0] miss_add_data = writeword_st2;
assign {miss_add_tag, miss_add_mem_read, miss_add_mem_write, miss_add_tid} = inst_meta_st2;
wire miss_add_is_snp = is_snp_st2;

10
hw/rtl/cache/VX_cache_miss_resrv.v vendored
View File

@@ -66,11 +66,9 @@ module VX_cache_miss_resrv #(
wire enqueue_possible = !miss_resrv_full;
wire [`LOG2UP(MRVQ_SIZE)-1:0] enqueue_index = tail_ptr;
wire qual_mrvq_init = mrvq_push && mrvq_init_ready_state;
`IGNORE_WARNINGS_BEGIN
`IGNORE_WARNINGS_BEGIN
wire [31:0] make_ready_push_full;
`IGNORE_WARNINGS_END
`IGNORE_WARNINGS_END
reg [MRVQ_SIZE-1:0] make_ready;
reg [MRVQ_SIZE-1:0] make_ready_push;
@@ -79,7 +77,7 @@ module VX_cache_miss_resrv #(
genvar i;
generate
for (i = 0; i < MRVQ_SIZE; i++) begin
assign valid_address_match[i] = valid_table[i] && (addr_table[i] == fill_addr_st1);
assign valid_address_match[i] = valid_table[i] && (addr_table[i] === fill_addr_st1);
assign make_ready[i] = is_fill_st1 && valid_address_match[i];
end
endgenerate
@@ -98,6 +96,8 @@ module VX_cache_miss_resrv #(
wire update_ready = (|make_ready);
wire qual_mrvq_init = mrvq_push && mrvq_init_ready_state;
assign make_ready_push_full = ({31'b0, qual_mrvq_init} << enqueue_index);
assign make_ready_push = make_ready_push_full[MRVQ_SIZE-1:0];

2
hw/rtl/cache/VX_snp_forwarder.v vendored
View File

@@ -1,4 +1,4 @@
`include "VX_define.vh"
`include "VX_cache_config.vh"
module VX_snp_forwarder #(
parameter BANK_LINE_SIZE = 0,