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register file refactoring

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This commit is contained in:
Blaise Tine
2020-12-05 01:40:50 -08:00
parent 478d971389
commit 13a5370254
33 changed files with 524 additions and 605 deletions
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12
hw/rtl/VX_writeback.v
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@@ -78,12 +78,12 @@ module VX_writeback #(
.N(1 + `NW_BITS + 32 + `NUM_THREADS + `NR_BITS + (`NUM_THREADS * 32)),
.R(1)
) pipe_reg (
.clk (clk),
.reset (reset),
.stall (stall),
.flush (1'b0),
.in ({wb_valid, wb_wid, wb_PC, wb_tmask, wb_rd, wb_data}),
.out ({writeback_if.valid, writeback_if.wid, writeback_if.PC, writeback_if.tmask, writeback_if.rd, writeback_if.data})
.clk (clk),
.reset (reset),
.stall (stall),
.flush (1'b0),
.data_in ({wb_valid, wb_wid, wb_PC, wb_tmask, wb_rd, wb_data}),
.data_out ({writeback_if.valid, writeback_if.wid, writeback_if.PC, writeback_if.tmask, writeback_if.rd, writeback_if.data})
);
assign alu_commit_if.ready = !stall;