moved apae sources into rtl/afu
This commit is contained in:
Blaise Tine
48
hw/rtl/afu/ccip_interface_reg.sv
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48
hw/rtl/afu/ccip_interface_reg.sv
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// Code reused from Intel OPAE's 04_local_memory sample program with changes made to fit Vortex
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// Register all interface signals
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import ccip_if_pkg::*;
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module ccip_interface_reg(
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// CCI-P Clocks and Resets
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input logic pClk, // 400MHz - CC-P clock domain. Primary Clock
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input logic pck_cp2af_softReset_T0, // CCI-P ACTIVE HIGH Soft Reset
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input logic [1:0] pck_cp2af_pwrState_T0, // CCI-P AFU Power State
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input logic pck_cp2af_error_T0, // CCI-P Protocol Error Detected
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// Interface structures
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input t_if_ccip_Rx pck_cp2af_sRx_T0, // CCI-P Rx Port
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input t_if_ccip_Tx pck_af2cp_sTx_T0, // CCI-P Tx Port
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output logic pck_cp2af_softReset_T1,
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output logic [1:0] pck_cp2af_pwrState_T1,
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output logic pck_cp2af_error_T1,
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output t_if_ccip_Rx pck_cp2af_sRx_T1,
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output t_if_ccip_Tx pck_af2cp_sTx_T1
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);
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(* preserve *) logic pck_cp2af_softReset_T0_q;
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(* preserve *) logic [1:0] pck_cp2af_pwrState_T0_q;
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(* preserve *) logic pck_cp2af_error_T0_q;
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(* preserve *) t_if_ccip_Rx pck_cp2af_sRx_T0_q;
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(* preserve *) t_if_ccip_Tx pck_af2cp_sTx_T0_q;
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always@(posedge pClk)
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begin
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pck_cp2af_softReset_T0_q <= pck_cp2af_softReset_T0;
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pck_cp2af_pwrState_T0_q <= pck_cp2af_pwrState_T0;
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pck_cp2af_error_T0_q <= pck_cp2af_error_T0;
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pck_cp2af_sRx_T0_q <= pck_cp2af_sRx_T0;
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pck_af2cp_sTx_T0_q <= pck_af2cp_sTx_T0;
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end
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always_comb
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begin
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pck_cp2af_softReset_T1 = pck_cp2af_softReset_T0_q;
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pck_cp2af_pwrState_T1 = pck_cp2af_pwrState_T0_q;
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pck_cp2af_error_T1 = pck_cp2af_error_T0_q;
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pck_cp2af_sRx_T1 = pck_cp2af_sRx_T0_q;
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pck_af2cp_sTx_T1 = pck_af2cp_sTx_T0_q;
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end
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endmodule
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167
hw/rtl/afu/ccip_std_afu.sv
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167
hw/rtl/afu/ccip_std_afu.sv
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// Code reused from Intel OPAE's 04_local_memory sample program with changes made to fit Vortex
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// Top Level Vortex Driver
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// To be done:
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// Check how to run this with OPAE. Looks like setup issue
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`include "platform_if.vh"
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import local_mem_cfg_pkg::*;
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module ccip_std_afu #(
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parameter NUM_LOCAL_MEM_BANKS = 2
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) (
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// CCI-P Clocks and Resets
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input logic pClk, // Primary CCI-P interface clock.
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input logic pClkDiv2, // Aligned, pClk divided by 2.
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input logic pClkDiv4, // Aligned, pClk divided by 4.
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input logic uClk_usr, // User clock domain. Refer to clock programming guide.
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input logic uClk_usrDiv2, // Aligned, user clock divided by 2.
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input logic pck_cp2af_softReset, // CCI-P ACTIVE HIGH Soft Reset
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input logic [1:0] pck_cp2af_pwrState, // CCI-P AFU Power State
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input logic pck_cp2af_error, // CCI-P Protocol Error Detected
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// CCI-P structures
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input t_if_ccip_Rx pck_cp2af_sRx, // CCI-P Rx Port
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output t_if_ccip_Tx pck_af2cp_sTx, // CCI-P Tx Port
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// Local memory interface
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avalon_mem_if.to_fiu local_mem[NUM_LOCAL_MEM_BANKS]
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);
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// ====================================================================
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// Pick the proper clk and reset, as chosen by the AFU's JSON file
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// ====================================================================
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// The platform may transform the CCI-P clock from pClk to a clock
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// chosen in the AFU's JSON file.
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logic clk;
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assign clk = `PLATFORM_PARAM_CCI_P_CLOCK;
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logic reset;
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assign reset = `PLATFORM_PARAM_CCI_P_RESET;
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// ====================================================================
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// Register signals at interface before consuming them
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// ====================================================================
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(* noprune *) logic [1:0] cp2af_pwrState_T1;
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(* noprune *) logic cp2af_error_T1;
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logic reset_T1;
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t_if_ccip_Rx cp2af_sRx_T1;
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t_if_ccip_Tx af2cp_sTx_T0;
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ccip_interface_reg inst_green_ccip_interface_reg
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(
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.pClk (clk),
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.pck_cp2af_softReset_T0 (reset),
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.pck_cp2af_pwrState_T0 (pck_cp2af_pwrState),
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.pck_cp2af_error_T0 (pck_cp2af_error),
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.pck_cp2af_sRx_T0 (pck_cp2af_sRx),
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.pck_af2cp_sTx_T0 (af2cp_sTx_T0),
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.pck_cp2af_softReset_T1 (reset_T1),
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.pck_cp2af_pwrState_T1 (cp2af_pwrState_T1),
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.pck_cp2af_error_T1 (cp2af_error_T1),
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.pck_cp2af_sRx_T1 (cp2af_sRx_T1),
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.pck_af2cp_sTx_T1 (pck_af2cp_sTx)
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);
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// ====================================================================
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// User AFU goes here
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// ====================================================================
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//
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// vortex_afu depends on CCI-P and local memory being in the same
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// clock domain. This is accomplished by choosing a common clock
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// in the AFU's JSON description. The platform instantiates clock-
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// crossing shims automatically, as needed.
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//
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//
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// Memory banks are used very simply here. Only bank is active at
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// a time, selected by mem_bank_select. mem_bank_select is set
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// by a CSR from the host.
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//
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t_local_mem_byte_mask avs_byteenable;
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logic avs_waitrequest;
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t_local_mem_data avs_readdata;
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logic avs_readdatavalid;
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t_local_mem_burst_cnt avs_burstcount;
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t_local_mem_data avs_writedata;
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t_local_mem_addr avs_address;
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logic avs_write;
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logic avs_read;
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// choose which memory bank to test
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logic [$clog2(NUM_LOCAL_MEM_BANKS)-1:0] mem_bank_select;
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vortex_afu #(
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.NUM_LOCAL_MEM_BANKS(NUM_LOCAL_MEM_BANKS)
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) afu (
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.clk (clk),
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.reset (reset_T1),
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.avs_writedata (avs_writedata),
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.avs_readdata (avs_readdata),
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.avs_address (avs_address),
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.avs_waitrequest (avs_waitrequest),
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.avs_write (avs_write),
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.avs_read (avs_read),
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.avs_byteenable (avs_byteenable),
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.avs_burstcount (avs_burstcount),
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.avs_readdatavalid (avs_readdatavalid),
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.mem_bank_select (mem_bank_select),
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.cp2af_sRxPort (cp2af_sRx_T1),
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.af2cp_sTxPort (af2cp_sTx_T0)
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);
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//
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// Export the local memory interface signals as vectors so that bank
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// selection can use array syntax.
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//
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logic avs_waitrequest_v[NUM_LOCAL_MEM_BANKS];
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t_local_mem_data avs_readdata_v[NUM_LOCAL_MEM_BANKS];
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logic avs_readdatavalid_v[NUM_LOCAL_MEM_BANKS];
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genvar b;
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generate
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for (b = 0; b < NUM_LOCAL_MEM_BANKS; b = b + 1)
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begin : lmb
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always_comb
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begin
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// Local memory to AFU signals
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avs_waitrequest_v[b] = local_mem[b].waitrequest;
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avs_readdata_v[b] = local_mem[b].readdata;
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avs_readdatavalid_v[b] = local_mem[b].readdatavalid;
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// Replicate address and write data to all banks. Only
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// the request signals have to be bank-specific.
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local_mem[b].burstcount = avs_burstcount;
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local_mem[b].writedata = avs_writedata;
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local_mem[b].address = avs_address;
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local_mem[b].byteenable = avs_byteenable;
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// Request a write to this bank?
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local_mem[b].write = avs_write &&
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($bits(mem_bank_select)'(b) == mem_bank_select);
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// Request a read from this bank?
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local_mem[b].read = avs_read &&
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($bits(mem_bank_select)'(b) == mem_bank_select);
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end
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end
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endgenerate
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assign avs_waitrequest = avs_waitrequest_v[mem_bank_select];
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assign avs_readdata = avs_readdata_v[mem_bank_select];
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assign avs_readdatavalid = avs_readdatavalid_v[mem_bank_select];
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endmodule
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