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potential deadlock

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This commit is contained in:
Richard Yan
2024-05-07 13:56:51 -07:00
parent 1e5dff52c1
commit 14d1552f08
2 changed files with 11 additions and 11 deletions
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18
hw/VX_config.h
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@@ -1,5 +1,5 @@
// auto-generated by gen_config.py. DO NOT EDIT // auto-generated by gen_config.py. DO NOT EDIT
// Generated at 2024-04-08 12:40:13.594321 // Generated at 2024-05-07 13:55:58.398687
// Translated from ./rtl/VX_config.vh: // Translated from ./rtl/VX_config.vh:
@@ -243,7 +243,7 @@
// Issue width // Issue width
#ifndef ISSUE_WIDTH #ifndef ISSUE_WIDTH
#define ISSUE_WIDTH MIN(NUM_WARPS, 4) #define ISSUE_WIDTH NUM_WARPS
#endif #endif
// Number of ALU units // Number of ALU units
@@ -251,7 +251,7 @@
#define NUM_ALU_LANES NUM_THREADS #define NUM_ALU_LANES NUM_THREADS
#endif #endif
#ifndef NUM_ALU_BLOCKS #ifndef NUM_ALU_BLOCKS
#define NUM_ALU_BLOCKS ISSUE_WIDTH #define NUM_ALU_BLOCKS 4
#endif #endif
// Number of FPU units // Number of FPU units
@@ -259,12 +259,12 @@
#define NUM_FPU_LANES NUM_THREADS #define NUM_FPU_LANES NUM_THREADS
#endif #endif
#ifndef NUM_FPU_BLOCKS #ifndef NUM_FPU_BLOCKS
#define NUM_FPU_BLOCKS ISSUE_WIDTH #define NUM_FPU_BLOCKS 2
#endif #endif
// Number of LSU units // Number of LSU units
#ifndef NUM_LSU_LANES #ifndef NUM_LSU_LANES
#define NUM_LSU_LANES MIN(NUM_THREADS, 4) #define NUM_LSU_LANES NUM_THREADS
#endif #endif
// Number of SFU units // Number of SFU units
@@ -274,12 +274,12 @@
// Size of Instruction Buffer // Size of Instruction Buffer
#ifndef IBUF_SIZE #ifndef IBUF_SIZE
#define IBUF_SIZE (8 * (NUM_WARPS / ISSUE_WIDTH)) #define IBUF_SIZE (4 * ISSUE_WIDTH)
#endif #endif
// Size of LSU Request Queue // Size of LSU Request Queue
#ifndef LSUQ_SIZE #ifndef LSUQ_SIZE
#define LSUQ_SIZE (8 * (NUM_THREADS / NUM_LSU_LANES)) #define LSUQ_SIZE (4 * NUM_WARPS * (NUM_THREADS / NUM_LSU_LANES))
#endif #endif
// LSU Duplicate Address Check // LSU Duplicate Address Check
@@ -464,7 +464,7 @@
// Number of Banks // Number of Banks
#ifndef DCACHE_NUM_BANKS #ifndef DCACHE_NUM_BANKS
#define DCACHE_NUM_BANKS MIN(NUM_LSU_LANES, 4) #define DCACHE_NUM_BANKS NUM_LSU_LANES
#endif #endif
// Core Response Queue Size // Core Response Queue Size
@@ -474,7 +474,7 @@
// Miss Handling Register Size // Miss Handling Register Size
#ifndef DCACHE_MSHR_SIZE #ifndef DCACHE_MSHR_SIZE
#define DCACHE_MSHR_SIZE 16 #define DCACHE_MSHR_SIZE 8
#endif #endif
// Memory Request Queue Size // Memory Request Queue Size

4
hw/rtl/core/VX_smem_unit.sv
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@@ -124,8 +124,8 @@ module VX_smem_unit import VX_gpu_pkg::*; #(
.TAG_WIDTH (DCACHE_TAG_WIDTH), .TAG_WIDTH (DCACHE_TAG_WIDTH),
.TAG_SEL_IDX (0), .TAG_SEL_IDX (0),
.ARBITER ("P"), .ARBITER ("P"),
.OUT_REG_REQ (2), .OUT_REG_REQ (0),
.OUT_REG_RSP (2) .OUT_REG_RSP (0)
) smem_switch ( ) smem_switch (
.clk (clk), .clk (clk),
.reset (switch_reset), .reset (switch_reset),