L2 and L1 using different block size support, RTLsim fixes, dram_rsp_ready optimization

2020-11-21 09:47:56 -08:00
parent a7da36c007
commit 1795980a52
50 changed files with 972 additions and 952 deletions
--- a/hw/rtl/interfaces/VX_cache_dram_req_if.v
+++ b/hw/rtl/interfaces/VX_cache_dram_req_if.v
@@ -10,11 +10,13 @@ interface VX_cache_dram_req_if #(
 ) ();

    wire                           valid;
+    
    wire                           rw;    
    wire [(DRAM_LINE_WIDTH/8)-1:0] byteen;
    wire [DRAM_ADDR_WIDTH-1:0]     addr;
    wire [DRAM_LINE_WIDTH-1:0]     data;  
-    wire [DRAM_TAG_WIDTH-1:0]      tag;    
+    wire [DRAM_TAG_WIDTH-1:0]      tag;   
+
    wire                           ready;

 endinterface