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Less expensive but slower fetch logic

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This commit is contained in:
felsabbagh3
2019-05-05 22:55:47 -04:00
parent f21eaec79f
commit 191ed73415
28 changed files with 904 additions and 1672 deletions
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134
rtl/VX_fetch.v
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@@ -26,24 +26,9 @@ module VX_fetch (
);
reg stall_reg;
reg delay_reg;
reg[31:0] old;
reg[4:0] state;
reg[31:0] real_PC;
reg[31:0] JAL_reg;
reg[31:0] BR_reg;
reg prev_debug;
reg delay;
reg[31:0] PC_to_use;
reg[31:0] PC_to_use_temp;
reg stall;
reg[31:0] temp_PC;
reg[31:0] out_PC;
reg[4:0] temp_state;
reg[4:0] tempp_state;
reg valid[`NT_M1:0];
@@ -55,14 +40,6 @@ module VX_fetch (
for (ini_cur_th = 1; ini_cur_th < `NT; ini_cur_th=ini_cur_th+1)
valid[ini_cur_th] = 0; // Thread 1 active
valid[0] = 1;
stall_reg = 0;
delay_reg = 0;
old = 0;
state = 0;
real_PC = 0;
JAL_reg = 0;
BR_reg = 0;
prev_debug = 0;
end
@@ -73,41 +50,11 @@ module VX_fetch (
end
end
always @(*) begin
case(state)
5'h00: PC_to_use_temp = real_PC;
5'h01: PC_to_use_temp = JAL_reg;
5'h02: PC_to_use_temp = BR_reg;
5'h03: PC_to_use_temp = real_PC;
5'h04: PC_to_use_temp = old;
default: PC_to_use_temp = 32'h0;
endcase // state
end
assign out_delay = 0;
assign delay = out_delay;
always @(*) begin
if ((delay_reg == 1'b1) && (in_freeze == 1'b0)) begin
// $display("Using old cuz delay: PC: %h",old);
PC_to_use = old;
end else if (in_debug == 1'b1) begin
if (prev_debug == 1'b1) begin
PC_to_use = old;
end else begin
PC_to_use = real_PC;
end
end else if (stall_reg == 1'b1) begin
// $display("Using old cuz stall: PC: %h\treal_pc: %h",old, real_PC);
PC_to_use = old;
end else begin
PC_to_use = PC_to_use_temp;
end
end
assign stall = in_clone_stall || in_branch_stall || in_fwd_stall || in_branch_stall_exe || in_interrupt || delay || in_freeze;
assign stall = in_clone_stall || in_branch_stall || in_fwd_stall || in_branch_stall_exe || in_interrupt || in_freeze || in_debug;
assign out_instruction = stall ? 32'b0 : in_instruction;
// assign out_instruction = in_instruction;
@@ -118,81 +65,30 @@ module VX_fetch (
endgenerate
// assign out_valid[0] = stall ? 1'b0 : valid[0];
// assign out_valid[1] = stall ? 1'b0 : valid[1];
always @(*) begin
wire[31:0] warp_pc;
VX_warp VX_Warp(
.clk (clk),
.reset (reset),
.stall (stall),
.in_jal (in_jal),
.in_jal_dest (in_jal_dest),
.in_branch_dir (in_branch_dir),
.in_branch_dest(in_branch_dest),
.out_PC (warp_pc)
);
if ((in_jal == 1'b1) && (delay_reg == 1'b0)) begin
temp_PC = in_jal_dest;
// $display("in_jal_dest: %h",in_jal_dest);
end else if ((in_branch_dir == 1'b1) && (delay_reg == 1'b0)) begin
temp_PC = in_branch_dest;
end else begin
temp_PC = PC_to_use;
end
end
assign out_PC = temp_PC;
assign out_PC = warp_pc;
// always @(*) begin
// $display("FETCH PC: %h (%h, %h, %h)",temp_PC, PC_to_use, in_jal_dest, in_branch_dest);
// $display("FETCH PC: %h (%h, %h, %h)",delete, delete, in_jal_dest, in_branch_dest);
// end
always @(*) begin
if (in_jal == 1'b1) begin
temp_state = 5'h1;
end else if (in_branch_dir == 1'b1) begin
temp_state = 5'h2;
end else begin
temp_state = 5'h0;
end
end
assign tempp_state = in_interrupt ? 5'h3 : temp_state;
assign out_curr_PC = out_PC;
always @(posedge clk or posedge reset) begin
if(reset) begin
state <= 0;
stall_reg <= 0;
delay_reg <= 0;
old <= 0;
real_PC <= 0;
JAL_reg <= 0;
BR_reg <= 0;
prev_debug <= 0;
end else begin
if (in_debug == 1'b1) begin
state <= 5'h3;
end else begin
if (prev_debug == 1'b1) begin
state <= 5'h4;
end else begin
state <= tempp_state;
end
end
stall_reg <= stall;
delay_reg <= delay || in_freeze;
old <= out_PC;
real_PC <= PC_to_use + 32'h4;
JAL_reg <= in_jal_dest + 32'h4;
BR_reg <= in_branch_dest + 32'h4;
prev_debug <= in_debug;
end
end
// always @(*) begin