From 1a2823da0d4dcee7354921fcc469ef549b6cf50d Mon Sep 17 00:00:00 2001 From: Blaise Tine Date: Mon, 20 Apr 2020 13:52:24 -0400 Subject: [PATCH] RTL code refactoring --- hw/modelsim/vortex_tb.v | 2 +- hw/opae/vortex_afu.sv | 2 +- hw/rtl/VX_alu.v | 151 +++++++++--------- hw/rtl/VX_back_end.v | 22 +-- hw/rtl/VX_csr_data.v | 38 ++--- hw/rtl/VX_csr_pipe.v | 16 +- hw/rtl/VX_execute_unit.v | 29 ++-- hw/rtl/VX_fetch.v | 6 +- hw/rtl/VX_front_end.v | 12 +- hw/rtl/VX_gpr.v | 28 ++-- hw/rtl/VX_gpr_stage.v | 4 +- hw/rtl/VX_gpr_wrapper.v | 33 ++-- hw/rtl/VX_lsu.v | 10 +- hw/rtl/VX_warp_scheduler.v | 4 +- hw/rtl/VX_writeback.v | 12 +- hw/rtl/Vortex.v | 8 +- hw/rtl/Vortex_Cluster.v | 8 +- hw/rtl/Vortex_Socket.v | 12 +- hw/rtl/cache/VX_bank.v | 20 +-- hw/rtl/cache/VX_cache_dfq_queue.v | 4 +- hw/rtl/cache/VX_cache_req_queue.v | 4 +- hw/rtl/cache/VX_prefetcher.v | 4 +- hw/rtl/libs/VX_generic_queue.v | 16 +- hw/rtl/pipe_regs/VX_d_e_reg.v | 10 +- hw/rtl/pipe_regs/VX_f_d_reg.v | 8 +- hw/rtl/pipe_regs/VX_i_d_reg.v | 8 +- hw/rtl/shared_memory/VX_priority_encoder_sm.v | 4 +- hw/rtl/shared_memory/VX_shared_memory.v | 12 +- hw/simulate/simulator.cpp | 4 +- hw/unit_tests/generic_queue/testbench.v | 4 +- simX/cache_simX.v | 18 +-- 31 files changed, 253 insertions(+), 260 deletions(-) diff --git a/hw/modelsim/vortex_tb.v b/hw/modelsim/vortex_tb.v index b57f97cf..4521244a 100644 --- a/hw/modelsim/vortex_tb.v +++ b/hw/modelsim/vortex_tb.v @@ -116,7 +116,7 @@ reg[31:0] io_data; .o_m_read_or_write_i (o_m_read_or_write_i), .i_m_readdata_i (i_m_readdata_i), .i_m_ready_i (i_m_ready_i), - .out_ebreak (out_ebreak) + .ebreak_o (out_ebreak) ); always @(negedge clk) begin diff --git a/hw/opae/vortex_afu.sv b/hw/opae/vortex_afu.sv index cab7ab48..07ad5ad3 100644 --- a/hw/opae/vortex_afu.sv +++ b/hw/opae/vortex_afu.sv @@ -570,7 +570,7 @@ Vortex_Socket #() vx_socket ( .llc_snp_req_ready (vx_snp_req_ready), // program exit signal - .out_ebreak (vx_ebreak) + .ebreak (vx_ebreak) ); endmodule diff --git a/hw/rtl/VX_alu.v b/hw/rtl/VX_alu.v index 3bb23f4c..805856fe 100644 --- a/hw/rtl/VX_alu.v +++ b/hw/rtl/VX_alu.v @@ -1,18 +1,18 @@ `include "VX_define.vh" -module VX_alu( - input wire clk, - input wire reset, - input wire[31:0] in_1, - input wire[31:0] in_2, - input wire in_rs2_src, - input wire[31:0] in_itype_immed, - input wire[19:0] in_upper_immed, - input wire[4:0] in_alu_op, - input wire[31:0] in_curr_PC, - output reg[31:0] out_alu_result, - output reg out_alu_stall - ); +module VX_alu ( + input wire clk, + input wire reset, + input wire[31:0] a_i, + input wire[31:0] b_i, + input wire rs2_src_i, + input wire[31:0] itype_immed_i, + input wire[19:0] upper_immed_i, + input wire[4:0] alu_op_i, + input wire[31:0] curr_PC_i, + output reg[31:0] alu_result_o, + output reg alu_stall_o +); localparam div_pipeline_len = 20; localparam mul_pipeline_len = 8; @@ -79,19 +79,18 @@ module VX_alu( // MUL, MULH (signed*signed), MULHSU (signed*unsigned), MULHU (unsigned*unsigned) wire[63:0] alu_in1_signed = {{32{ALU_in1[31]}}, ALU_in1}; wire[63:0] alu_in2_signed = {{32{ALU_in2[31]}}, ALU_in2}; - assign mul_data_a = (in_alu_op == `MULHU) ? {32'b0, ALU_in1} : alu_in1_signed; - assign mul_data_b = (in_alu_op == `MULHU || in_alu_op == `MULHSU) ? {32'b0, ALU_in2} : alu_in2_signed; - + assign mul_data_a = (alu_op_i == `MULHU) ? {32'b0, ALU_in1} : alu_in1_signed; + assign mul_data_b = (alu_op_i == `MULHU || alu_op_i == `MULHSU) ? {32'b0, ALU_in2} : alu_in2_signed; reg [15:0] curr_inst_delay; reg [15:0] inst_delay; reg inst_was_stalling; wire inst_delay_stall = inst_was_stalling ? inst_delay != 0 : curr_inst_delay != 0; - assign out_alu_stall = inst_delay_stall; + assign alu_stall_o = inst_delay_stall; always @(*) begin - case(in_alu_op) + case(alu_op_i) `DIV, `DIVU, `REM, @@ -101,7 +100,7 @@ module VX_alu( `MULHSU, `MULHU: curr_inst_delay = mul_pipeline_len; default: curr_inst_delay = 0; - endcase // in_alu_op + endcase // alu_op_i end always @(posedge clk) begin @@ -128,39 +127,39 @@ module VX_alu( wire which_in2; wire[31:0] upper_immed; - assign which_in2 = in_rs2_src == `RS2_IMMED; + assign which_in2 = rs2_src_i == `RS2_IMMED; - assign ALU_in1 = in_1; - assign ALU_in2 = which_in2 ? in_itype_immed : in_2; + assign ALU_in1 = a_i; + assign ALU_in2 = which_in2 ? itype_immed_i : b_i; - assign upper_immed = {in_upper_immed, {12{1'b0}}}; + assign upper_immed = {upper_immed_i, {12{1'b0}}}; always @(*) begin - case(in_alu_op) - `ADD: out_alu_result = $signed(ALU_in1) + $signed(ALU_in2); - `SUB: out_alu_result = $signed(ALU_in1) - $signed(ALU_in2); - `SLLA: out_alu_result = ALU_in1 << ALU_in2[4:0]; - `SLT: out_alu_result = ($signed(ALU_in1) < $signed(ALU_in2)) ? 32'h1 : 32'h0; - `SLTU: out_alu_result = ALU_in1 < ALU_in2 ? 32'h1 : 32'h0; - `XOR: out_alu_result = ALU_in1 ^ ALU_in2; - `SRL: out_alu_result = ALU_in1 >> ALU_in2[4:0]; - `SRA: out_alu_result = $signed(ALU_in1) >>> ALU_in2[4:0]; - `OR: out_alu_result = ALU_in1 | ALU_in2; - `AND: out_alu_result = ALU_in2 & ALU_in1; - `SUBU: out_alu_result = (ALU_in1 >= ALU_in2) ? 32'h0 : 32'hffffffff; - `LUI_ALU: out_alu_result = upper_immed; - `AUIPC_ALU: out_alu_result = $signed(in_curr_PC) + $signed(upper_immed); + case(alu_op_i) + `ADD: alu_result_o = $signed(ALU_in1) + $signed(ALU_in2); + `SUB: alu_result_o = $signed(ALU_in1) - $signed(ALU_in2); + `SLLA: alu_result_o = ALU_in1 << ALU_in2[4:0]; + `SLT: alu_result_o = ($signed(ALU_in1) < $signed(ALU_in2)) ? 32'h1 : 32'h0; + `SLTU: alu_result_o = ALU_in1 < ALU_in2 ? 32'h1 : 32'h0; + `XOR: alu_result_o = ALU_in1 ^ ALU_in2; + `SRL: alu_result_o = ALU_in1 >> ALU_in2[4:0]; + `SRA: alu_result_o = $signed(ALU_in1) >>> ALU_in2[4:0]; + `OR: alu_result_o = ALU_in1 | ALU_in2; + `AND: alu_result_o = ALU_in2 & ALU_in1; + `SUBU: alu_result_o = (ALU_in1 >= ALU_in2) ? 32'h0 : 32'hffffffff; + `LUI_ALU: alu_result_o = upper_immed; + `AUIPC_ALU: alu_result_o = $signed(curr_PC_i) + $signed(upper_immed); // TODO profitable to roll these exceptional cases into inst_delay to avoid pipeline when possible? - `MUL: out_alu_result = mul_result[31:0]; - `MULH: out_alu_result = mul_result[63:32]; - `MULHSU: out_alu_result = mul_result[63:32]; - `MULHU: out_alu_result = mul_result[63:32]; - `DIV: out_alu_result = (ALU_in2 == 0) ? 32'hffffffff : signed_div_result; - `DIVU: out_alu_result = (ALU_in2 == 0) ? 32'hffffffff : unsigned_div_result; - `REM: out_alu_result = (ALU_in2 == 0) ? ALU_in1 : signed_rem_result; - `REMU: out_alu_result = (ALU_in2 == 0) ? ALU_in1 : unsigned_rem_result; - default: out_alu_result = 32'h0; - endcase // in_alu_op + `MUL: alu_result_o = mul_result[31:0]; + `MULH: alu_result_o = mul_result[63:32]; + `MULHSU: alu_result_o = mul_result[63:32]; + `MULHU: alu_result_o = mul_result[63:32]; + `DIV: alu_result_o = (ALU_in2 == 0) ? 32'hffffffff : signed_div_result; + `DIVU: alu_result_o = (ALU_in2 == 0) ? 32'hffffffff : unsigned_div_result; + `REM: alu_result_o = (ALU_in2 == 0) ? ALU_in1 : signed_rem_result; + `REMU: alu_result_o = (ALU_in2 == 0) ? ALU_in1 : unsigned_rem_result; + default: alu_result_o = 32'h0; + endcase // alu_op_i end `else @@ -168,42 +167,40 @@ module VX_alu( wire which_in2; wire[31:0] upper_immed; + assign which_in2 = rs2_src_i == `RS2_IMMED; - assign which_in2 = in_rs2_src == `RS2_IMMED; + assign ALU_in1 = a_i; - assign ALU_in1 = in_1; + assign ALU_in2 = which_in2 ? itype_immed_i : b_i; - assign ALU_in2 = which_in2 ? in_itype_immed : in_2; - - - assign upper_immed = {in_upper_immed, {12{1'b0}}}; + assign upper_immed = {upper_immed_i, {12{1'b0}}}; always @(*) begin - case(in_alu_op) - `ADD: out_alu_result = $signed(ALU_in1) + $signed(ALU_in2); - `SUB: out_alu_result = $signed(ALU_in1) - $signed(ALU_in2); - `SLLA: out_alu_result = ALU_in1 << ALU_in2[4:0]; - `SLT: out_alu_result = ($signed(ALU_in1) < $signed(ALU_in2)) ? 32'h1 : 32'h0; - `SLTU: out_alu_result = ALU_in1 < ALU_in2 ? 32'h1 : 32'h0; - `XOR: out_alu_result = ALU_in1 ^ ALU_in2; - `SRL: out_alu_result = ALU_in1 >> ALU_in2[4:0]; - `SRA: out_alu_result = $signed(ALU_in1) >>> ALU_in2[4:0]; - `OR: out_alu_result = ALU_in1 | ALU_in2; - `AND: out_alu_result = ALU_in2 & ALU_in1; - `SUBU: out_alu_result = (ALU_in1 >= ALU_in2) ? 32'h0 : 32'hffffffff; - `LUI_ALU: out_alu_result = upper_immed; - `AUIPC_ALU: out_alu_result = $signed(in_curr_PC) + $signed(upper_immed); + case(alu_op_i) + `ADD: alu_result_o = $signed(ALU_in1) + $signed(ALU_in2); + `SUB: alu_result_o = $signed(ALU_in1) - $signed(ALU_in2); + `SLLA: alu_result_o = ALU_in1 << ALU_in2[4:0]; + `SLT: alu_result_o = ($signed(ALU_in1) < $signed(ALU_in2)) ? 32'h1 : 32'h0; + `SLTU: alu_result_o = ALU_in1 < ALU_in2 ? 32'h1 : 32'h0; + `XOR: alu_result_o = ALU_in1 ^ ALU_in2; + `SRL: alu_result_o = ALU_in1 >> ALU_in2[4:0]; + `SRA: alu_result_o = $signed(ALU_in1) >>> ALU_in2[4:0]; + `OR: alu_result_o = ALU_in1 | ALU_in2; + `AND: alu_result_o = ALU_in2 & ALU_in1; + `SUBU: alu_result_o = (ALU_in1 >= ALU_in2) ? 32'h0 : 32'hffffffff; + `LUI_ALU: alu_result_o = upper_immed; + `AUIPC_ALU: alu_result_o = $signed(curr_PC_i) + $signed(upper_immed); // TODO profitable to roll these exceptional cases into inst_delay to avoid pipeline when possible? - `MUL: out_alu_result = mul_result[31:0]; - `MULH: out_alu_result = mul_result[63:32]; - `MULHSU: out_alu_result = mul_result[63:32]; - `MULHU: out_alu_result = mul_result[63:32]; - `DIV: out_alu_result = (ALU_in2 == 0) ? 32'hffffffff : signed_div_result; - `DIVU: out_alu_result = (ALU_in2 == 0) ? 32'hffffffff : unsigned_div_result; - `REM: out_alu_result = (ALU_in2 == 0) ? ALU_in1 : signed_rem_result; - `REMU: out_alu_result = (ALU_in2 == 0) ? ALU_in1 : unsigned_rem_result; - default: out_alu_result = 32'h0; - endcase // in_alu_op + `MUL: alu_result_o = mul_result[31:0]; + `MULH: alu_result_o = mul_result[63:32]; + `MULHSU: alu_result_o = mul_result[63:32]; + `MULHU: alu_result_o = mul_result[63:32]; + `DIV: alu_result_o = (ALU_in2 == 0) ? 32'hffffffff : signed_div_result; + `DIVU: alu_result_o = (ALU_in2 == 0) ? 32'hffffffff : unsigned_div_result; + `REM: alu_result_o = (ALU_in2 == 0) ? ALU_in1 : signed_rem_result; + `REMU: alu_result_o = (ALU_in2 == 0) ? ALU_in1 : unsigned_rem_result; + default: alu_result_o = 32'h0; + endcase // alu_op_i end `endif diff --git a/hw/rtl/VX_back_end.v b/hw/rtl/VX_back_end.v index 76736ea6..af0be2fc 100644 --- a/hw/rtl/VX_back_end.v +++ b/hw/rtl/VX_back_end.v @@ -10,8 +10,8 @@ module VX_back_end #( VX_gpu_dcache_rsp_if dcache_rsp_if, VX_gpu_dcache_req_if dcache_req_if, - output wire out_mem_delay, - output wire out_exec_delay, + output wire mem_delay_o, + output wire exec_delay_o, output wire gpr_stage_delay, VX_jal_response_if jal_rsp_if, VX_branch_response_if branch_rsp_if, @@ -65,8 +65,8 @@ VX_gpr_stage gpr_stage ( .csr_req_if (csr_req_if), .stall_gpr_csr (stall_gpr_csr), // End new - .memory_delay (out_mem_delay), - .exec_delay (out_exec_delay), + .memory_delay (mem_delay_o), + .exec_delay (exec_delay_o), .gpr_stage_delay (gpr_stage_delay) ); @@ -77,8 +77,8 @@ VX_lsu load_store_unit ( .mem_wb_if (mem_wb_if), .dcache_rsp_if (dcache_rsp_if), .dcache_req_if (dcache_req_if), - .out_delay (out_mem_delay), - .no_slot_mem (no_slot_mem) + .delay_o (mem_delay_o), + .no_slot_mem_i (no_slot_mem) ); VX_execute_unit execUnit ( @@ -88,8 +88,8 @@ VX_execute_unit execUnit ( .inst_exec_wb_if (inst_exec_wb_if), .jal_rsp_if (jal_rsp_if), .branch_rsp_if (branch_rsp_if), - .out_delay (out_exec_delay), - .no_slot_exec (no_slot_exec) + .delay_o (exec_delay_o), + .no_slot_exec_i (no_slot_exec) ); VX_gpgpu_inst gpgpu_inst ( @@ -117,9 +117,9 @@ VX_writeback wb ( .csr_wb_if (csr_wb_if), .writeback_if (writeback_temp_if), - .no_slot_mem (no_slot_mem), - .no_slot_exec (no_slot_exec), - .no_slot_csr (no_slot_csr) + .no_slot_mem_o (no_slot_mem), + .no_slot_exec_o (no_slot_exec), + .no_slot_csr_o (no_slot_csr) ); endmodule \ No newline at end of file diff --git a/hw/rtl/VX_csr_data.v b/hw/rtl/VX_csr_data.v index ced6dae4..0cd29da0 100644 --- a/hw/rtl/VX_csr_data.v +++ b/hw/rtl/VX_csr_data.v @@ -4,19 +4,19 @@ module VX_csr_data ( input wire clk, // Clock input wire reset, - input wire[`CSR_ADDR_SIZE-1:0] in_read_csr_address, - input wire in_write_valid, - input wire[`CSR_WIDTH-1:0] in_write_csr_data, + input wire[`CSR_ADDR_SIZE-1:0] read_csr_address_i, + input wire write_valid_i, + input wire[`CSR_WIDTH-1:0] write_csr_data_i, `IGNORE_WARNINGS_BEGIN // We use a smaller storage for CSRs than the standard 4KB in RISC-V - input wire[`CSR_ADDR_SIZE-1:0] in_write_csr_address, + input wire[`CSR_ADDR_SIZE-1:0] write_csr_address_i, `IGNORE_WARNINGS_END - output wire[31:0] out_read_csr_data, + output wire[31:0] read_csr_data_o, // For instruction retire counting - input wire in_writeback_valid + input wire writeback_valid_i ); // wire[`NUM_THREADS-1:0][31:0] thread_ids; // wire[`NUM_THREADS-1:0][31:0] warp_ids; @@ -41,21 +41,21 @@ module VX_csr_data ( wire read_instret; wire read_instreth; - assign read_cycle = in_read_csr_address == `CSR_CYCL_L; - assign read_cycleh = in_read_csr_address == `CSR_CYCL_H; - assign read_instret = in_read_csr_address == `CSR_INST_L; - assign read_instreth = in_read_csr_address == `CSR_INST_H; + assign read_cycle = read_csr_address_i == `CSR_CYCL_L; + assign read_cycleh = read_csr_address_i == `CSR_CYCL_H; + assign read_instret = read_csr_address_i == `CSR_INST_L; + assign read_instreth = read_csr_address_i == `CSR_INST_H; wire [$clog2(`NUM_CSRS)-1:0] read_addr, write_addr; // cast address to physical CSR range - assign read_addr = $size(read_addr)'(in_read_csr_address); - assign write_addr = $size(write_addr)'(in_write_csr_address); + assign read_addr = $size(read_addr)'(read_csr_address_i); + assign write_addr = $size(write_addr)'(write_csr_address_i); - // wire thread_select = in_read_csr_address == 12'h20; - // wire warp_select = in_read_csr_address == 12'h21; + // wire thread_select = read_csr_address_i == 12'h20; + // wire warp_select = read_csr_address_i == 12'h21; - // assign out_read_csr_data = thread_select ? thread_ids : + // assign read_csr_data_o = thread_select ? thread_ids : // warp_select ? warp_ids : // 0; @@ -67,16 +67,16 @@ module VX_csr_data ( instret <= 0; end else begin cycle <= cycle + 1; - if (in_write_valid) begin - csr[write_addr] <= in_write_csr_data; + if (write_valid_i) begin + csr[write_addr] <= write_csr_data_i; end - if (in_writeback_valid) begin + if (writeback_valid_i) begin instret <= instret + 1; end end end - assign out_read_csr_data = read_cycle ? cycle[31:0] : + assign read_csr_data_o = read_cycle ? cycle[31:0] : read_cycleh ? cycle[63:32] : read_instret ? instret[31:0] : read_instreth ? instret[63:32] : diff --git a/hw/rtl/VX_csr_pipe.v b/hw/rtl/VX_csr_pipe.v index 6da9a23c..ae711d34 100644 --- a/hw/rtl/VX_csr_pipe.v +++ b/hw/rtl/VX_csr_pipe.v @@ -31,14 +31,14 @@ module VX_csr_pipe #( wire writeback = |writeback_if.wb_valid; VX_csr_data csr_data( - .clk (clk), - .reset (reset), - .in_read_csr_address (csr_req_if.csr_address), - .in_write_valid (is_csr_s2), - .in_write_csr_data (csr_updated_data_s2[`CSR_WIDTH-1:0]), - .in_write_csr_address(csr_address_s2), - .out_read_csr_data (csr_read_data_unqual), - .in_writeback_valid (writeback) + .clk (clk), + .reset (reset), + .read_csr_address_i (csr_req_if.csr_address), + .write_valid_i (is_csr_s2), + .write_csr_data_i (csr_updated_data_s2[`CSR_WIDTH-1:0]), + .write_csr_address_i(csr_address_s2), + .read_csr_data_o (csr_read_data_unqual), + .writeback_valid_i (writeback) ); reg [31:0] csr_updated_data; diff --git a/hw/rtl/VX_execute_unit.v b/hw/rtl/VX_execute_unit.v index 6126e58b..762a3b6d 100644 --- a/hw/rtl/VX_execute_unit.v +++ b/hw/rtl/VX_execute_unit.v @@ -14,8 +14,8 @@ module VX_execute_unit ( // Branch Response VX_branch_response_if branch_rsp_if, - input wire no_slot_exec, - output wire out_delay + input wire no_slot_exec_i, + output wire delay_o ); wire[`NUM_THREADS-1:0][31:0] in_a_reg_data; @@ -48,18 +48,17 @@ module VX_execute_unit ( generate for (index_out_reg = 0; index_out_reg < `NUM_THREADS; index_out_reg = index_out_reg + 1) begin : alu_defs VX_alu alu( - .clk(clk), - .reset(reset), - // .in_reg_data (in_reg_data[1:0]), - .in_1 (in_a_reg_data[index_out_reg]), - .in_2 (in_b_reg_data[index_out_reg]), - .in_rs2_src (in_rs2_src), - .in_itype_immed(in_itype_immed), - .in_upper_immed(in_upper_immed), - .in_alu_op (in_alu_op), - .in_curr_PC (in_curr_PC), - .out_alu_result(alu_result[index_out_reg]), - .out_alu_stall(alu_stall[index_out_reg]) + .clk (clk), + .reset (reset), + .a_i (in_a_reg_data[index_out_reg]), + .b_i (in_b_reg_data[index_out_reg]), + .rs2_src_i (in_rs2_src), + .itype_immed_i (in_itype_immed), + .upper_immed_i (in_upper_immed), + .alu_op_i (in_alu_op), + .curr_PC_i (in_curr_PC), + .alu_result_o (alu_result[index_out_reg]), + .alu_stall_o (alu_stall[index_out_reg]) ); end endgenerate @@ -67,7 +66,7 @@ module VX_execute_unit ( wire internal_stall; assign internal_stall = |alu_stall; - assign out_delay = no_slot_exec || internal_stall; + assign delay_o = no_slot_exec_i || internal_stall; `DEBUG_BEGIN wire [$clog2(`NUM_THREADS)-1:0] jal_branch_use_index; diff --git a/hw/rtl/VX_fetch.v b/hw/rtl/VX_fetch.v index e7027844..db149337 100644 --- a/hw/rtl/VX_fetch.v +++ b/hw/rtl/VX_fetch.v @@ -10,7 +10,7 @@ module VX_fetch ( input wire[`NW_BITS-1:0] icache_stage_wid, input wire[`NUM_THREADS-1:0] icache_stage_valids, - output wire out_ebreak, + output wire ebreak_o, VX_jal_response_if jal_rsp_if, VX_branch_response_if branch_rsp_if, VX_inst_meta_if fe_inst_meta_fi, @@ -86,9 +86,9 @@ module VX_fetch ( .thread_mask (thread_mask), .warp_num (warp_num), .warp_pc (warp_pc), - .out_ebreak (out_ebreak), + .ebreak_o (ebreak_o), .scheduled_warp (scheduled_warp) - ); + ); assign fe_inst_meta_fi.warp_num = warp_num; assign fe_inst_meta_fi.valid = thread_mask; diff --git a/hw/rtl/VX_front_end.v b/hw/rtl/VX_front_end.v index 6ac70286..d5fe06e1 100644 --- a/hw/rtl/VX_front_end.v +++ b/hw/rtl/VX_front_end.v @@ -52,7 +52,7 @@ module VX_front_end ( .warp_ctl_if (warp_ctl_if), .icache_stage_delay (icache_stage_delay), .branch_rsp_if (branch_rsp_if), - .out_ebreak (vortex_ebreak), // fetch_ebreak + .ebreak_o (vortex_ebreak), // fetch_ebreak .fe_inst_meta_fi (fe_inst_meta_fi) ); @@ -61,7 +61,7 @@ module VX_front_end ( VX_f_d_reg f_i_reg( .clk (clk), .reset (reset), - .in_freeze (freeze_fi_reg), + .freeze_i (freeze_fi_reg), .fe_inst_meta_fd(fe_inst_meta_fi), .fd_inst_meta_de(fe_inst_meta_fi2) ); @@ -79,16 +79,14 @@ module VX_front_end ( .icache_req_if (icache_req_if) ); - VX_i_d_reg i_d_reg( .clk (clk), .reset (reset), - .in_freeze (total_freeze), + .freeze_i (total_freeze), .fe_inst_meta_fd (fe_inst_meta_id), .fd_inst_meta_de (fd_inst_meta_de) ); - VX_decode decode( .fd_inst_meta_de (fd_inst_meta_de), .frE_to_bckE_req_if (frE_to_bckE_req_if), @@ -102,8 +100,8 @@ module VX_front_end ( VX_d_e_reg d_e_reg( .clk (clk), .reset (reset), - .in_branch_stall (no_br_stall), - .in_freeze (total_freeze), + .branch_stall_i (no_br_stall), + .freeze_i (total_freeze), .frE_to_bckE_req_if (frE_to_bckE_req_if), .bckE_req_if (bckE_req_if) ); diff --git a/hw/rtl/VX_gpr.v b/hw/rtl/VX_gpr.v index 523f1dda..c8921fcc 100644 --- a/hw/rtl/VX_gpr.v +++ b/hw/rtl/VX_gpr.v @@ -1,19 +1,19 @@ `include "VX_define.vh" module VX_gpr ( - input wire clk, - input wire reset, - input wire valid_write_request, + input wire clk, + input wire reset, + input wire valid_write_request_i, VX_gpr_read_if gpr_read_if, - VX_wb_if writeback_if, + VX_wb_if writeback_if, - output reg[`NUM_THREADS-1:0][`NUM_GPRS-1:0] out_a_reg_data, - output reg[`NUM_THREADS-1:0][`NUM_GPRS-1:0] out_b_reg_data + output reg[`NUM_THREADS-1:0][`NUM_GPRS-1:0] a_reg_data_o, + output reg[`NUM_THREADS-1:0][`NUM_GPRS-1:0] b_reg_data_o ); wire write_enable; `ifndef ASIC - assign write_enable = valid_write_request && ((writeback_if.wb != 0)) && (writeback_if.rd != 0); + assign write_enable = valid_write_request_i && ((writeback_if.wb != 0)) && (writeback_if.rd != 0); byte_enabled_simple_dual_port_ram first_ram( .we (write_enable), @@ -24,11 +24,11 @@ module VX_gpr ( .raddr2(gpr_read_if.rs2), .be (writeback_if.wb_valid), .wdata (writeback_if.write_data), - .q1 (out_a_reg_data), - .q2 (out_b_reg_data) + .q1 (a_reg_data_o), + .q2 (b_reg_data_o) ); `else - assign write_enable = valid_write_request && ((writeback_if.wb != 0)); + assign write_enable = valid_write_request_i && ((writeback_if.wb != 0)); wire going_to_write = write_enable & (|writeback_if.wb_valid); wire[`NUM_THREADS-1:0][`NUM_GPRS-1:0] write_bit_mask; @@ -56,13 +56,13 @@ module VX_gpr ( begin for (curr_bit = 0; curr_bit < `NUM_GPRS; curr_bit=curr_bit+1) begin - assign out_a_reg_data[thread][curr_bit] = ((temp_a[thread][curr_bit] === 1'dx) || cena_1 )? 1'b0 : temp_a[thread][curr_bit]; - assign out_b_reg_data[thread][curr_bit] = ((temp_b[thread][curr_bit] === 1'dx) || cena_2) ? 1'b0 : temp_b[thread][curr_bit]; + assign a_reg_data_o[thread][curr_bit] = ((temp_a[thread][curr_bit] === 1'dx) || cena_1 )? 1'b0 : temp_a[thread][curr_bit]; + assign b_reg_data_o[thread][curr_bit] = ((temp_b[thread][curr_bit] === 1'dx) || cena_2) ? 1'b0 : temp_b[thread][curr_bit]; end end `else - assign out_a_reg_data = temp_a; - assign out_b_reg_data = temp_b; + assign a_reg_data_o = temp_a; + assign b_reg_data_o = temp_b; `endif wire[`NUM_THREADS-1:0][`NUM_GPRS-1:0] to_write = (writeback_if.rd != 0) ? writeback_if.write_data : 0; diff --git a/hw/rtl/VX_gpr_stage.v b/hw/rtl/VX_gpr_stage.v index 8eda34d9..33fea7fc 100644 --- a/hw/rtl/VX_gpr_stage.v +++ b/hw/rtl/VX_gpr_stage.v @@ -55,8 +55,8 @@ module VX_gpr_stage ( .gpr_read_if (gpr_read_if), .gpr_jal_if (gpr_jal_if), - .out_a_reg_data (gpr_datf_if.a_reg_data), - .out_b_reg_data (gpr_datf_if.b_reg_data) + .a_reg_data_o (gpr_datf_if.a_reg_data), + .b_reg_data_o (gpr_datf_if.b_reg_data) ); // assign bckE_req_if.is_csr = is_csr; diff --git a/hw/rtl/VX_gpr_wrapper.v b/hw/rtl/VX_gpr_wrapper.v index f728bf3f..e5ceea56 100644 --- a/hw/rtl/VX_gpr_wrapper.v +++ b/hw/rtl/VX_gpr_wrapper.v @@ -3,13 +3,12 @@ module VX_gpr_wrapper ( input wire clk, input wire reset, - VX_gpr_read_if gpr_read_if, - VX_wb_if writeback_if, - VX_gpr_jal_if gpr_jal_if, + VX_gpr_read_if gpr_read_if, + VX_wb_if writeback_if, + VX_gpr_jal_if gpr_jal_if, - output wire[`NUM_THREADS-1:0][31:0] out_a_reg_data, - output wire[`NUM_THREADS-1:0][31:0] out_b_reg_data - + output wire[`NUM_THREADS-1:0][31:0] a_reg_data_o, + output wire[`NUM_THREADS-1:0][31:0] b_reg_data_o ); wire[`NUM_WARPS-1:0][`NUM_THREADS-1:0][31:0] temp_a_reg_data; @@ -24,8 +23,8 @@ module VX_gpr_wrapper ( endgenerate `ifndef ASIC - assign out_a_reg_data = (gpr_jal_if.is_jal ? jal_data : (temp_a_reg_data[gpr_read_if.warp_num])); - assign out_b_reg_data = (temp_b_reg_data[gpr_read_if.warp_num]); + assign a_reg_data_o = (gpr_jal_if.is_jal ? jal_data : (temp_a_reg_data[gpr_read_if.warp_num])); + assign b_reg_data_o = (temp_b_reg_data[gpr_read_if.warp_num]); `else wire zer = 0; @@ -42,8 +41,8 @@ module VX_gpr_wrapper ( .out (old_warp_num) ); - assign out_a_reg_data = (gpr_jal_if.is_jal ? jal_data : (temp_a_reg_data[old_warp_num])); - assign out_b_reg_data = (temp_b_reg_data[old_warp_num]); + assign a_reg_data_o = (gpr_jal_if.is_jal ? jal_data : (temp_a_reg_data[old_warp_num])); + assign b_reg_data_o = (temp_b_reg_data[old_warp_num]); `endif @@ -53,13 +52,13 @@ module VX_gpr_wrapper ( for (warp_index = 0; warp_index < `NUM_WARPS; warp_index = warp_index + 1) begin : warp_gprs wire valid_write_request = warp_index == writeback_if.wb_warp_num; VX_gpr gpr( - .clk (clk), - .reset (reset), - .valid_write_request(valid_write_request), - .gpr_read_if (gpr_read_if), - .writeback_if (writeback_if), - .out_a_reg_data (temp_a_reg_data[warp_index]), - .out_b_reg_data (temp_b_reg_data[warp_index]) + .clk (clk), + .reset (reset), + .valid_write_request_i (valid_write_request), + .gpr_read_if (gpr_read_if), + .writeback_if (writeback_if), + .a_reg_data_o (temp_a_reg_data[warp_index]), + .b_reg_data_o (temp_b_reg_data[warp_index]) ); end diff --git a/hw/rtl/VX_lsu.v b/hw/rtl/VX_lsu.v index 560a7225..0425b700 100644 --- a/hw/rtl/VX_lsu.v +++ b/hw/rtl/VX_lsu.v @@ -3,7 +3,7 @@ module VX_lsu ( input wire clk, input wire reset, - input wire no_slot_mem, + input wire no_slot_mem_i, VX_lsu_req_if lsu_req_if, // Write back to GPR @@ -11,7 +11,7 @@ module VX_lsu ( VX_gpu_dcache_rsp_if dcache_rsp_if, VX_gpu_dcache_req_if dcache_req_if, - output wire out_delay + output wire delay_o ); // Generate Addresses wire[`NUM_THREADS-1:0][31:0] address; @@ -38,7 +38,7 @@ module VX_lsu ( ) lsu_buffer( .clk (clk), .reset(reset), - .stall(out_delay), + .stall(delay_o), .flush(zero), .in ({address , lsu_req_if.store_data, lsu_req_if.valid, lsu_req_if.mem_read, lsu_req_if.mem_write, lsu_req_if.rd, lsu_req_if.warp_num, lsu_req_if.wb, lsu_req_if.lsu_pc}), .out ({use_address, use_store_data , use_valid , use_mem_read , use_mem_write , use_rd , use_warp_num , use_wb , use_pc }) @@ -56,10 +56,10 @@ module VX_lsu ( assign dcache_req_if.core_req_pc = use_pc; // Core can't accept response - assign dcache_rsp_if.core_rsp_ready = ~no_slot_mem; + assign dcache_rsp_if.core_rsp_ready = ~no_slot_mem_i; // Cache can't accept request - assign out_delay = ~dcache_req_if.core_req_ready; + assign delay_o = ~dcache_req_if.core_req_ready; // Core Response assign mem_wb_if.rd = dcache_rsp_if.core_rsp_read; diff --git a/hw/rtl/VX_warp_scheduler.v b/hw/rtl/VX_warp_scheduler.v index f9202eb8..50aabf86 100644 --- a/hw/rtl/VX_warp_scheduler.v +++ b/hw/rtl/VX_warp_scheduler.v @@ -55,7 +55,7 @@ module VX_warp_scheduler ( output wire[`NUM_THREADS-1:0] thread_mask, output wire[`NW_BITS-1:0] warp_num, output wire[31:0] warp_pc, - output wire out_ebreak, + output wire ebreak_o, output wire scheduled_warp, input wire[`NW_BITS-1:0] icache_stage_wid, @@ -333,7 +333,7 @@ module VX_warp_scheduler ( wire ebreak = (warp_active == 0); - assign out_ebreak = ebreak; + assign ebreak_o = ebreak; /* verilator lint_on WIDTH */ diff --git a/hw/rtl/VX_writeback.v b/hw/rtl/VX_writeback.v index dc9971cc..f678d39b 100644 --- a/hw/rtl/VX_writeback.v +++ b/hw/rtl/VX_writeback.v @@ -12,9 +12,9 @@ module VX_writeback ( // Actual WB to GPR VX_wb_if writeback_if, - output wire no_slot_mem, - output wire no_slot_exec, - output wire no_slot_csr + output wire no_slot_mem_o, + output wire no_slot_exec_o, + output wire no_slot_csr_o ); VX_wb_if writeback_tempp_if(); @@ -24,9 +24,9 @@ module VX_writeback ( wire csr_wb = (csr_wb_if.wb != 0) && (|csr_wb_if.valid); - assign no_slot_mem = mem_wb && (exec_wb || csr_wb); - assign no_slot_csr = csr_wb && (exec_wb); - assign no_slot_exec = 0; + assign no_slot_mem_o = mem_wb && (exec_wb || csr_wb); + assign no_slot_csr_o = csr_wb && (exec_wb); + assign no_slot_exec_o = 0; assign writeback_tempp_if.write_data = exec_wb ? inst_exec_wb_if.alu_result : csr_wb ? csr_wb_if.csr_result : diff --git a/hw/rtl/Vortex.v b/hw/rtl/Vortex.v index f891a287..9d3f6a7a 100644 --- a/hw/rtl/Vortex.v +++ b/hw/rtl/Vortex.v @@ -43,7 +43,7 @@ module Vortex #( input wire [31:0] llc_snp_req_addr, output wire llc_snp_req_ready, - output wire out_ebreak + output wire ebreak ); `DEBUG_BEGIN wire scheduler_empty; @@ -156,7 +156,7 @@ VX_front_end front_end ( .icache_req_if (icache_req_if), .jal_rsp_if (jal_rsp_if), .branch_rsp_if (branch_rsp_if), - .fetch_ebreak (out_ebreak) + .fetch_ebreak (ebreak) ); VX_scheduler schedule ( @@ -184,8 +184,8 @@ VX_back_end #( .dcache_rsp_if (dcache_rsp_if), .dcache_req_if (dcache_req_if), .writeback_if (writeback_if), - .out_mem_delay (memory_delay), - .out_exec_delay (exec_delay), + .mem_delay_o (memory_delay), + .exec_delay_o (exec_delay), .gpr_stage_delay (gpr_stage_delay) ); diff --git a/hw/rtl/Vortex_Cluster.v b/hw/rtl/Vortex_Cluster.v index ac2c9ddd..d5c38cdd 100644 --- a/hw/rtl/Vortex_Cluster.v +++ b/hw/rtl/Vortex_Cluster.v @@ -30,7 +30,7 @@ module Vortex_Cluster #( input wire[31:0] llc_snp_req_addr, output wire llc_snp_req_ready, - output wire out_ebreak + output wire ebreak ); // DRAM Dcache Req wire[`NUM_CORES-1:0] per_core_dram_req_read; @@ -57,7 +57,7 @@ module Vortex_Cluster #( wire[`NUM_CORES-1:0] per_core_I_dram_rsp_ready; // Out ebreak - wire[`NUM_CORES-1:0] per_core_out_ebreak; + wire[`NUM_CORES-1:0] per_core_ebreak; wire[`NUM_CORES-1:0] per_core_io_valid; wire[`NUM_CORES-1:0][31:0] per_core_io_data; @@ -68,7 +68,7 @@ module Vortex_Cluster #( wire[31:0] snp_fwd_addr; wire[`NUM_CORES-1:0] snp_fwd_ready; - assign out_ebreak = (&per_core_out_ebreak); + assign ebreak = (&per_core_ebreak); genvar curr_core; generate @@ -109,7 +109,7 @@ module Vortex_Cluster #( .llc_snp_req_valid (snp_fwd_valid), .llc_snp_req_addr (snp_fwd_addr), .llc_snp_req_ready (snp_fwd_ready [curr_core]), - .out_ebreak (per_core_out_ebreak [curr_core]) + .ebreak (per_core_ebreak [curr_core]) ); assign per_core_dram_req_data [curr_core] = curr_core_dram_req_data; diff --git a/hw/rtl/Vortex_Socket.v b/hw/rtl/Vortex_Socket.v index dd972743..1b1bf902 100644 --- a/hw/rtl/Vortex_Socket.v +++ b/hw/rtl/Vortex_Socket.v @@ -28,7 +28,7 @@ module Vortex_Socket ( input wire[31:0] llc_snp_req_addr, output wire llc_snp_req_ready, - output wire out_ebreak + output wire ebreak ); if (`NUM_CLUSTERS == 1) begin @@ -63,7 +63,7 @@ module Vortex_Socket ( .llc_snp_req_addr (llc_snp_req_addr), .llc_snp_req_ready (llc_snp_req_ready), - .out_ebreak (out_ebreak) + .ebreak (ebreak) ); end else begin @@ -72,9 +72,9 @@ module Vortex_Socket ( wire[31:0] snp_fwd_addr; wire[`NUM_CLUSTERS-1:0] snp_fwd_ready; - wire[`NUM_CLUSTERS-1:0] per_cluster_out_ebreak; + wire[`NUM_CLUSTERS-1:0] per_cluster_ebreak; - assign out_ebreak = (&per_cluster_out_ebreak); + assign ebreak = (&per_cluster_ebreak); // // DRAM Dcache Req wire[`NUM_CLUSTERS-1:0] per_cluster_dram_req_valid; @@ -133,9 +133,9 @@ module Vortex_Socket ( .llc_snp_req_valid (snp_fwd_valid), .llc_snp_req_addr (snp_fwd_addr), - .llc_snp_req_ready (snp_fwd_ready[curr_cluster]), + .llc_snp_req_ready (snp_fwd_ready [curr_cluster]), - .out_ebreak (per_cluster_out_ebreak [curr_cluster]) + .ebreak (per_cluster_ebreak [curr_cluster]) ); end diff --git a/hw/rtl/cache/VX_bank.v b/hw/rtl/cache/VX_bank.v index c93a0b2d..32513d94 100644 --- a/hw/rtl/cache/VX_bank.v +++ b/hw/rtl/cache/VX_bank.v @@ -125,9 +125,9 @@ module VX_bank #( .clk (clk), .reset (reset), .push (snp_req_valid), - .in_data (snp_req_addr), + .data_i (snp_req_addr), .pop (snrq_pop), - .out_data(snrq_addr_st0), + .data_o (snrq_addr_st0), .empty (snrq_empty), .full (snp_req_full) ); @@ -147,9 +147,9 @@ module VX_bank #( .clk (clk), .reset (reset), .push (dram_fill_rsp_valid), - .in_data ({dram_fill_rsp_addr, dram_fill_rsp_data}), + .data_i ({dram_fill_rsp_addr, dram_fill_rsp_data}), .pop (dfpq_pop), - .out_data({dfpq_addr_st0, dfpq_filldata_st0}), + .data_o({dfpq_addr_st0, dfpq_filldata_st0}), .empty (dfpq_empty), .full (dfpq_full) ); @@ -538,10 +538,10 @@ module VX_bank #( .reset (reset), .push (cwbq_push), - .in_data ({cwbq_tid, cwbq_rd, cwbq_wb, cwbq_warp_num, cwbq_data, cwbq_pc, addr_st2}), + .data_i ({cwbq_tid, cwbq_rd, cwbq_wb, cwbq_warp_num, cwbq_data, cwbq_pc, addr_st2}), .pop (core_rsp_pop), - .out_data({core_rsp_tid, core_rsp_rd, core_rsp_wb, core_rsp_warp_num, core_rsp_data, core_rsp_pc, core_rsp_addr}), + .data_o({core_rsp_tid, core_rsp_rd, core_rsp_wb, core_rsp_warp_num, core_rsp_data, core_rsp_pc, core_rsp_addr}), .empty (cwbq_empty), .full (cwbq_full) ); @@ -606,10 +606,10 @@ module VX_bank #( .reset (reset), .push (dwbq_push), - .in_data ({dwbq_req_addr, dwbq_req_data}), + .data_i ({dwbq_req_addr, dwbq_req_data}), .pop (dram_wb_req_pop), - .out_data({dram_wb_req_addr, dram_wb_req_data}), + .data_o({dram_wb_req_addr, dram_wb_req_data}), .empty (dwbq_empty), .full (dwbq_full) ); @@ -627,9 +627,9 @@ module VX_bank #( .clk (clk), .reset (reset), .push (snp_fwd_push), - .in_data ({addr_st2}), + .data_i ({addr_st2}), .pop (snp_fwd_pop), - .out_data({snp_fwd_addr}), + .data_o({snp_fwd_addr}), .empty (ffsq_empty), .full (ffsq_full) ); diff --git a/hw/rtl/cache/VX_cache_dfq_queue.v b/hw/rtl/cache/VX_cache_dfq_queue.v index 83024873..767ab570 100644 --- a/hw/rtl/cache/VX_cache_dfq_queue.v +++ b/hw/rtl/cache/VX_cache_dfq_queue.v @@ -79,9 +79,9 @@ module VX_cache_dfq_queue #( .clk (clk), .reset (reset), .push (push_qual), - .in_data ({per_bank_dram_fill_req_valid, per_bank_dram_fill_req_addr}), + .data_i ({per_bank_dram_fill_req_valid, per_bank_dram_fill_req_addr}), .pop (pop_qual), - .out_data({out_per_bank_dram_fill_req, out_per_bank_dram_fill_req_addr}), + .data_o({out_per_bank_dram_fill_req, out_per_bank_dram_fill_req_addr}), .empty (o_empty), .full (dfqq_full) ); diff --git a/hw/rtl/cache/VX_cache_req_queue.v b/hw/rtl/cache/VX_cache_req_queue.v index 78f5a310..7aa90497 100644 --- a/hw/rtl/cache/VX_cache_req_queue.v +++ b/hw/rtl/cache/VX_cache_req_queue.v @@ -122,9 +122,9 @@ module VX_cache_req_queue #( .clk (clk), .reset (reset), .push (push_qual), - .in_data ({bank_valids , bank_addr , bank_writedata , bank_rd , bank_wb , bank_warp_num , bank_mem_read , bank_mem_write , bank_pc}), + .data_i ({bank_valids , bank_addr , bank_writedata , bank_rd , bank_wb , bank_warp_num , bank_mem_read , bank_mem_write , bank_pc}), .pop (pop_qual), - .out_data ({out_per_valids, out_per_addr, out_per_writedata, out_per_rd, out_per_wb, out_per_warp_num, out_per_mem_read, out_per_mem_write, out_per_pc}), + .data_o ({out_per_valids, out_per_addr, out_per_writedata, out_per_rd, out_per_wb, out_per_warp_num, out_per_mem_read, out_per_mem_write, out_per_pc}), .empty (o_empty), .full (reqq_full) ); diff --git a/hw/rtl/cache/VX_prefetcher.v b/hw/rtl/cache/VX_prefetcher.v index 50792dbc..9e599eae 100644 --- a/hw/rtl/cache/VX_prefetcher.v +++ b/hw/rtl/cache/VX_prefetcher.v @@ -40,10 +40,10 @@ module VX_prefetcher #( .reset (reset), .push (dram_req && !current_full && !pref_pop), - .in_data (dram_req_addr & `BASE_ADDR_MASK), + .data_i (dram_req_addr & `BASE_ADDR_MASK), .pop (update_use), - .out_data(current_addr), + .data_o(current_addr), .empty (current_empty), .full (current_full) diff --git a/hw/rtl/libs/VX_generic_queue.v b/hw/rtl/libs/VX_generic_queue.v index 36801156..02f44ff4 100644 --- a/hw/rtl/libs/VX_generic_queue.v +++ b/hw/rtl/libs/VX_generic_queue.v @@ -10,13 +10,13 @@ module VX_generic_queue #( output wire empty, output wire full, `IGNORE_WARNINGS_END - input wire [DATAW-1:0] in_data, - output wire [DATAW-1:0] out_data + input wire [DATAW-1:0] data_i, + output wire [DATAW-1:0] data_o ); if (SIZE == 0) begin assign empty = 1; - assign out_data = in_data; + assign data_o = data_i; assign full = 0; end else begin // (SIZE > 0) @@ -49,12 +49,12 @@ module VX_generic_queue #( end if (writing) begin - head_r <= in_data; + head_r <= data_i; end end end - assign out_data = head_r; + assign data_o = head_r; assign empty = (size_r == 0); assign full = (size_r != 0) && !pop; @@ -99,7 +99,7 @@ module VX_generic_queue #( always @(posedge clk) begin if (writing) begin - data[wr_ctr_r] <= in_data; + data[wr_ctr_r] <= data_i; end end @@ -121,12 +121,12 @@ module VX_generic_queue #( end bypass_r <= writing && (empty_r || (1 == size_r) && reading); - curr_r <= in_data; + curr_r <= data_i; head_r <= data[reading ? rd_next_ptr_r : rd_ptr_r]; end end - assign out_data = bypass_r ? curr_r : head_r; + assign data_o = bypass_r ? curr_r : head_r; assign empty = empty_r; assign full = full_r; end diff --git a/hw/rtl/pipe_regs/VX_d_e_reg.v b/hw/rtl/pipe_regs/VX_d_e_reg.v index 9bdf1fb8..f4e6b2f8 100644 --- a/hw/rtl/pipe_regs/VX_d_e_reg.v +++ b/hw/rtl/pipe_regs/VX_d_e_reg.v @@ -1,16 +1,16 @@ `include "../VX_define.vh" module VX_d_e_reg ( - input wire clk, + input wire clk, input wire reset, - input wire in_branch_stall, - input wire in_freeze, + input wire branch_stall_i, + input wire freeze_i, VX_frE_to_bckE_req_if frE_to_bckE_req_if, VX_frE_to_bckE_req_if bckE_req_if ); - wire stall = in_freeze; - wire flush = (in_branch_stall == `STALL); + wire stall = freeze_i; + wire flush = (branch_stall_i == `STALL); VX_generic_register #( .N(233 + `NW_BITS-1 + 1 + `NUM_THREADS) diff --git a/hw/rtl/pipe_regs/VX_f_d_reg.v b/hw/rtl/pipe_regs/VX_f_d_reg.v index 83505199..d130f71e 100644 --- a/hw/rtl/pipe_regs/VX_f_d_reg.v +++ b/hw/rtl/pipe_regs/VX_f_d_reg.v @@ -1,9 +1,9 @@ `include "../VX_define.vh" module VX_f_d_reg ( - input wire clk, - input wire reset, - input wire in_freeze, + input wire clk, + input wire reset, + input wire freeze_i, VX_inst_meta_if fe_inst_meta_fd, VX_inst_meta_if fd_inst_meta_de @@ -11,7 +11,7 @@ module VX_f_d_reg ( ); wire flush = 1'b0; - wire stall = in_freeze == 1'b1; + wire stall = freeze_i == 1'b1; VX_generic_register #( .N(64+`NW_BITS-1+1+`NUM_THREADS) ) f_d_reg ( .clk (clk), diff --git a/hw/rtl/pipe_regs/VX_i_d_reg.v b/hw/rtl/pipe_regs/VX_i_d_reg.v index b1c31324..e7da02eb 100644 --- a/hw/rtl/pipe_regs/VX_i_d_reg.v +++ b/hw/rtl/pipe_regs/VX_i_d_reg.v @@ -1,9 +1,9 @@ `include "../VX_define.vh" module VX_i_d_reg ( - input wire clk, - input wire reset, - input wire in_freeze, + input wire clk, + input wire reset, + input wire freeze_i, VX_inst_meta_if fe_inst_meta_fd, VX_inst_meta_if fd_inst_meta_de @@ -11,7 +11,7 @@ module VX_i_d_reg ( ); wire flush = 1'b0; - wire stall = in_freeze == 1'b1; + wire stall = freeze_i == 1'b1; VX_generic_register #( .N( 64 + `NW_BITS-1 + 1 + `NUM_THREADS ) ) i_d_reg ( diff --git a/hw/rtl/shared_memory/VX_priority_encoder_sm.v b/hw/rtl/shared_memory/VX_priority_encoder_sm.v index aa1a2187..75720aaa 100644 --- a/hw/rtl/shared_memory/VX_priority_encoder_sm.v +++ b/hw/rtl/shared_memory/VX_priority_encoder_sm.v @@ -40,8 +40,8 @@ module VX_priority_encoder_sm .NB(NB), .BITS_PER_BANK(BITS_PER_BANK) ) bank_valid ( - .in_valids(use_valid), - .in_addr(in_address), + .valids_i(use_valid), + .addr_i(in_address), .bank_valids(bank_valids) ); diff --git a/hw/rtl/shared_memory/VX_shared_memory.v b/hw/rtl/shared_memory/VX_shared_memory.v index 2ee60eeb..3e8cec75 100644 --- a/hw/rtl/shared_memory/VX_shared_memory.v +++ b/hw/rtl/shared_memory/VX_shared_memory.v @@ -73,13 +73,13 @@ module VX_shared_memory #( ) priority_encoder_sm ( .clk(clk), .reset(reset), - .in_valid(orig_in_valid), - .in_address(in_address), - .in_data(in_data), + .valid_i(orig_in_valid), + .address_i(in_address), + .data_i(in_data), - .out_valid(temp_in_valid), - .out_address(temp_address), - .out_data(temp_in_data), + .valid_o(temp_in_valid), + .address_o(temp_address), + .data_o(temp_in_data), .req_num(req_num), .stall(stall), diff --git a/hw/simulate/simulator.cpp b/hw/simulate/simulator.cpp index a2521154..dafdcb20 100644 --- a/hw/simulate/simulator.cpp +++ b/hw/simulate/simulator.cpp @@ -258,7 +258,7 @@ void Simulator::wait(uint32_t cycles) { } bool Simulator::is_busy() { - return (0 == vortex_->out_ebreak); + return (0 == vortex_->ebreak); } void Simulator::send_snoops(uint32_t mem_addr, uint32_t size) { @@ -295,7 +295,7 @@ bool Simulator::run() { this->reset(); // execute program - while (!vortex_->out_ebreak) { + while (!vortex_->ebreak) { this->step(); } diff --git a/hw/unit_tests/generic_queue/testbench.v b/hw/unit_tests/generic_queue/testbench.v index 3eb57648..f315df33 100644 --- a/hw/unit_tests/generic_queue/testbench.v +++ b/hw/unit_tests/generic_queue/testbench.v @@ -17,10 +17,10 @@ module testbench(); VX_generic_queue #(.DATAW(4), .SIZE(4)) dut ( .clk(clk), .reset(reset), - .in_data(in_data), + .data_i(in_data), .push(push), .pop(pop), - .out_data(out_data), + .data_o(out_data), .empty(empty), .full(full)); diff --git a/simX/cache_simX.v b/simX/cache_simX.v index 1b10ab0e..79354c0e 100644 --- a/simX/cache_simX.v +++ b/simX/cache_simX.v @@ -27,10 +27,10 @@ module cache_simX ( //////////////////// ICACHE /////////////////// VX_icache_request_if VX_icache_req; assign VX_icache_req.pc_address = in_icache_pc_addr; - assign VX_icache_req.out_cache_driver_in_mem_read = (in_icache_valid_pc_addr) ? `LW_MEM_READ : `NO_MEM_READ; - assign VX_icache_req.out_cache_driver_in_mem_write = `NO_MEM_WRITE; - assign VX_icache_req.out_cache_driver_in_valid = in_icache_valid_pc_addr; - assign VX_icache_req.out_cache_driver_in_data = 0; + assign VX_icache_req.cache_driver_in_mem_read_o = (in_icache_valid_pc_addr) ? `LW_MEM_READ : `NO_MEM_READ; + assign VX_icache_req.cache_driver_in_mem_write_o = `NO_MEM_WRITE; + assign VX_icache_req.cache_driver_in_valid_o = in_icache_valid_pc_addr; + assign VX_icache_req.cache_driver_in_data_o = 0; VX_icache_response_if VX_icache_rsp; @@ -53,15 +53,15 @@ module cache_simX ( //////////////////// DCACHE /////////////////// VX_dcache_request_if VX_dcache_req; - assign VX_dcache_req.out_cache_driver_in_mem_read = in_dcache_mem_read; - assign VX_dcache_req.out_cache_driver_in_mem_write = in_dcache_mem_write; - assign VX_dcache_req.out_cache_driver_in_data = 0; + assign VX_dcache_req.cache_driver_in_mem_read_o = in_dcache_mem_read; + assign VX_dcache_req.cache_driver_in_mem_write_o = in_dcache_mem_write; + assign VX_dcache_req.cache_driver_in_data_o = 0; genvar curr_t; for (curr_t = 0; curr_t < `NT; curr_t=curr_t+1) begin - assign VX_dcache_req.out_cache_driver_in_address[curr_t] = in_dcache_in_address[curr_t]; - assign VX_dcache_req.out_cache_driver_in_valid[curr_t] = in_dcache_in_valid[curr_t]; + assign VX_dcache_req.cache_driver_in_address_o[curr_t] = in_dcache_in_address[curr_t]; + assign VX_dcache_req.cache_driver_in_valid_o[curr_t] = in_dcache_in_valid[curr_t]; end VX_dcache_response_if VX_dcache_rsp;