From 1c21110ffe17fcd26049ea5dbece5aa26dae32f5 Mon Sep 17 00:00:00 2001 From: "Lyons, Ethan Tyler" Date: Fri, 8 Nov 2019 10:56:11 -0500 Subject: [PATCH] Add files via upload ICache_In_Place --- rtl/modelsim/vortex_dpi.cpp | 123 ++++++++++++++++++++++++++++++++---- rtl/modelsim/vortex_dpi.h | 4 +- rtl/modelsim/vortex_tb.v | 98 ++++++++++++++++++---------- 3 files changed, 177 insertions(+), 48 deletions(-) diff --git a/rtl/modelsim/vortex_dpi.cpp b/rtl/modelsim/vortex_dpi.cpp index 73207e32..67af68ab 100644 --- a/rtl/modelsim/vortex_dpi.cpp +++ b/rtl/modelsim/vortex_dpi.cpp @@ -15,7 +15,7 @@ extern "C" { void load_file (char * filename); - void ibus_driver (bool clk, unsigned pc_addr, unsigned * instruction); + void ibus_driver (bool clk, unsigned o_m_read_addr, unsigned o_m_evict_addr, bool o_m_valid, svLogicVecVal * o_m_writedata, bool o_m_read_or_write, unsigned cache_banks, unsigned num_words_per_block, svLogicVecVal * i_m_readdata, bool * i_m_ready); void dbus_driver (bool clk, unsigned o_m_read_addr, unsigned o_m_evict_addr, bool o_m_valid, svLogicVecVal * o_m_writedata, bool o_m_read_or_write, unsigned cache_banks, unsigned num_words_per_block, svLogicVecVal * i_m_readdata, bool * i_m_ready); void io_handler (bool clk, bool io_valid, unsigned io_data); void gracefulExit(int); @@ -24,6 +24,8 @@ extern "C" { RAM ram; bool refill; unsigned refill_addr; +bool i_refill; +unsigned i_refill_addr; unsigned num_cycles; @@ -55,30 +57,125 @@ void load_file(char * filename) loadHexImpl(filename, &ram); // printf("Filename: %s\n", filename); refill = false; + i_refill = false; } -void ibus_driver(bool clk, unsigned pc_addr, unsigned * instruction) -{ - // printf("Inside ibus_driver\n"); +void ibus_driver(bool clk, unsigned o_m_read_addr, unsigned o_m_evict_addr, bool o_m_valid, svLogicVecVal * o_m_writedata, bool o_m_read_or_write, unsigned cache_banks, unsigned num_words_per_block, svLogicVecVal * i_m_readdata, bool * i_m_ready) +{ + + + // Default values + { + s_vpi_vecval * real_i_m_readdata = (s_vpi_vecval *) i_m_readdata; + (*i_m_ready) = false; + for (int i = 0; i < cache_banks; i++) + { + for (int j = 0; j < num_words_per_block; j++) + { + + unsigned index = getIndex(i,j, num_words_per_block); + + real_i_m_readdata[index].aval = 0x506070; + + // svGetArrElemPtr2(i_m_readdata, i, j); + // svPutLogicArrElem2VecVal(i_m_readdata, i, j); + // i_m_readdata[getIndex(i,j, num_words_per_block)] = 0; + } + } + } + + if (clk) { - (*instruction) = 0; + // Do nothing on positive edge } else { - num_cycles++; - uint32_t curr_inst = 0; - curr_inst = 0xdeadbeef; - uint32_t u_pc_addr = (uint32_t) (pc_addr); + if (i_refill) + { + // svGetArrElemPtr2((*i_m_readdata), 0,0); + // fprintf(stderr, "--------------------------------\n"); + i_refill = false; - ram.getWord(u_pc_addr, &curr_inst); - // printf("PC_addr: %x, instruction: %x\n", pc_addr, instruction); + *i_m_ready = true; + s_vpi_vecval * real_i_m_readdata = (s_vpi_vecval *) i_m_readdata; + for (int curr_e = 0; curr_e < (cache_banks*num_words_per_block); curr_e++) + { + unsigned new_addr = i_refill_addr + (4*curr_e); + + + unsigned addr_without_byte = new_addr >> 2; + + unsigned bits_per_bank = (int)log2(cache_banks); + // unsigned maskbits_per_bank = calculate_bits_per_bank_num(bits_per_bank); + unsigned maskbits_per_bank = cache_banks - 1; + unsigned bank_num = addr_without_byte & maskbits_per_bank; + unsigned addr_wihtout_bank = addr_without_byte >> bits_per_bank; + unsigned offset_num = addr_wihtout_bank & (num_words_per_block-1); + + unsigned value; + ram.getWord(new_addr, &value); + + fprintf(stdout, "-------- (%x) i_m_readdata[%d][%d] (%d) = %x\n", new_addr, bank_num, offset_num, curr_e, value); + unsigned index = getIndex(bank_num,offset_num, num_words_per_block); + + // fprintf(stderr, "Index: %d (%d, %d) = %x\n", index, bank_num, offset_num, value); + + real_i_m_readdata[index].aval = value; + + } + } + else + { + if (o_m_valid) + { + + s_vpi_vecval * real_o_m_writedata = (s_vpi_vecval *) o_m_writedata; + + if (o_m_read_or_write) + { + // fprintf(stderr, "++++++++++++++++++++++++++++++++\n"); + + for (int curr_e = 0; curr_e < (cache_banks*num_words_per_block); curr_e++) + { + unsigned new_addr = (o_m_evict_addr) + (4*curr_e); + + + unsigned addr_without_byte = new_addr >> 2; + unsigned bits_per_bank = (int)log2(cache_banks); + // unsigned maskbits_per_bank = calculate_bits_per_bank_num(bits_per_bank); + unsigned maskbits_per_bank = cache_banks - 1; + unsigned bank_num = addr_without_byte & maskbits_per_bank; + unsigned addr_wihtout_bank = addr_without_byte >> bits_per_bank; + unsigned offset_num = addr_wihtout_bank & (num_words_per_block-1); + // unsigned offset_num = addr_wihtout_bank & 0x3; + unsigned index = getIndex(bank_num,offset_num, num_words_per_block); + + + + unsigned new_value = real_o_m_writedata[index].aval; + + // new_value = (unsigned *) svGetArrElemPtr2(o_m_writedata, bank_num, offset_num); + // new_value = getElem(o_m_writedata, index); + // unsigned new_value = o_m_writedata[getIndex(bank_num,offset_num, num_words_per_block)]; + + + ram.writeWord( new_addr, &new_value); + + fprintf(stdout, "+++++++ (%x) writeback[%d][%d] (%d) = %x\n", new_addr, bank_num, offset_num, curr_e, new_value); + } + + } + + // Respond next cycle + i_refill = true; + i_refill_addr = o_m_read_addr; + } + } - (*instruction) = curr_inst; } - } diff --git a/rtl/modelsim/vortex_dpi.h b/rtl/modelsim/vortex_dpi.h index be0f1558..4a3509d0 100644 --- a/rtl/modelsim/vortex_dpi.h +++ b/rtl/modelsim/vortex_dpi.h @@ -1,8 +1,8 @@ extern "C" { void load_file (char * filename); - void ibus_driver (bool clk, unsigned pc_addr, unsigned * instruction); - void dbus_driver (bool clk, unsigned o_m_read_addr, unsigned o_m_evict_addr, bool o_m_valid, svLogicVecVal * o_m_writedata, bool o_m_read_or_write, svOpenArrayHandle * i_m_readdata, bool * i_m_ready); + void dbus_driver(bool clk, unsigned o_m_read_addr, unsigned o_m_evict_addr, bool o_m_valid, svLogicVecVal * o_m_writedata, bool o_m_read_or_write, unsigned cache_banks, unsigned num_words_per_block, svLogicVecVal * i_m_readdata, bool * i_m_ready); + void ibus_driver(bool clk, unsigned o_m_read_addr, unsigned o_m_evict_addr, bool o_m_valid, svLogicVecVal * o_m_writedata, bool o_m_read_or_write, unsigned cache_banks, unsigned num_words_per_block, svLogicVecVal * i_m_readdata, bool * i_m_ready); void io_handler (bool clk, bool io_valid, unsigned io_data); void gracefulExit(); } \ No newline at end of file diff --git a/rtl/modelsim/vortex_tb.v b/rtl/modelsim/vortex_tb.v index 7888d10b..7bb7a774 100644 --- a/rtl/modelsim/vortex_tb.v +++ b/rtl/modelsim/vortex_tb.v @@ -10,8 +10,22 @@ import "DPI-C" load_file = function void load_file(input string filename); +/* import "DPI-C" ibus_driver = function void ibus_driver(input logic clk, input int pc_addr, output int instruction); + */ + +import "DPI-C" ibus_driver = function void ibus_driver( input logic clk, + input int o_m_read_addr, + input int o_m_evict_addr, + input logic o_m_valid, + input reg[31:0] o_m_writedata[`ICACHE_BANKS - 1:0][`ICACHE_NUM_WORDS_PER_BLOCK-1:0], + input logic o_m_read_or_write, + input int cache_banks, + input int words_per_block, + // Rsp + output reg[31:0] i_m_readdata[`ICACHE_BANKS - 1:0][`ICACHE_NUM_WORDS_PER_BLOCK-1:0], + output logic i_m_ready); import "DPI-C" dbus_driver = function void dbus_driver( input logic clk, input int o_m_read_addr, @@ -36,24 +50,35 @@ module vortex_tb ( int cycle_num; - reg clk; - reg reset; - reg[31:0] icache_response_instruction; - reg[31:0] icache_request_pc_address; - // IO - reg io_valid; - reg[31:0] io_data; - // Req - reg [31:0] o_m_read_addr; - reg [31:0] o_m_evict_addr; - reg o_m_valid; - reg [31:0] o_m_writedata[`DCACHE_BANKS - 1:0][`DCACHE_NUM_WORDS_PER_BLOCK-1:0]; - reg o_m_read_or_write; +reg clk; +reg reset; +reg[31:0] icache_response_instruction; +reg[31:0] icache_request_pc_address; +// IO +reg io_valid; +reg[31:0] io_data; +// Req + reg [31:0] o_m_read_addr_d; + reg [31:0] o_m_evict_addr_d; + reg o_m_valid_d; + reg [31:0] o_m_writedata_d[`DCACHE_BANKS - 1:0][`DCACHE_NUM_WORDS_PER_BLOCK-1:0]; + reg o_m_read_or_write_d; - // Rsp - reg [31:0] i_m_readdata[`DCACHE_BANKS - 1:0][`DCACHE_NUM_WORDS_PER_BLOCK -1:0]; - reg i_m_ready; - reg out_ebreak; + // Rsp + reg [31:0] i_m_readdata_d[`DCACHE_BANKS - 1:0][`DCACHE_NUM_WORDS_PER_BLOCK-1:0]; + reg i_m_ready_d; + +// Req + reg [31:0] o_m_read_addr_i; + reg [31:0] o_m_evict_addr_i; + reg o_m_valid_i; + reg [31:0] o_m_writedata_i[`ICACHE_BANKS - 1:0][`ICACHE_NUM_WORDS_PER_BLOCK-1:0]; + reg o_m_read_or_write_i; + + // Rsp + reg [31:0] i_m_readdata_i[`ICACHE_BANKS - 1:0][`ICACHE_NUM_WORDS_PER_BLOCK-1:0]; + reg i_m_ready_i; +reg out_ebreak; reg[31:0] hi; @@ -73,25 +98,32 @@ module vortex_tb ( end Vortex vortex( - .clk (clk), - .reset (reset), - .icache_response_instruction(icache_response_instruction), - .icache_request_pc_address (icache_request_pc_address), - .io_valid (io_valid), - .io_data (io_data), - .o_m_read_addr (o_m_read_addr), - .o_m_evict_addr (o_m_evict_addr), - .o_m_valid (o_m_valid), - .o_m_writedata (o_m_writedata), - .o_m_read_or_write (o_m_read_or_write), - .i_m_readdata (i_m_readdata), - .i_m_ready (i_m_ready), - .out_ebreak (out_ebreak) + .clk (clk), + .reset (reset), + .icache_response_instruction (icache_response_instruction), + .icache_request_pc_address (icache_request_pc_address), + .io_valid (io_valid), + .io_data (io_data), + .o_m_read_addr_d (o_m_read_addr_d), + .o_m_evict_addr_d (o_m_evict_addr_d), + .o_m_valid_d (o_m_valid_d), + .o_m_writedata_d (o_m_writedata_d), + .o_m_read_or_write_d (o_m_read_or_write_d), + .i_m_readdata_d (i_m_readdata_d), + .i_m_ready_d (i_m_ready_d), + .o_m_read_addr_i (o_m_read_addr_i), + .o_m_evict_addr_i (o_m_evict_addr_i), + .o_m_valid_i (o_m_valid_i), + .o_m_writedata_i (o_m_writedata_i), + .o_m_read_or_write_i (o_m_read_or_write_i), + .i_m_readdata_i (i_m_readdata_i), + .i_m_ready_i (i_m_ready_i), + .out_ebreak (out_ebreak) ); always @(negedge clk) begin - ibus_driver(clk, icache_request_pc_address, icache_response_instruction); - dbus_driver(clk, o_m_read_addr, o_m_evict_addr, o_m_valid, o_m_writedata, o_m_read_or_write, `DCACHE_BANKS, `DCACHE_NUM_WORDS_PER_BLOCK, i_m_readdata, i_m_ready); + ibus_driver(clk, o_m_read_addr_i, o_m_evict_addr_i, o_m_valid_i, o_m_writedata_i, o_m_read_or_write_i, `ICACHE_BANKS, `ICACHE_NUM_WORDS_PER_BLOCK, i_m_readdata_i, i_m_ready_i); + dbus_driver(clk, o_m_read_addr_d, o_m_evict_addr_d, o_m_valid_d, o_m_writedata_d, o_m_read_or_write_d, `DCACHE_BANKS, `DCACHE_NUM_WORDS_PER_BLOCK, i_m_readdata_d, i_m_ready_d); io_handler (clk, io_valid, io_data); end