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fixed bank_core_req_abr critical path

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This commit is contained in:
Blaise Tine
2020-11-08 18:25:32 -08:00
parent 10505caae1
commit 203a184008
7 changed files with 167 additions and 120 deletions
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14
hw/rtl/VX_lsu_unit.v
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@@ -91,6 +91,10 @@ module VX_lsu_unit #(
wire [1:0] rsp_sext;
reg [`NUM_THREADS-1:0][31:0] rsp_data;
`DEBUG_BLOCK(
reg [`LSUQ_SIZE-1:0][`DCORE_TAG_WIDTH-1:0] pending_tags;
)
reg [`LSUQ_SIZE-1:0][`NUM_THREADS-1:0] mem_rsp_mask;
wire [`DCORE_TAG_ID_BITS-1:0] req_tag, rsp_tag;
@@ -113,7 +117,7 @@ module VX_lsu_unit #(
) lsu_cam (
.clk (clk),
.reset (reset),
.write_addr (req_tag),
.write_addr (req_tag),
.acquire_slot (lsuq_push),
.read_addr (rsp_tag),
.write_data ({req_wid, req_pc, req_rd, req_wb, req_offset, req_sext}),
@@ -126,6 +130,7 @@ module VX_lsu_unit #(
always @(posedge clk) begin
if (lsuq_push) begin
mem_rsp_mask[req_tag] <= req_tmask;
pending_tags[req_tag] <= dcache_req_if.tag;
end
if (lsuq_pop_part) begin
mem_rsp_mask[rsp_tag] <= mem_rsp_mask_n;
@@ -215,6 +220,13 @@ module VX_lsu_unit #(
$display("%t: D$%0d rsp: valid=%b, wid=%0d, PC=%0h, tag=%0h, rd=%0d, data=%0h",
$time, CORE_ID, dcache_rsp_if.valid, rsp_wid, rsp_pc, dcache_rsp_if.tag, rsp_rd, dcache_rsp_if.data);
end
if (lsuq_full) begin
$write("%t: D$%0d queue-full:", $time, CORE_ID);
for (integer j = 0; j < `LSUQ_SIZE; j++) begin
$write(" tag%0d=%0h", j, pending_tags[j]);
end
$write("\n");
end
end
`endif