fix simX build

2020-04-21 01:31:32 -04:00
parent ba4e736782
commit 20ae78f434
31 changed files with 84 additions and 87 deletions
--- a/hw/rtl/VX_csr_data.v
+++ b/hw/rtl/VX_csr_data.v
@@ -1,4 +1,4 @@
-`include "../VX_define.vh"
+`include "VX_define.vh"

 module VX_csr_data (
 	input wire clk,    // Clock
--- a/hw/rtl/VX_define.vh
+++ b/hw/rtl/VX_define.vh
@@ -1,7 +1,7 @@
 `ifndef VX_DEFINE
 `define VX_DEFINE

-`include "./VX_config.vh"
+`include "VX_config.vh"

 // `define QUEUE_FORCE_MLAB 1
 // `define SYN 1
--- a/hw/rtl/cache/VX_cache_config.vh
+++ b/hw/rtl/cache/VX_cache_config.vh
@@ -1,7 +1,7 @@
 `ifndef VX_CACHE_CONFIG
 `define VX_CACHE_CONFIG

-`include "../VX_define.vh"
+`include "VX_define.vh"

 //                                data         tid                   rd  wb    warp_num  read write
 `define MRVQ_METADATA_SIZE      (`WORD_SIZE + `LOG2UP(NUM_REQUESTS) + 5 + 2 + (`NW_BITS) + 3 + 3)
--- a/hw/rtl/interfaces/VX_branch_rsp_if.v
+++ b/hw/rtl/interfaces/VX_branch_rsp_if.v
@@ -1,7 +1,7 @@
 `ifndef VX_BRANCH_RSP
 `define VX_BRANCH_RSP

-`include "../VX_define.vh"
+`include "VX_define.vh"

 interface VX_branch_rsp_if ();

--- a/hw/rtl/interfaces/VX_csr_req_if.v
+++ b/hw/rtl/interfaces/VX_csr_req_if.v
@@ -1,7 +1,7 @@
 `ifndef VX_CSR_REQ
 `define VX_CSR_REQ

-`include "../VX_define.vh"
+`include "VX_define.vh"

 interface VX_csr_req_if ();

--- a/hw/rtl/interfaces/VX_csr_wb_if.v
+++ b/hw/rtl/interfaces/VX_csr_wb_if.v
@@ -1,7 +1,7 @@
 `ifndef VX_CSR_WB_REQ
 `define VX_CSR_WB_REQ

-`include "../VX_define.vh"
+`include "VX_define.vh"

 interface VX_csr_wb_if ();

--- a/hw/rtl/interfaces/VX_exec_unit_req_if.v
+++ b/hw/rtl/interfaces/VX_exec_unit_req_if.v
@@ -1,7 +1,7 @@
 `ifndef VX_EXE_UNIT_REQ_INTER
 `define VX_EXE_UNIT_REQ_INTER

-`include "../VX_define.vh"
+`include "VX_define.vh"

 interface VX_exec_unit_req_if ();

--- a/hw/rtl/interfaces/VX_gpr_data_if.v
+++ b/hw/rtl/interfaces/VX_gpr_data_if.v
@@ -2,7 +2,7 @@
 `ifndef VX_gpr_data_INTER
 `define VX_gpr_data_INTER

-`include "../VX_define.vh"
+`include "VX_define.vh"

 interface VX_gpr_data_if ();

--- a/hw/rtl/interfaces/VX_gpr_jal_if.v
+++ b/hw/rtl/interfaces/VX_gpr_jal_if.v
@@ -1,7 +1,7 @@
 `ifndef VX_GPR_JAL_INTER
 `define VX_GPR_JAL_INTER

-`include "../VX_define.vh"
+`include "VX_define.vh"

 interface VX_gpr_jal_if ();

--- a/hw/rtl/interfaces/VX_gpr_read_if.v
+++ b/hw/rtl/interfaces/VX_gpr_read_if.v
@@ -1,7 +1,7 @@
 `ifndef VX_GPR_READ
 `define VX_GPR_READ

-`include "../VX_define.vh"
+`include "VX_define.vh"

 interface VX_gpr_read_if ();

--- a/hw/rtl/interfaces/VX_gpu_inst_req_if.v
+++ b/hw/rtl/interfaces/VX_gpu_inst_req_if.v
@@ -1,7 +1,7 @@
 `ifndef VX_GPU_INST_REQ_IN
 `define VX_GPU_INST_REQ_IN

-`include "../VX_define.vh"
+`include "VX_define.vh"

 interface VX_gpu_inst_req_if();

--- a/hw/rtl/interfaces/VX_icache_rsp_if.v
+++ b/hw/rtl/interfaces/VX_icache_rsp_if.v
@@ -1,7 +1,7 @@
 `ifndef VX_ICACHE_RSP
 `define VX_ICACHE_RSP

-`include "../VX_define.vh"
+`include "VX_define.vh"

 interface VX_icache_rsp_if ();

--- a/hw/rtl/interfaces/VX_inst_exec_wb_if.v
+++ b/hw/rtl/interfaces/VX_inst_exec_wb_if.v
@@ -2,7 +2,7 @@
 `ifndef VX_EXEC_UNIT_WB_INST_INTER
 `define VX_EXEC_UNIT_WB_INST_INTER

-`include "../VX_define.vh"
+`include "VX_define.vh"

 interface VX_inst_exec_wb_if ();

--- a/hw/rtl/interfaces/VX_inst_mem_wb_if.v
+++ b/hw/rtl/interfaces/VX_inst_mem_wb_if.v
@@ -2,7 +2,7 @@
 `ifndef VX_MEM_WB_INST_INTER
 `define VX_MEM_WB_INST_INTER

-`include "../VX_define.vh"
+`include "VX_define.vh"

 interface VX_inst_mem_wb_if ();

--- a/hw/rtl/interfaces/VX_inst_meta_if.v
+++ b/hw/rtl/interfaces/VX_inst_meta_if.v
@@ -1,7 +1,7 @@
 `ifndef VX_F_D_INTER
 `define VX_F_D_INTER

-`include "../VX_define.vh"
+`include "VX_define.vh"

 interface VX_inst_meta_if ();

--- a/hw/rtl/interfaces/VX_jal_rsp_if.v
+++ b/hw/rtl/interfaces/VX_jal_rsp_if.v
@@ -2,7 +2,7 @@
 `ifndef VX_JAL_RSP
 `define VX_JAL_RSP

-`include "../VX_define.vh"
+`include "VX_define.vh"

 interface VX_jal_rsp_if ();

--- a/hw/rtl/interfaces/VX_join_if.v
+++ b/hw/rtl/interfaces/VX_join_if.v
@@ -2,7 +2,7 @@
 `ifndef VX_JOIN_INTER
 `define VX_JOIN_INTER

-`include "../VX_define.vh"
+`include "VX_define.vh"

 interface VX_join_if ();

--- a/hw/rtl/interfaces/VX_lsu_req_if.v
+++ b/hw/rtl/interfaces/VX_lsu_req_if.v
@@ -2,7 +2,7 @@
 `ifndef VX_LSU_REQ_INTER
 `define VX_LSU_REQ_INTER

-`include "../VX_define.vh"
+`include "VX_define.vh"

 interface VX_lsu_req_if ();

--- a/hw/rtl/interfaces/VX_mw_wb_if.v
+++ b/hw/rtl/interfaces/VX_mw_wb_if.v
@@ -2,7 +2,7 @@
 `ifndef VX_MW_WB_INTER
 `define VX_MW_WB_INTER

-`include "../VX_define.vh"
+`include "VX_define.vh"

 interface VX_mw_wb_if ();

--- a/hw/rtl/interfaces/VX_warp_ctl_if.v
+++ b/hw/rtl/interfaces/VX_warp_ctl_if.v
@@ -2,7 +2,7 @@
 `ifndef VX_WARP_CTL_INTER
 `define VX_WARP_CTL_INTER

-`include "../VX_define.vh"
+`include "VX_define.vh"

 interface VX_warp_ctl_if ();

--- a/hw/rtl/interfaces/VX_wb_if.v
+++ b/hw/rtl/interfaces/VX_wb_if.v
@@ -1,7 +1,7 @@
 `ifndef VX_WB_INTER
 `define VX_WB_INTER

-`include "../VX_define.vh"
+`include "VX_define.vh"

 interface VX_wb_if ();

--- a/hw/rtl/interfaces/VX_wstall_if.v
+++ b/hw/rtl/interfaces/VX_wstall_if.v
@@ -1,7 +1,7 @@
 `ifndef VX_WSTALL_INTER
 `define VX_WSTALL_INTER

-`include "../VX_define.vh"
+`include "VX_define.vh"

 interface VX_wstall_if();

--- a/hw/rtl/libs/VX_generic_priority_encoder.v
+++ b/hw/rtl/libs/VX_generic_priority_encoder.v
@@ -1,13 +1,8 @@
-`ifndef VX_GENERIC_PRIORITY_ENCODER
-`define VX_GENERIC_PRIORITY_ENCODER
-
 `include "VX_define.vh"

-module VX_generic_priority_encoder
-  #(
-  	parameter N = 1
-  )
-  (
+module VX_generic_priority_encoder #(
+	parameter N = 1
+)  (
    input  wire[N-1:0] valids,
    //output reg[$clog2(N)-1:0] index,
    output reg[(`LOG2UP(N))-1:0] index,
@@ -27,6 +22,5 @@ module VX_generic_priority_encoder
 			end
 		end
 	end
-endmodule
-
-`endif
+	
+endmodule
--- a/hw/rtl/libs/VX_priority_encoder.v
+++ b/hw/rtl/libs/VX_priority_encoder.v
@@ -17,4 +17,5 @@ module VX_priority_encoder (
 			end
 		end
 	end
+	
 endmodule
--- a/hw/rtl/libs/VX_priority_encoder_w_mask.v
+++ b/hw/rtl/libs/VX_priority_encoder_w_mask.v
@@ -1,4 +1,5 @@
 `include "VX_define.vh"
+
 module VX_priority_encoder_w_mask #(
 	parameter N = 10
 )  (
@@ -27,4 +28,5 @@ module VX_priority_encoder_w_mask #(
 	end

 	assign mask = found ? (1 << index) : 0;
+	
 endmodule
--- a/hw/rtl/pipe_regs/VX_d_e_reg.v
+++ b/hw/rtl/pipe_regs/VX_d_e_reg.v
@@ -1,4 +1,4 @@
-`include "../VX_define.vh"
+`include "VX_define.vh"

 module VX_d_e_reg (
 	input wire        		clk,
--- a/hw/rtl/pipe_regs/VX_f_d_reg.v
+++ b/hw/rtl/pipe_regs/VX_f_d_reg.v
@@ -1,4 +1,4 @@
-`include "../VX_define.vh"
+`include "VX_define.vh"

 module VX_f_d_reg (
 	input wire		clk,
--- a/hw/rtl/pipe_regs/VX_i_d_reg.v
+++ b/hw/rtl/pipe_regs/VX_i_d_reg.v
@@ -1,4 +1,4 @@
-`include "../VX_define.vh"
+`include "VX_define.vh"

 module VX_i_d_reg (
 	input wire          clk,