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fix simX build

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This commit is contained in:
Blaise Tine
2020-04-21 01:31:32 -04:00
parent ba4e736782
commit 20ae78f434
31 changed files with 84 additions and 87 deletions
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2
hw/modelsim/vortex_tb.v
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@@ -1,4 +1,4 @@
`include "../VX_define.vh" `include "VX_define.vh"
//`define NUM_BANKS 8 //`define NUM_BANKS 8
//`define NUM_WORDS_PER_BLOCK 4 //`define NUM_WORDS_PER_BLOCK 4

2
hw/rtl/VX_csr_data.v
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@@ -1,4 +1,4 @@
`include "../VX_define.vh" `include "VX_define.vh"
module VX_csr_data ( module VX_csr_data (
input wire clk, // Clock input wire clk, // Clock

2
hw/rtl/VX_define.vh
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@@ -1,7 +1,7 @@
`ifndef VX_DEFINE `ifndef VX_DEFINE
`define VX_DEFINE `define VX_DEFINE
`include "./VX_config.vh" `include "VX_config.vh"
// `define QUEUE_FORCE_MLAB 1 // `define QUEUE_FORCE_MLAB 1
// `define SYN 1 // `define SYN 1

2
hw/rtl/cache/VX_cache_config.vh vendored
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@@ -1,7 +1,7 @@
`ifndef VX_CACHE_CONFIG `ifndef VX_CACHE_CONFIG
`define VX_CACHE_CONFIG `define VX_CACHE_CONFIG
`include "../VX_define.vh" `include "VX_define.vh"
// data tid rd wb warp_num read write // data tid rd wb warp_num read write
`define MRVQ_METADATA_SIZE (`WORD_SIZE + `LOG2UP(NUM_REQUESTS) + 5 + 2 + (`NW_BITS) + 3 + 3) `define MRVQ_METADATA_SIZE (`WORD_SIZE + `LOG2UP(NUM_REQUESTS) + 5 + 2 + (`NW_BITS) + 3 + 3)

2
hw/rtl/interfaces/VX_branch_rsp_if.v
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@@ -1,7 +1,7 @@
`ifndef VX_BRANCH_RSP `ifndef VX_BRANCH_RSP
`define VX_BRANCH_RSP `define VX_BRANCH_RSP
`include "../VX_define.vh" `include "VX_define.vh"
interface VX_branch_rsp_if (); interface VX_branch_rsp_if ();

2
hw/rtl/interfaces/VX_csr_req_if.v
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@@ -1,7 +1,7 @@
`ifndef VX_CSR_REQ `ifndef VX_CSR_REQ
`define VX_CSR_REQ `define VX_CSR_REQ
`include "../VX_define.vh" `include "VX_define.vh"
interface VX_csr_req_if (); interface VX_csr_req_if ();

2
hw/rtl/interfaces/VX_csr_wb_if.v
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@@ -1,7 +1,7 @@
`ifndef VX_CSR_WB_REQ `ifndef VX_CSR_WB_REQ
`define VX_CSR_WB_REQ `define VX_CSR_WB_REQ
`include "../VX_define.vh" `include "VX_define.vh"
interface VX_csr_wb_if (); interface VX_csr_wb_if ();

2
hw/rtl/interfaces/VX_exec_unit_req_if.v
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@@ -1,7 +1,7 @@
`ifndef VX_EXE_UNIT_REQ_INTER `ifndef VX_EXE_UNIT_REQ_INTER
`define VX_EXE_UNIT_REQ_INTER `define VX_EXE_UNIT_REQ_INTER
`include "../VX_define.vh" `include "VX_define.vh"
interface VX_exec_unit_req_if (); interface VX_exec_unit_req_if ();

2
hw/rtl/interfaces/VX_gpr_data_if.v
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@@ -2,7 +2,7 @@
`ifndef VX_gpr_data_INTER `ifndef VX_gpr_data_INTER
`define VX_gpr_data_INTER `define VX_gpr_data_INTER
`include "../VX_define.vh" `include "VX_define.vh"
interface VX_gpr_data_if (); interface VX_gpr_data_if ();

2
hw/rtl/interfaces/VX_gpr_jal_if.v
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@@ -1,7 +1,7 @@
`ifndef VX_GPR_JAL_INTER `ifndef VX_GPR_JAL_INTER
`define VX_GPR_JAL_INTER `define VX_GPR_JAL_INTER
`include "../VX_define.vh" `include "VX_define.vh"
interface VX_gpr_jal_if (); interface VX_gpr_jal_if ();

2
hw/rtl/interfaces/VX_gpr_read_if.v
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@@ -1,7 +1,7 @@
`ifndef VX_GPR_READ `ifndef VX_GPR_READ
`define VX_GPR_READ `define VX_GPR_READ
`include "../VX_define.vh" `include "VX_define.vh"
interface VX_gpr_read_if (); interface VX_gpr_read_if ();

2
hw/rtl/interfaces/VX_gpu_inst_req_if.v
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@@ -1,7 +1,7 @@
`ifndef VX_GPU_INST_REQ_IN `ifndef VX_GPU_INST_REQ_IN
`define VX_GPU_INST_REQ_IN `define VX_GPU_INST_REQ_IN
`include "../VX_define.vh" `include "VX_define.vh"
interface VX_gpu_inst_req_if(); interface VX_gpu_inst_req_if();

2
hw/rtl/interfaces/VX_icache_rsp_if.v
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@@ -1,7 +1,7 @@
`ifndef VX_ICACHE_RSP `ifndef VX_ICACHE_RSP
`define VX_ICACHE_RSP `define VX_ICACHE_RSP
`include "../VX_define.vh" `include "VX_define.vh"
interface VX_icache_rsp_if (); interface VX_icache_rsp_if ();

2
hw/rtl/interfaces/VX_inst_exec_wb_if.v
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@@ -2,7 +2,7 @@
`ifndef VX_EXEC_UNIT_WB_INST_INTER `ifndef VX_EXEC_UNIT_WB_INST_INTER
`define VX_EXEC_UNIT_WB_INST_INTER `define VX_EXEC_UNIT_WB_INST_INTER
`include "../VX_define.vh" `include "VX_define.vh"
interface VX_inst_exec_wb_if (); interface VX_inst_exec_wb_if ();

2
hw/rtl/interfaces/VX_inst_mem_wb_if.v
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@@ -2,7 +2,7 @@
`ifndef VX_MEM_WB_INST_INTER `ifndef VX_MEM_WB_INST_INTER
`define VX_MEM_WB_INST_INTER `define VX_MEM_WB_INST_INTER
`include "../VX_define.vh" `include "VX_define.vh"
interface VX_inst_mem_wb_if (); interface VX_inst_mem_wb_if ();

2
hw/rtl/interfaces/VX_inst_meta_if.v
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@@ -1,7 +1,7 @@
`ifndef VX_F_D_INTER `ifndef VX_F_D_INTER
`define VX_F_D_INTER `define VX_F_D_INTER
`include "../VX_define.vh" `include "VX_define.vh"
interface VX_inst_meta_if (); interface VX_inst_meta_if ();

2
hw/rtl/interfaces/VX_jal_rsp_if.v
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@@ -2,7 +2,7 @@
`ifndef VX_JAL_RSP `ifndef VX_JAL_RSP
`define VX_JAL_RSP `define VX_JAL_RSP
`include "../VX_define.vh" `include "VX_define.vh"
interface VX_jal_rsp_if (); interface VX_jal_rsp_if ();

2
hw/rtl/interfaces/VX_join_if.v
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@@ -2,7 +2,7 @@
`ifndef VX_JOIN_INTER `ifndef VX_JOIN_INTER
`define VX_JOIN_INTER `define VX_JOIN_INTER
`include "../VX_define.vh" `include "VX_define.vh"
interface VX_join_if (); interface VX_join_if ();

2
hw/rtl/interfaces/VX_lsu_req_if.v
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@@ -2,7 +2,7 @@
`ifndef VX_LSU_REQ_INTER `ifndef VX_LSU_REQ_INTER
`define VX_LSU_REQ_INTER `define VX_LSU_REQ_INTER
`include "../VX_define.vh" `include "VX_define.vh"
interface VX_lsu_req_if (); interface VX_lsu_req_if ();

2
hw/rtl/interfaces/VX_mw_wb_if.v
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@@ -2,7 +2,7 @@
`ifndef VX_MW_WB_INTER `ifndef VX_MW_WB_INTER
`define VX_MW_WB_INTER `define VX_MW_WB_INTER
`include "../VX_define.vh" `include "VX_define.vh"
interface VX_mw_wb_if (); interface VX_mw_wb_if ();

2
hw/rtl/interfaces/VX_warp_ctl_if.v
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@@ -2,7 +2,7 @@
`ifndef VX_WARP_CTL_INTER `ifndef VX_WARP_CTL_INTER
`define VX_WARP_CTL_INTER `define VX_WARP_CTL_INTER
`include "../VX_define.vh" `include "VX_define.vh"
interface VX_warp_ctl_if (); interface VX_warp_ctl_if ();

2
hw/rtl/interfaces/VX_wb_if.v
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@@ -1,7 +1,7 @@
`ifndef VX_WB_INTER `ifndef VX_WB_INTER
`define VX_WB_INTER `define VX_WB_INTER
`include "../VX_define.vh" `include "VX_define.vh"
interface VX_wb_if (); interface VX_wb_if ();

2
hw/rtl/interfaces/VX_wstall_if.v
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@@ -1,7 +1,7 @@
`ifndef VX_WSTALL_INTER `ifndef VX_WSTALL_INTER
`define VX_WSTALL_INTER `define VX_WSTALL_INTER
`include "../VX_define.vh" `include "VX_define.vh"
interface VX_wstall_if(); interface VX_wstall_if();

12
hw/rtl/libs/VX_generic_priority_encoder.v
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@@ -1,13 +1,8 @@
`ifndef VX_GENERIC_PRIORITY_ENCODER
`define VX_GENERIC_PRIORITY_ENCODER
`include "VX_define.vh" `include "VX_define.vh"
module VX_generic_priority_encoder module VX_generic_priority_encoder #(
#(
parameter N = 1 parameter N = 1
) ) (
(
input wire[N-1:0] valids, input wire[N-1:0] valids,
//output reg[$clog2(N)-1:0] index, //output reg[$clog2(N)-1:0] index,
output reg[(`LOG2UP(N))-1:0] index, output reg[(`LOG2UP(N))-1:0] index,
@@ -27,6 +22,5 @@ module VX_generic_priority_encoder
end end
end end
end end
endmodule
`endif endmodule

1
hw/rtl/libs/VX_priority_encoder.v
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@@ -17,4 +17,5 @@ module VX_priority_encoder (
end end
end end
end end
endmodule endmodule

2
hw/rtl/libs/VX_priority_encoder_w_mask.v
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@@ -1,4 +1,5 @@
`include "VX_define.vh" `include "VX_define.vh"
module VX_priority_encoder_w_mask #( module VX_priority_encoder_w_mask #(
parameter N = 10 parameter N = 10
) ( ) (
@@ -27,4 +28,5 @@ module VX_priority_encoder_w_mask #(
end end
assign mask = found ? (1 << index) : 0; assign mask = found ? (1 << index) : 0;
endmodule endmodule

2
hw/rtl/pipe_regs/VX_d_e_reg.v
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@@ -1,4 +1,4 @@
`include "../VX_define.vh" `include "VX_define.vh"
module VX_d_e_reg ( module VX_d_e_reg (
input wire clk, input wire clk,

2
hw/rtl/pipe_regs/VX_f_d_reg.v
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@@ -1,4 +1,4 @@
`include "../VX_define.vh" `include "VX_define.vh"
module VX_f_d_reg ( module VX_f_d_reg (
input wire clk, input wire clk,

2
hw/rtl/pipe_regs/VX_i_d_reg.v
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@@ -1,4 +1,4 @@
`include "../VX_define.vh" `include "VX_define.vh"
module VX_i_d_reg ( module VX_i_d_reg (
input wire clk, input wire clk,

38
simX/cache_simX.v
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@@ -1,11 +1,11 @@
`include "VX_define.vh" `include "VX_define.v"
module cache_simX ( module cache_simX (
input wire clk, // Clock input wire clk, // Clock
input wire reset, input wire reset,
// Icache // Icache
input wire[31:0] cache_pc_addr, input wire[31:0] icache_pc_addr,
input wire icache_valid_pc_addr, input wire icache_valid_pc_addr,
output wire icache_stall, output wire icache_stall,
@@ -18,17 +18,17 @@ module cache_simX (
); );
//////////////////// ICACHE /////////////////// //////////////////// ICACHE ///////////////////
VX_icache_request_if VX_icache_req; VX_icache_request_inter VX_icache_req;
assign VX_icache_req.pc_address = cache_pc_addr; assign VX_icache_req.pc_address = icache_pc_addr;
assign VX_icache_req.cache_driver_in_mem_read_o = (icache_valid_pc_addr) ? `LW_MEM_READ : `NO_MEM_READ; assign VX_icache_req.out_cache_driver_in_mem_read = (icache_valid_pc_addr) ? `LW_MEM_READ : `NO_MEM_READ;
assign VX_icache_req.cache_driver_in_mem_write_o = `NO_MEM_WRITE; assign VX_icache_req.out_cache_driver_in_mem_write = `NO_MEM_WRITE;
assign VX_icache_req.cache_driver_in_valid_o = icache_valid_pc_addr; assign VX_icache_req.out_cache_driver_in_valid = icache_valid_pc_addr;
assign VX_icache_req.cache_driver_in_data_o = 0; assign VX_icache_req.out_cache_driver_in_data = 0;
VX_icache_rsp_if VX_icache_rsp; VX_icache_response_inter VX_icache_rsp;
assign icache_stall = VX_icache_rsp.delay; assign icache_stall = VX_icache_rsp.delay;
VX_dram_req_rsp_if #( VX_dram_req_rsp_inter #(
.NUMBER_BANKS(`ICACHE_BANKS), .NUMBER_BANKS(`ICACHE_BANKS),
.NUM_WORDS_PER_BLOCK(`ICACHE_NUM_WORDS_PER_BLOCK) .NUM_WORDS_PER_BLOCK(`ICACHE_NUM_WORDS_PER_BLOCK)
@@ -41,22 +41,22 @@ module cache_simX (
//////////////////// DCACHE /////////////////// //////////////////// DCACHE ///////////////////
VX_dcache_request_if VX_dcache_req; VX_dcache_request_inter VX_dcache_req;
assign VX_dcache_req.cache_driver_in_mem_read_o = dcache_mem_read; assign VX_dcache_req.out_cache_driver_in_mem_read = dcache_mem_read;
assign VX_dcache_req.cache_driver_in_mem_write_o = dcache_mem_write; assign VX_dcache_req.out_cache_driver_in_mem_write = dcache_mem_write;
assign VX_dcache_req.cache_driver_in_data_o = 0; assign VX_dcache_req.out_cache_driver_in_data = 0;
genvar curr_t; genvar curr_t;
for (curr_t = 0; curr_t < `NT; curr_t=curr_t+1) for (curr_t = 0; curr_t < `NT; curr_t=curr_t+1)
begin begin
assign VX_dcache_req.cache_driver_in_address_o[curr_t] = dcache_in_addr[curr_t]; assign VX_dcache_req.out_cache_driver_in_address[curr_t] = dcache_in_addr[curr_t];
assign VX_dcache_req.cache_driver_in_valid_o[curr_t] = dcache_in_valid[curr_t]; assign VX_dcache_req.out_cache_driver_in_valid[curr_t] = dcache_in_valid[curr_t];
end end
VX_dcache_response_if VX_dcache_rsp; VX_dcache_response_inter VX_dcache_rsp;
assign dcache_stall = VX_dcache_rsp.delay; assign dcache_stall = VX_dcache_rsp.delay;
VX_dram_req_rsp_if #( VX_dram_req_rsp_inter #(
.NUMBER_BANKS(`DCACHE_BANKS), .NUMBER_BANKS(`DCACHE_BANKS),
.NUM_WORDS_PER_BLOCK(`DCACHE_NUM_WORDS_PER_BLOCK) .NUM_WORDS_PER_BLOCK(`DCACHE_NUM_WORDS_PER_BLOCK)
@@ -66,7 +66,7 @@ module cache_simX (
reg dcache_i_m_ready; reg dcache_i_m_ready;
assign VX_dram_req_rsp.i_m_ready = dcache_i_m_ready; assign VX_dram_req_rsp.i_m_ready = dcache_i_m_ready;
VX_dmem_ctrl dmem_controller ( VX_dmem_controller dmem_ctrl (
.clk (clk), .clk (clk),
.reset (reset), .reset (reset),
.VX_dram_req_rsp (VX_dram_req_rsp), .VX_dram_req_rsp (VX_dram_req_rsp),

62
simX/core.cpp
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@@ -255,16 +255,16 @@ void Core::getCacheDelays(trace_inst_t * trace_inst)
cache_simulator->eval(); cache_simulator->eval();
// m_trace->dump(2*curr_cycle); // m_trace->dump(2*curr_cycle);
cache_simulator->in_icache_pc_addr = trace_inst->pc; cache_simulator->icache_pc_addr = trace_inst->pc;
cache_simulator->in_icache_valid_pc_addr = 1; cache_simulator->icache_valid_pc_addr = 1;
// DCache start // DCache start
cache_simulator->in_dcache_mem_read = in_dcache_mem_read; cache_simulator->dcache_mem_read = in_dcache_mem_read;
cache_simulator->in_dcache_mem_write = in_dcache_mem_write; cache_simulator->dcache_mem_write = in_dcache_mem_write;
for (int cur_t = 0; cur_t < a.getNThds(); cur_t++) for (int cur_t = 0; cur_t < a.getNThds(); cur_t++)
{ {
cache_simulator->in_dcache_in_valid[cur_t] = in_dcache_in_valid[cur_t]; cache_simulator->dcache_in_valid[cur_t] = in_dcache_in_valid[cur_t];
cache_simulator->in_dcache_in_address[cur_t] = in_dcache_in_address[cur_t]; cache_simulator->dcache_in_addr[cur_t] = in_dcache_in_address[cur_t];
} }
// DCache end // DCache end
cache_simulator->clk = 0; cache_simulator->clk = 0;
@@ -273,39 +273,39 @@ void Core::getCacheDelays(trace_inst_t * trace_inst)
curr_cycle++; curr_cycle++;
while((cache_simulator->out_icache_stall || cache_simulator->out_dcache_stall)) while((cache_simulator->icache_stall || cache_simulator->dcache_stall))
{ {
////////// Feed input ////////// Feed input
if (cache_simulator->out_icache_stall) if (cache_simulator->icache_stall)
{ {
cache_simulator->in_icache_pc_addr = trace_inst->pc; cache_simulator->icache_pc_addr = trace_inst->pc;
cache_simulator->in_icache_valid_pc_addr = 1; cache_simulator->icache_valid_pc_addr = 1;
trace_inst->fetch_stall_cycles++; trace_inst->fetch_stall_cycles++;
} }
else else
{ {
cache_simulator->in_icache_valid_pc_addr = 0; cache_simulator->icache_valid_pc_addr = 0;
} }
if (cache_simulator->out_dcache_stall) if (cache_simulator->dcache_stall)
{ {
cache_simulator->in_dcache_mem_read = in_dcache_mem_read; cache_simulator->dcache_mem_read = in_dcache_mem_read;
cache_simulator->in_dcache_mem_write = in_dcache_mem_write; cache_simulator->dcache_mem_write = in_dcache_mem_write;
for (int cur_t = 0; cur_t < a.getNThds(); cur_t++) for (int cur_t = 0; cur_t < a.getNThds(); cur_t++)
{ {
cache_simulator->in_dcache_in_valid[cur_t] = in_dcache_in_valid[cur_t]; cache_simulator->dcache_in_valid[cur_t] = in_dcache_in_valid[cur_t];
cache_simulator->in_dcache_in_address[cur_t] = in_dcache_in_address[cur_t]; cache_simulator->dcache_in_addr[cur_t] = in_dcache_in_address[cur_t];
} }
trace_inst->mem_stall_cycles++; trace_inst->mem_stall_cycles++;
} }
else else
{ {
cache_simulator->in_dcache_mem_read = NO_MEM_READ; cache_simulator->dcache_mem_read = NO_MEM_READ;
cache_simulator->in_dcache_mem_write = NO_MEM_WRITE; cache_simulator->dcache_mem_write = NO_MEM_WRITE;
for (int cur_t = 0; cur_t < a.getNThds(); cur_t++) for (int cur_t = 0; cur_t < a.getNThds(); cur_t++)
{ {
cache_simulator->in_dcache_in_valid[cur_t] = 0; cache_simulator->dcache_in_valid[cur_t] = 0;
} }
} }
@@ -314,33 +314,33 @@ void Core::getCacheDelays(trace_inst_t * trace_inst)
// m_trace->dump(2*curr_cycle); // m_trace->dump(2*curr_cycle);
//////// Feed input //////// Feed input
if (cache_simulator->out_icache_stall) if (cache_simulator->icache_stall)
{ {
cache_simulator->in_icache_pc_addr = trace_inst->pc; cache_simulator->icache_pc_addr = trace_inst->pc;
cache_simulator->in_icache_valid_pc_addr = 1; cache_simulator->icache_valid_pc_addr = 1;
} }
else else
{ {
cache_simulator->in_icache_valid_pc_addr = 0; cache_simulator->icache_valid_pc_addr = 0;
} }
if (cache_simulator->out_dcache_stall) if (cache_simulator->dcache_stall)
{ {
cache_simulator->in_dcache_mem_read = in_dcache_mem_read; cache_simulator->dcache_mem_read = in_dcache_mem_read;
cache_simulator->in_dcache_mem_write = in_dcache_mem_write; cache_simulator->dcache_mem_write = in_dcache_mem_write;
for (int cur_t = 0; cur_t < a.getNThds(); cur_t++) for (int cur_t = 0; cur_t < a.getNThds(); cur_t++)
{ {
cache_simulator->in_dcache_in_valid[cur_t] = in_dcache_in_valid[cur_t]; cache_simulator->dcache_in_valid[cur_t] = in_dcache_in_valid[cur_t];
cache_simulator->in_dcache_in_address[cur_t] = in_dcache_in_address[cur_t]; cache_simulator->dcache_in_addr[cur_t] = in_dcache_in_address[cur_t];
} }
} }
else else
{ {
cache_simulator->in_dcache_mem_read = NO_MEM_READ; cache_simulator->dcache_mem_read = NO_MEM_READ;
cache_simulator->in_dcache_mem_write = NO_MEM_WRITE; cache_simulator->dcache_mem_write = NO_MEM_WRITE;
for (int cur_t = 0; cur_t < a.getNThds(); cur_t++) for (int cur_t = 0; cur_t < a.getNThds(); cur_t++)
{ {
cache_simulator->in_dcache_in_valid[cur_t] = 0; cache_simulator->dcache_in_valid[cur_t] = 0;
} }
} }