Fixed Single Core with Optimizations

2020-06-28 19:38:36 -07:00
parent 567376971e
commit 21566cdcd7
3 changed files with 9 additions and 8 deletions
--- a/hw/rtl/VX_lsu_unit.v
+++ b/hw/rtl/VX_lsu_unit.v
@@ -21,7 +21,7 @@ module VX_lsu_unit #(
    output wire             delay
 );

-    VX_wb_if                mem_wb_if;
+    VX_wb_if                mem_wb_if();

    wire[`NUM_THREADS-1:0][31:0]    use_address;
    wire[`NUM_THREADS-1:0][31:0]    use_store_data;
@@ -159,7 +159,7 @@ module VX_lsu_unit #(
    assign mem_wb_if.data  = core_rsp_data;

    // Can't accept new response
-    assign dcache_rsp_if.core_rsp_ready = !no_slot_mem & (|mem_wb_if_p1.valid);
+    assign dcache_rsp_if.core_rsp_ready = !(no_slot_mem & (|mem_wb_if_p1.valid));