cache area optimization by disabling BRAM read-during-write bypassing for tag/data stores

hw/rtl/cache/VX_bank.v

@@ -162,6 +162,8 @@ module VX_bank #(
 
     wire creq_fire = creq_valid && creq_ready;
 
+    wire fill_in_st0 = valid_st0 && is_fill_st0;
+    
     // determine which queue to pop next in priority order 
     wire mshr_grant  = 1;
     wire mshr_enable = mshr_grant && mshr_valid; 
@@ -172,6 +174,7 @@ module VX_bank #(
     wire creq_grant  = !mshr_enable && !mrsq_enable && !flush_enable;
     
     wire mshr_ready = mshr_grant
+                   && !fill_in_st0      // prevent tag read-during-write with fill
                    && !crsq_stall;      // ensure core response ready
 
     assign mem_rsp_ready = mrsq_grant

hw/rtl/cache/VX_data_access.v

@@ -65,7 +65,8 @@ module VX_data_access #(
     VX_sp_ram #(
         .DATAW      (CACHE_LINE_SIZE * 8),
         .SIZE       (`LINES_PER_BANK),
-        .BYTEENW (BYTEENW)
+        .BYTEENW    (BYTEENW),
+        .NO_RWCHECK (1)
     ) data_store (
         .clk   (clk),        
         .addr  (line_addr),

hw/rtl/cache/VX_shared_mem.v

@@ -173,7 +173,8 @@ module VX_shared_mem #(
         VX_sp_ram #(
             .DATAW      (`WORD_WIDTH),
             .SIZE       (`LINES_PER_BANK),
-            .BYTEENW (WORD_SIZE)
+            .BYTEENW    (WORD_SIZE),
+            .NO_RWCHECK (1)
         ) data_store (
             .clk   (clk),
             .addr  (per_bank_core_req_addr[i]),

hw/rtl/cache/VX_tag_access.v

@@ -49,7 +49,8 @@ module VX_tag_access #(
         .DATAW       (`TAG_SELECT_BITS + 1),
         .SIZE        (`LINES_PER_BANK),
         .INIT_ENABLE (1),
-        .INIT_VALUE(0)
+        .INIT_VALUE  (0),
+        .NO_RWCHECK  (1)
     ) tag_store (
         .clk(  clk),                 
         .addr  (line_addr),   

hw/syn/opae/fpga_prog.sh

@@ -0,0 +1,7 @@
+#!/bin/bash
+
+# FPGA programming
+# first argument is the bitstream
+
+echo "fpgaconf --bus 0xaf $1"
+fpgaconf --bus 0xaf $1