RTL code refactoring

This commit is contained in:
Blaise Tine
2020-04-23 12:38:44 -04:00
parent f0e257bc8e
commit 28d054e295
39 changed files with 179 additions and 225 deletions

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@@ -1,5 +1,5 @@
`ifndef VX_BRANCH_RSP
`define VX_BRANCH_RSP
`ifndef VX_BRANCH_RSP_IF
`define VX_BRANCH_RSP_IF
`include "VX_define.vh"

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@@ -1,9 +1,9 @@
`ifndef VX_GPU_DCACHE_REQ
`define VX_GPU_DCACHE_REQ
`ifndef VX_CACHE_CORE_REQ_IF
`define VX_CACHE_CORE_REQ_IF
`include "../cache/VX_cache_config.vh"
interface VX_gpu_dcache_req_if #(
interface VX_cache_core_req_if #(
parameter NUM_REQUESTS = 32
) ();

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@@ -1,9 +1,9 @@
`ifndef VX_GPU_DCACHE_RSP
`define VX_GPU_DCACHE_RSP
`ifndef VX_CACHE_CORE_RSP_IF
`define VX_CACHE_CORE_RSP_IF
`include "../cache/VX_cache_config.vh"
interface VX_gpu_dcache_rsp_if #(
interface VX_cache_core_rsp_if #(
parameter NUM_REQUESTS = 32
) ();

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@@ -1,9 +1,9 @@
`ifndef VX_GPU_DRAM_DCACHE_REQ
`define VX_GPU_DRAM_DCACHE_REQ
`ifndef VX_CACHE_DRAM_REQ_IF
`define VX_CACHE_DRAM_REQ_IF
`include "../cache/VX_cache_config.vh"
interface VX_gpu_dcache_dram_req_if #(
interface VX_cache_dram_req_if #(
parameter BANK_LINE_WORDS = 2
) ();

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@@ -1,9 +1,9 @@
`ifndef VX_GPU_DRAM_DCACHE_RSP
`define VX_GPU_DRAM_DCACHE_RSP
`ifndef VX_CACHE_DRAM_RSP_IF
`define VX_CACHE_DRAM_RSP_IF
`include "../cache/VX_cache_config.vh"
interface VX_gpu_dcache_dram_rsp_if #(
interface VX_cache_dram_rsp_if #(
parameter BANK_LINE_WORDS = 2
) ();
// DRAM Response

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@@ -1,9 +1,9 @@
`ifndef VX_GPU_SNP_REQ_RSP
`define VX_GPU_SNP_REQ_RSP
`ifndef VX_CACHE_SNP_REQ_RSP_IF
`define VX_CACHE_SNP_REQ_RSP_IF
`include "../cache/VX_cache_config.vh"
interface VX_gpu_snp_req_rsp_if ();
interface VX_cache_snp_req_rsp_if ();
// Snoop request
wire snp_req_valid;

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@@ -1,5 +1,5 @@
`ifndef VX_CSR_REQ
`define VX_CSR_REQ
`ifndef VX_CSR_REQ_IF
`define VX_CSR_REQ_IF
`include "VX_define.vh"

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@@ -1,5 +1,5 @@
`ifndef VX_CSR_WB_REQ
`define VX_CSR_WB_REQ
`ifndef VX_CSR_WB_IF
`define VX_CSR_WB_IF
`include "VX_define.vh"

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@@ -1,5 +1,5 @@
`ifndef VX_EXE_UNIT_REQ_INTER
`define VX_EXE_UNIT_REQ_INTER
`ifndef VX_EXE_UNIT_REQ_IF
`define VX_EXE_UNIT_REQ_IF
`include "VX_define.vh"

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@@ -1,5 +1,5 @@
`ifndef VX_FrE_to_BE_INTER
`define VX_FrE_to_BE_INTER
`ifndef VX_FrE_to_BCKBE_REQ_IF
`define VX_FrE_to_BCKBE_REQ_IF
`include "VX_define.vh"

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@@ -1,9 +1,9 @@
`ifndef VX_GPU_INST_REQ_IN
`define VX_GPU_INST_REQ_IN
`ifndef VX_GPGPU_INST_REQ_IF
`define VX_GPGPU_INST_REQ_IF
`include "VX_define.vh"
interface VX_gpu_inst_req_if();
interface VX_gpgpu_inst_req_if();
wire [`NUM_THREADS-1:0] valid;
wire [`NW_BITS-1:0] warp_num;

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@@ -1,6 +1,6 @@
`ifndef VX_gpr_data_INTER
`define VX_gpr_data_INTER
`ifndef VX_GPR_DATA_IF
`define VX_GPR_DATA_IF
`include "VX_define.vh"

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@@ -1,5 +1,5 @@
`ifndef VX_GPR_JAL_INTER
`define VX_GPR_JAL_INTER
`ifndef VX_GPR_JAL_IF
`define VX_GPR_JAL_IF
`include "VX_define.vh"

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@@ -1,5 +1,5 @@
`ifndef VX_GPR_READ
`define VX_GPR_READ
`ifndef VX_GPR_READ_IF
`define VX_GPR_READ_IF
`include "VX_define.vh"

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@@ -1,13 +0,0 @@
`ifndef VX_GPU_SNP_REQ
`define VX_GPU_SNP_REQ
`include "../cache/VX_cache_config.vh"
interface VX_gpu_dcache_snp_req_if ();
// Snoop Req
wire snp_req_valid;
wire [31:0] snp_req_addr;
endinterface
`endif

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@@ -1,15 +0,0 @@
`ifndef VX_ICACHE_RSP
`define VX_ICACHE_RSP
`include "VX_define.vh"
interface VX_icache_rsp_if ();
// wire ready;
// wire stall;
wire [31:0] instruction;
wire delay;
endinterface
`endif

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@@ -1,6 +1,6 @@
`ifndef VX_EXEC_UNIT_WB_INST_INTER
`define VX_EXEC_UNIT_WB_INST_INTER
`ifndef VX_INST_EXEC_WB_IF
`define VX_INST_EXEC_WB_IF
`include "VX_define.vh"

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@@ -1,6 +1,6 @@
`ifndef VX_MEM_WB_INST_INTER
`define VX_MEM_WB_INST_INTER
`ifndef VX_INST_MEM_WB_IF
`define VX_INST_MEM_WB_IF
`include "VX_define.vh"

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@@ -1,5 +1,5 @@
`ifndef VX_F_D_INTER
`define VX_F_D_INTER
`ifndef VX_INST_META_IF
`define VX_INST_META_IF
`include "VX_define.vh"

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@@ -1,6 +1,6 @@
`ifndef VX_JAL_RSP
`define VX_JAL_RSP
`ifndef VX_JAL_RSP_IF
`define VX_JAL_RSP_IF
`include "VX_define.vh"

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@@ -1,6 +1,6 @@
`ifndef VX_JOIN_INTER
`define VX_JOIN_INTER
`ifndef VX_JOIN_IF
`define VX_JOIN_IF
`include "VX_define.vh"

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@@ -1,6 +1,6 @@
`ifndef VX_LSU_REQ_INTER
`define VX_LSU_REQ_INTER
`ifndef VX_LSU_REQ_IF
`define VX_LSU_REQ_IF
`include "VX_define.vh"

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@@ -1,19 +0,0 @@
`ifndef VX_MW_WB_INTER
`define VX_MW_WB_INTER
`include "VX_define.vh"
interface VX_mw_wb_if ();
wire [`NUM_THREADS-1:0][31:0] alu_result;
wire [`NUM_THREADS-1:0][31:0] mem_result;
wire [4:0] rd;
wire [1:0] wb;
wire [31:0] PC_next;
wire [`NUM_THREADS-1:0] valid;
wire [`NW_BITS-1:0] warp_num;
endinterface
`endif

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@@ -1,6 +1,6 @@
`ifndef VX_WARP_CTL_INTER
`define VX_WARP_CTL_INTER
`ifndef VX_WARP_CTL_IF
`define VX_WARP_CTL_IF
`include "VX_define.vh"

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@@ -1,5 +1,5 @@
`ifndef VX_WB_INTER
`define VX_WB_INTER
`ifndef VX_WB_IF
`define VX_WB_IF
`include "VX_define.vh"

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@@ -1,5 +1,5 @@
`ifndef VX_WSTALL_INTER
`define VX_WSTALL_INTER
`ifndef VX_WSTALL_IF
`define VX_WSTALL_IF
`include "VX_define.vh"