diff --git a/hw/rtl/VX_cluster.v b/hw/rtl/VX_cluster.v index 56c70793..2414828e 100644 --- a/hw/rtl/VX_cluster.v +++ b/hw/rtl/VX_cluster.v @@ -143,6 +143,8 @@ module VX_cluster #( end else begin + `RESET_RELAY (mem_arb_reset); + VX_mem_arb #( .NUM_REQS (`NUM_CORES), .DATA_WIDTH (`L2MEM_DATA_WIDTH), @@ -153,7 +155,7 @@ module VX_cluster #( .BUFFERED_RSP (1) ) mem_arb ( .clk (clk), - .reset (reset), + .reset (mem_arb_reset), // Core request .req_valid_in (per_core_mem_req_valid), diff --git a/hw/rtl/VX_issue.v b/hw/rtl/VX_issue.v index 5dc41aea..8b00ddd9 100644 --- a/hw/rtl/VX_issue.v +++ b/hw/rtl/VX_issue.v @@ -30,11 +30,15 @@ module VX_issue #( wire scoreboard_delay; + `RESET_RELAY (ibuf_reset); + `RESET_RELAY (gpr_reset); + `RESET_RELAY (demux_reset); + VX_ibuffer #( .CORE_ID(CORE_ID) ) ibuffer ( .clk (clk), - .reset (reset), + .reset (ibuf_reset), .decode_if (decode_if), .ibuffer_if (ibuffer_if) ); @@ -58,7 +62,7 @@ module VX_issue #( .CORE_ID(CORE_ID) ) gpr_stage ( .clk (clk), - .reset (reset), + .reset (gpr_reset), .writeback_if (writeback_if), .gpr_req_if (gpr_req_if), .gpr_rsp_if (gpr_rsp_if) @@ -80,7 +84,7 @@ module VX_issue #( VX_instr_demux instr_demux ( .clk (clk), - .reset (reset), + .reset (demux_reset), .ibuffer_if (execute_if), .gpr_rsp_if (gpr_rsp_if), .alu_req_if (alu_req_if), diff --git a/hw/rtl/VX_mem_unit.v b/hw/rtl/VX_mem_unit.v index c68e051a..12623e3d 100644 --- a/hw/rtl/VX_mem_unit.v +++ b/hw/rtl/VX_mem_unit.v @@ -65,6 +65,7 @@ module VX_mem_unit # ( `RESET_RELAY (icache_reset); `RESET_RELAY (dcache_reset); + `RESET_RELAY (mem_arb_reset); VX_cache #( .CACHE_ID (`ICACHE_ID), @@ -197,6 +198,9 @@ module VX_mem_unit # ( .TAG_WIDTH (`DCORE_TAG_WIDTH-`SM_ENABLE) ) smem_rsp_if(); + `RESET_RELAY (smem_arb_reset); + `RESET_RELAY (smem_reset); + VX_smem_arb #( .NUM_REQS (2), .LANES (`NUM_THREADS), @@ -207,7 +211,7 @@ module VX_mem_unit # ( .BUFFERED_RSP (1) ) smem_arb ( .clk (clk), - .reset (reset), + .reset (smem_arb_reset), // input request .req_valid_in (dcache_req_if.valid), @@ -242,8 +246,6 @@ module VX_mem_unit # ( .rsp_ready_out (dcache_rsp_if.ready) ); - `RESET_RELAY (smem_reset); - VX_shared_mem #( .CACHE_ID (`SCACHE_ID), .CACHE_SIZE (`SMEM_SIZE), @@ -312,7 +314,7 @@ module VX_mem_unit # ( .BUFFERED_RSP (2) ) mem_arb ( .clk (clk), - .reset (reset), + .reset (mem_arb_reset), // Source request .req_valid_in ({dcache_mem_req_if.valid, icache_mem_req_if.valid}), diff --git a/hw/rtl/VX_platform.vh b/hw/rtl/VX_platform.vh index 76b57c6b..14f26054 100644 --- a/hw/rtl/VX_platform.vh +++ b/hw/rtl/VX_platform.vh @@ -74,6 +74,7 @@ `define USE_FAST_BRAM (* ramstyle = "MLAB, no_rw_check" *) `define NO_RW_RAM_CHECK (* altera_attribute = "-name add_pass_through_logic_to_inferred_rams off" *) `define DISABLE_BRAM (* ramstyle = "logic" *) +`define PRESERVE_REG (* preserve *) /////////////////////////////////////////////////////////////////////////////// diff --git a/hw/rtl/VX_warp_sched.v b/hw/rtl/VX_warp_sched.v index 26529498..89673310 100644 --- a/hw/rtl/VX_warp_sched.v +++ b/hw/rtl/VX_warp_sched.v @@ -202,7 +202,7 @@ module VX_warp_sched #( VX_priority_encoder #( .N (`NUM_WARPS) - ) rr_arbiter ( + ) pri_enc ( .data_in (ready_warps), .index (schedule_wid), .valid_out (schedule_valid), diff --git a/hw/rtl/Vortex.v b/hw/rtl/Vortex.v index d92c6cfd..4d871e0e 100644 --- a/hw/rtl/Vortex.v +++ b/hw/rtl/Vortex.v @@ -141,6 +141,8 @@ module Vortex ( end else begin + `RESET_RELAY (mem_arb_reset); + VX_mem_arb #( .NUM_REQS (`NUM_CLUSTERS), .DATA_WIDTH (`L3MEM_DATA_WIDTH), @@ -150,7 +152,7 @@ module Vortex ( .BUFFERED_RSP (1) ) mem_arb ( .clk (clk), - .reset (reset), + .reset (mem_arb_reset), // Core request .req_valid_in (per_cluster_mem_req_valid), diff --git a/hw/rtl/afu/vortex_afu.sv b/hw/rtl/afu/vortex_afu.sv index bfa276af..70208392 100644 --- a/hw/rtl/afu/vortex_afu.sv +++ b/hw/rtl/afu/vortex_afu.sv @@ -512,6 +512,8 @@ t_local_mem_data mem_rsp_data; wire [AVS_REQ_TAGW:0] mem_rsp_tag; wire mem_rsp_ready; +`RESET_RELAY (mem_arb_reset); + VX_mem_arb #( .NUM_REQS (2), .DATA_WIDTH (LMEM_DATA_WIDTH), @@ -522,7 +524,7 @@ VX_mem_arb #( .TYPE ("X") ) mem_arb ( .clk (clk), - .reset (reset), + .reset (mem_arb_reset), // Source request .req_valid_in ({vx_mem_req_arb_valid, cci_mem_req_arb_valid}), @@ -557,6 +559,8 @@ VX_mem_arb #( //-- +`RESET_RELAY (avs_wrapper_reset); + VX_avs_wrapper #( .AVS_DATA_WIDTH (LMEM_DATA_WIDTH), .AVS_ADDR_WIDTH (LMEM_ADDR_WIDTH), @@ -566,7 +570,7 @@ VX_avs_wrapper #( .RD_QUEUE_SIZE (AVS_RD_QUEUE_SIZE) ) avs_wrapper ( .clk (clk), - .reset (reset), + .reset (avs_wrapper_reset), // Memory request .mem_req_valid (mem_req_valid), @@ -724,13 +728,15 @@ always @(posedge clk) begin end end +`RESET_RELAY (cci_rdq_reset); + VX_fifo_queue #( .DATAW (CCI_RD_QUEUE_DATAW), .SIZE (CCI_RD_QUEUE_SIZE), .OUTPUT_REG (1) ) cci_rd_req_queue ( .clk (clk), - .reset (reset), + .reset (cci_rdq_reset), .push (cci_rdq_push), .pop (cci_rdq_pop), .data_in (cci_rdq_din), @@ -878,7 +884,7 @@ Vortex #() vortex ( `SCOPE_BIND_afu_vortex .clk (clk), - .reset (reset | vx_reset), + .reset (reset || vx_reset), // Memory request .mem_req_valid (vx_mem_req_valid), @@ -997,6 +1003,8 @@ VX_fifo_queue #( wire scope_changed = `SCOPE_TRIGGER; +`RESET_RELAY (scope_reset); + VX_scope #( .DATAW ($bits({`SCOPE_DATA_LIST,`SCOPE_UPDATE_LIST})), .BUSW (64), @@ -1004,7 +1012,7 @@ VX_scope #( .UPDW ($bits({`SCOPE_UPDATE_LIST})) ) scope ( .clk (clk), - .reset (reset), + .reset (scope_reset), .start (1'b0), .stop (1'b0), .changed (scope_changed), diff --git a/hw/rtl/cache/VX_cache.v b/hw/rtl/cache/VX_cache.v index bbe1e10a..eab2004e 100644 --- a/hw/rtl/cache/VX_cache.v +++ b/hw/rtl/cache/VX_cache.v @@ -134,7 +134,7 @@ module VX_cache #( wire mem_rsp_valid_nc; wire [`CACHE_LINE_WIDTH-1:0] mem_rsp_data_nc; wire [MEM_TAG_IN_WIDTH-1:0] mem_rsp_tag_nc; - wire mem_rsp_ready_nc; + wire mem_rsp_ready_nc; if (NC_ENABLE) begin VX_nc_bypass #( @@ -151,8 +151,8 @@ module VX_cache #( .MEM_TAG_IN_WIDTH (MEM_TAG_IN_WIDTH), .MEM_TAG_OUT_WIDTH (MEM_TAG_WIDTH) ) nc_bypass ( - .clk (clk), - .reset (reset), + .clk (clk), + .reset (reset), // Core request in .core_req_valid_in (core_req_valid), @@ -251,6 +251,8 @@ module VX_cache #( wire [MEM_TAG_IN_WIDTH-1:0] mem_rsp_tag_qual; wire mrsq_out_valid, mrsq_out_ready; + + `RESET_RELAY (mrsq_reset); VX_elastic_buffer #( .DATAW (MEM_TAG_IN_WIDTH + `CACHE_LINE_WIDTH), @@ -258,7 +260,7 @@ module VX_cache #( .OUTPUT_REG (MRSQ_SIZE > 2) ) mem_rsp_queue ( .clk (clk), - .reset (reset), + .reset (mrsq_reset), .ready_in (mem_rsp_ready_nc), .valid_in (mem_rsp_valid_nc), .data_in ({mem_rsp_tag_nc, mem_rsp_data_nc}), @@ -274,13 +276,15 @@ module VX_cache #( wire [`LINE_SELECT_BITS-1:0] flush_addr; wire flush_enable; + `RESET_RELAY (flush_reset); + VX_flush_ctrl #( .CACHE_SIZE (CACHE_SIZE), .CACHE_LINE_SIZE (CACHE_LINE_SIZE), .NUM_BANKS (NUM_BANKS) ) flush_ctrl ( .clk (clk), - .reset (reset), + .reset (flush_reset), .addr_out (flush_addr), .valid_out (flush_enable) ); @@ -435,6 +439,8 @@ module VX_cache #( assign curr_bank_mem_rsp_id = `MEM_TAG_TO_REQ_ID(mem_rsp_tag_qual); assign curr_bank_mem_rsp_data = mem_rsp_data_qual; assign per_bank_mem_rsp_ready[i] = curr_bank_mem_rsp_ready; + + `RESET_RELAY (bank_reset); VX_bank #( .BANK_ID (i), @@ -457,7 +463,7 @@ module VX_cache #( `SCOPE_BIND_VX_cache_bank(i) .clk (clk), - .reset (reset), + .reset (bank_reset), `ifdef PERF_ENABLE .perf_read_misses (perf_read_miss_per_bank[i]), @@ -539,13 +545,15 @@ module VX_cache #( wire [MSHR_ADDR_WIDTH-1:0] mem_req_id; + `RESET_RELAY (mreq_reset); + VX_stream_arbiter #( .NUM_REQS (NUM_BANKS), .DATAW (`MEM_ADDR_WIDTH + MSHR_ADDR_WIDTH + 1 + CACHE_LINE_SIZE + `CACHE_LINE_WIDTH), .BUFFERED (1) ) mem_req_arb ( .clk (clk), - .reset (reset), + .reset (mreq_reset), .valid_in (per_bank_mem_req_valid), .data_in (data_in), .ready_in (per_bank_mem_req_ready), diff --git a/hw/rtl/libs/VX_onehot_encoder.v b/hw/rtl/libs/VX_onehot_encoder.v index e1362078..8b85acb6 100644 --- a/hw/rtl/libs/VX_onehot_encoder.v +++ b/hw/rtl/libs/VX_onehot_encoder.v @@ -1,7 +1,7 @@ `include "VX_platform.vh" // Fast encoder using parallel prefix computation -// Adapter from BaseJump STL: http://bjump.org/data_out.html +// Adapted from BaseJump STL: http://bjump.org/data_out.html `TRACING_OFF module VX_onehot_encoder #( diff --git a/hw/rtl/libs/VX_reset_relay.v b/hw/rtl/libs/VX_reset_relay.v index facca82b..94b24250 100644 --- a/hw/rtl/libs/VX_reset_relay.v +++ b/hw/rtl/libs/VX_reset_relay.v @@ -1,26 +1,31 @@ `include "VX_platform.vh" -`TRACING_OFF module VX_reset_relay #( - parameter ASYNC = 0 + parameter N = 1, + parameter DEPTH = 1 ) ( input wire clk, input wire reset, - output wire reset_o + output wire [N-1:0] reset_o ); - (* preserve *) reg reset_r; - if (ASYNC) begin - always @(posedge clk or posedge reset) begin - reset_r <= reset; - end - end else begin + if (DEPTH > 1) begin + `PRESERVE_REG `DISABLE_BRAM reg [N-1:0] reset_r [DEPTH-1:0]; always @(posedge clk) begin - reset_r <= reset; + for (integer i = DEPTH-1; i > 0; --i) + reset_r[i] <= reset_r[i-1]; + reset_r[0] <= {N{reset}}; + end + assign reset_o = reset_r[DEPTH-1]; + end else if (DEPTH == 1) begin + `PRESERVE_REG reg [N-1:0] reset_r; + always @(posedge clk) begin + reset_r <= {N{reset}}; end + assign reset_o = reset_r; + end else begin + `UNUSED_VAR (clk) + assign reset_o = {N{reset}}; end - - assign reset_o = reset_r; -endmodule -`TRACING_ON \ No newline at end of file +endmodule \ No newline at end of file diff --git a/hw/syn/opae/vortex_afu.qsf b/hw/syn/opae/vortex_afu.qsf index 0c7e4cbd..1628f9d8 100644 --- a/hw/syn/opae/vortex_afu.qsf +++ b/hw/syn/opae/vortex_afu.qsf @@ -23,12 +23,12 @@ set_global_assignment -name ROUTER_LCELL_INSERTION_AND_LOGIC_DUPLICATION ON set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS ON set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON -set_global_assignment -name USE_HIGH_SPEED_ADDER ON -set_global_assignment -name MUX_RESTRUCTURE ON -set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP ON -set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING "FORCE ALL TILES WITH FAILING TIMING PATHS TO HIGH SPEED" -set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON -set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING ON +#set_global_assignment -name USE_HIGH_SPEED_ADDER ON +#set_global_assignment -name MUX_RESTRUCTURE ON +#set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP ON +#set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING "FORCE ALL TILES WITH FAILING TIMING PATHS TO HIGH SPEED" +#set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON +#set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING ON set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 set_global_assignment -name MAX_CORE_JUNCTION_TEMP 100