simx directory name fix
This commit is contained in:
Blaise Tine
648
sim/simx/core.cpp
Normal file
648
sim/simx/core.cpp
Normal file
@@ -0,0 +1,648 @@
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#include <iostream>
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#include <iomanip>
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#include <string.h>
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#include <assert.h>
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#include <util.h>
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#include "types.h"
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#include "archdef.h"
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#include "mem.h"
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#include "decode.h"
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#include "core.h"
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#include "debug.h"
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#include "constants.h"
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using namespace vortex;
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Core::Core(const SimContext& ctx, const ArchDef &arch, Word id)
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: SimObject(ctx, "Core")
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, MemRspPort(this)
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, MemReqPort(this)
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, id_(id)
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, arch_(arch)
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, decoder_(arch)
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, mmu_(0, arch.wsize(), true)
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, tex_units_(NUM_TEX_UNITS, this)
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, warps_(arch.num_warps())
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, barriers_(arch.num_barriers(), 0)
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, csrs_(arch.num_csrs(), 0)
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, fcsrs_(arch.num_warps(), 0)
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, ibuffers_(arch.num_warps(), IBUF_SIZE)
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, scoreboard_(arch_)
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, exe_units_((int)ExeType::MAX)
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, icache_(Cache::Create("Icache", Cache::Config{
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log2ceil(ICACHE_SIZE), // C
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log2ceil(L1_BLOCK_SIZE),// B
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2, // W
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0, // A
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32, // address bits
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1, // number of banks
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1, // number of ports
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1, // request size
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true, // write-through
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false, // write response
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0, // victim size
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NUM_WARPS, // mshr
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2, // pipeline latency
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}))
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, dcache_(Cache::Create("Dcache", Cache::Config{
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log2ceil(DCACHE_SIZE), // C
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log2ceil(L1_BLOCK_SIZE),// B
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2, // W
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0, // A
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32, // address bits
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DCACHE_NUM_BANKS, // number of banks
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DCACHE_NUM_PORTS, // number of ports
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(uint8_t)arch.num_threads(), // request size
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true, // write-through
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false, // write response
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0, // victim size
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DCACHE_MSHR_SIZE, // mshr
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4, // pipeline latency
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}))
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, shared_mem_(SharedMem::Create("sharedmem", SharedMem::Config{
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arch.num_threads(),
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arch.num_threads(),
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Constants::SMEM_BANK_OFFSET,
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1,
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false
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}))
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, l1_mem_switch_(Switch<MemReq, MemRsp>::Create("l1_arb", ArbiterType::Priority, 2))
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, dcache_switch_(arch.num_threads())
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, fetch_latch_("fetch")
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, decode_latch_("decode")
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, pending_icache_(arch_.num_warps())
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, active_warps_(1)
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, stalled_warps_(0)
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, last_schedule_wid_(0)
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, issued_instrs_(0)
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, committed_instrs_(0)
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, csr_tex_unit_(0)
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, ecall_(false)
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, ebreak_(false)
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, perf_mem_pending_reads_(0)
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{
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for (int i = 0; i < arch_.num_warps(); ++i) {
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warps_.at(i) = std::make_shared<Warp>(this, i);
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}
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// register execute units
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exe_units_.at((int)ExeType::NOP) = SimPlatform::instance().CreateObject<NopUnit>(this);
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exe_units_.at((int)ExeType::ALU) = SimPlatform::instance().CreateObject<AluUnit>(this);
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exe_units_.at((int)ExeType::LSU) = SimPlatform::instance().CreateObject<LsuUnit>(this);
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exe_units_.at((int)ExeType::CSR) = SimPlatform::instance().CreateObject<CsrUnit>(this);
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exe_units_.at((int)ExeType::FPU) = SimPlatform::instance().CreateObject<FpuUnit>(this);
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exe_units_.at((int)ExeType::GPU) = SimPlatform::instance().CreateObject<GpuUnit>(this);
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// connect l1 switch
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icache_->MemReqPort.bind(&l1_mem_switch_->ReqIn[0]);
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dcache_->MemReqPort.bind(&l1_mem_switch_->ReqIn[1]);
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l1_mem_switch_->RspOut[0].bind(&icache_->MemRspPort);
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l1_mem_switch_->RspOut[1].bind(&dcache_->MemRspPort);
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this->MemRspPort.bind(&l1_mem_switch_->RspIn);
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l1_mem_switch_->ReqOut.bind(&this->MemReqPort);
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// lsu/tex switch
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for (uint32_t i = 0, n = arch.num_threads(); i < n; ++i) {
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auto& sw = dcache_switch_.at(i);
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#ifdef EXT_TEX_ENABLE
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sw = Switch<MemReq, MemRsp>::Create("lsu_arb", ArbiterType::Priority, 2);
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#else
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sw = Switch<MemReq, MemRsp>::Create("lsu_arb", ArbiterType::Priority, 1);
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#endif
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sw->ReqOut.bind(&dcache_->CoreReqPorts.at(i));
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dcache_->CoreRspPorts.at(i).bind(&sw->RspIn);
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}
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// activate warp0
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warps_.at(0)->setTmask(0, true);
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// memory perf callbacks
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MemReqPort.tx_callback([&](const MemReq& req, uint64_t cycle){
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__unused (cycle);
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perf_stats_.mem_reads += !req.write;
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perf_stats_.mem_writes += req.write;
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perf_mem_pending_reads_ += !req.write;
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});
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MemRspPort.tx_callback([&](const MemRsp&, uint64_t cycle){
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__unused (cycle);
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--perf_mem_pending_reads_;
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});
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}
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Core::~Core() {
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for (auto& buf : print_bufs_) {
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auto str = buf.second.str();
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if (!str.empty()) {
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std::cout << "#" << buf.first << ": " << str << std::endl;
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}
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}
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}
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void Core::attach_ram(RAM* ram) {
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// bind RAM to memory unit
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mmu_.attach(*ram, 0, 0xFFFFFFFF);
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}
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void Core::step(uint64_t cycle) {
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this->commit(cycle);
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this->execute(cycle);
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this->decode(cycle);
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this->fetch(cycle);
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this->schedule(cycle);
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// update perf counter
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perf_stats_.mem_latency += perf_mem_pending_reads_;
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DPN(2, std::flush);
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}
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void Core::schedule(uint64_t cycle) {
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__unused (cycle);
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bool foundSchedule = false;
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int scheduled_warp = last_schedule_wid_;
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// round robin scheduling
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for (size_t wid = 0, nw = arch_.num_warps(); wid < nw; ++wid) {
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scheduled_warp = (scheduled_warp + 1) % nw;
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bool warp_active = active_warps_.test(scheduled_warp);
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bool warp_stalled = stalled_warps_.test(scheduled_warp);
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if (warp_active && !warp_stalled) {
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last_schedule_wid_ = scheduled_warp;
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foundSchedule = true;
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break;
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}
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}
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if (!foundSchedule)
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return;
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// suspend warp until decode
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stalled_warps_.set(scheduled_warp);
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auto& warp = warps_.at(scheduled_warp);
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uint64_t uuid = (issued_instrs_++ * arch_.num_cores()) + id_;
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auto trace = new pipeline_trace_t(uuid, arch_);
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warp->eval(trace);
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DT(3, cycle, "pipeline-schedule: " << *trace);
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// advance to fetch stage
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fetch_latch_.push(trace);
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}
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void Core::fetch(uint64_t cycle) {
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__unused (cycle);
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// handle icache reponse
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auto& icache_rsp_port = icache_->CoreRspPorts.at(0);
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if (!icache_rsp_port.empty()){
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auto& mem_rsp = icache_rsp_port.front();
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auto trace = pending_icache_.at(mem_rsp.tag);
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decode_latch_.push(trace);
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DT(3, cycle, "icache-rsp: addr=" << std::hex << trace->PC << ", tag=" << mem_rsp.tag << ", " << *trace);
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pending_icache_.release(mem_rsp.tag);
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icache_rsp_port.pop();
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}
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// send icache request
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if (!fetch_latch_.empty()) {
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auto trace = fetch_latch_.front();
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MemReq mem_req;
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mem_req.addr = trace->PC;
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mem_req.write = false;
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mem_req.tag = pending_icache_.allocate(trace);
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icache_->CoreReqPorts.at(0).send(mem_req, 1);
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DT(3, cycle, "icache-req: addr=" << std::hex << mem_req.addr << ", tag=" << mem_req.tag << ", " << *trace);
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fetch_latch_.pop();
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}
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}
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void Core::decode(uint64_t cycle) {
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__unused (cycle);
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if (decode_latch_.empty())
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return;
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auto trace = decode_latch_.front();
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// check ibuffer capacity
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auto& ibuffer = ibuffers_.at(trace->wid);
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if (ibuffer.full()) {
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if (!trace->suspend()) {
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DT(3, cycle, "*** ibuffer-stall: " << *trace);
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}
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++perf_stats_.ibuf_stalls;
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return;
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} else {
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trace->resume();
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}
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// release warp
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if (!trace->fetch_stall) {
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stalled_warps_.reset(trace->wid);
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}
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// update perf counters
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uint32_t active_threads = trace->tmask.count();
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if (trace->exe_type == ExeType::LSU && trace->lsu.type == LsuType::LOAD)
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perf_stats_.loads += active_threads;
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if (trace->exe_type == ExeType::LSU && trace->lsu.type == LsuType::STORE)
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perf_stats_.stores += active_threads;
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if (trace->exe_type == ExeType::ALU && trace->alu.type == AluType::BRANCH)
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perf_stats_.branches += active_threads;
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DT(3, cycle, "pipeline-decode: " << *trace);
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// insert to ibuffer
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ibuffer.push(trace);
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decode_latch_.pop();
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}
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void Core::execute(uint64_t cycle) {
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__unused (cycle);
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// issue ibuffer instructions
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for (auto& ibuffer : ibuffers_) {
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if (ibuffer.empty())
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continue;
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auto trace = ibuffer.top();
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// check scoreboard
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if (scoreboard_.in_use(trace)) {
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if (!trace->suspend()) {
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DTH(3, cycle, "*** scoreboard-stall: dependents={");
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auto uses = scoreboard_.get_uses(trace);
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for (uint32_t i = 0, n = uses.size(); i < n; ++i) {
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auto& use = uses.at(i);
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__unused (use);
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if (i) DTN(3, ", ");
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DTN(3, use.type << use.reg << "(#" << use.owner << ")");
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}
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DTN(3, "}, " << *trace << std::endl);
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}
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++perf_stats_.scrb_stalls;
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continue;
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} else {
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trace->resume();
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}
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// update scoreboard
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scoreboard_.reserve(trace);
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DT(3, cycle, "pipeline-issue: " << *trace);
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// push to execute units
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auto& exe_unit = exe_units_.at((int)trace->exe_type);
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exe_unit->Input.send(trace, 1);
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ibuffer.pop();
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break;
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}
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}
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void Core::commit(uint64_t cycle) {
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__unused (cycle);
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// commit completed instructions
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bool wb = false;
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for (auto& exe_unit : exe_units_) {
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if (!exe_unit->Output.empty()) {
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auto trace = exe_unit->Output.front();
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// allow only one commit that updates registers
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if (trace->wb && wb)
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continue;
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wb |= trace->wb;
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// advance to commit stage
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DT(3, cycle, "pipeline-commit: " << *trace);
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// update scoreboard
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scoreboard_.release(trace);
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assert(committed_instrs_ <= issued_instrs_);
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++committed_instrs_;
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perf_stats_.instrs += trace->tmask.count();
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// delete the trace
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delete trace;
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exe_unit->Output.pop();
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}
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}
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}
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WarpMask Core::wspawn(int num_warps, int nextPC) {
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WarpMask ret(1);
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int active_warps = std::min<int>(num_warps, arch_.num_warps());
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DP(3, "*** Activate " << (active_warps-1) << " warps at PC: " << std::hex << nextPC);
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for (int i = 1; i < active_warps; ++i) {
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auto warp = warps_.at(i);
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warp->setPC(nextPC);
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warp->setTmask(0, true);
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ret.set(i);
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}
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return std::move(ret);
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}
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WarpMask Core::barrier(int bar_id, int count, int warp_id) {
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WarpMask ret(0);
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auto& barrier = barriers_.at(bar_id);
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barrier.set(warp_id);
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if (barrier.count() < (size_t)count) {
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warps_.at(warp_id)->suspend();
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DP(3, "*** Suspend warp #" << warp_id << " at barrier #" << bar_id);
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return std::move(ret);
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}
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for (int i = 0; i < arch_.num_warps(); ++i) {
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if (barrier.test(i)) {
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DP(3, "*** Resume warp #" << i << " at barrier #" << bar_id);
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warps_.at(i)->activate();
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ret.set(i);
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}
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}
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barrier.reset();
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return std::move(ret);
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}
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Word Core::icache_read(Addr addr, Size size) {
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Word data;
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mmu_.read(&data, addr, size, 0);
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return data;
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}
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Word Core::dcache_read(Addr addr, Size size) {
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Word data;
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mmu_.read(&data, addr, size, 0);
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return data;
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}
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void Core::dcache_write(Addr addr, Word data, Size size) {
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if (addr >= IO_COUT_ADDR
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&& addr <= (IO_COUT_ADDR + IO_COUT_SIZE - 1)) {
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this->writeToStdOut(addr, data);
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} else {
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mmu_.write(&data, addr, size, 0);
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}
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}
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Word Core::tex_read(uint32_t unit, Word u, Word v, Word lod, std::vector<mem_addr_size_t>* mem_addrs) {
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return tex_units_.at(unit).read(u, v, lod, mem_addrs);
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}
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void Core::writeToStdOut(Addr addr, Word data) {
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uint32_t tid = (addr - IO_COUT_ADDR) & (IO_COUT_SIZE-1);
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auto& ss_buf = print_bufs_[tid];
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char c = (char)data;
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ss_buf << c;
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if (c == '\n') {
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std::cout << std::dec << "#" << tid << ": " << ss_buf.str() << std::flush;
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ss_buf.str("");
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}
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}
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Word Core::get_csr(Addr addr, int tid, int wid) {
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switch (addr) {
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case CSR_SATP:
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case CSR_PMPCFG0:
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case CSR_PMPADDR0:
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case CSR_MSTATUS:
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case CSR_MISA:
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case CSR_MEDELEG:
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case CSR_MIDELEG:
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case CSR_MIE:
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case CSR_MTVEC:
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case CSR_MEPC:
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return 0;
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case CSR_FFLAGS:
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return fcsrs_.at(wid) & 0x1F;
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case CSR_FRM:
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return (fcsrs_.at(wid) >> 5);
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case CSR_FCSR:
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return fcsrs_.at(wid);
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case CSR_WTID:
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// Warp threadID
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return tid;
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case CSR_LTID:
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// Core threadID
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return tid + (wid * arch_.num_threads());
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case CSR_GTID:
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// Processor threadID
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return tid + (wid * arch_.num_threads()) +
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(arch_.num_threads() * arch_.num_warps() * id_);
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case CSR_LWID:
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// Core warpID
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return wid;
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case CSR_GWID:
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// Processor warpID
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return wid + (arch_.num_warps() * id_);
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case CSR_GCID:
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// Processor coreID
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return id_;
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case CSR_TMASK:
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// Processor coreID
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return warps_.at(wid)->getTmask();
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case CSR_NT:
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// Number of threads per warp
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return arch_.num_threads();
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case CSR_NW:
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// Number of warps per core
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return arch_.num_warps();
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case CSR_NC:
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// Number of cores
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return arch_.num_cores();
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case CSR_MINSTRET:
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// NumInsts
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return perf_stats_.instrs & 0xffffffff;
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case CSR_MINSTRET_H:
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// NumInsts
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return (Word)(perf_stats_.instrs >> 32);
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case CSR_MCYCLE:
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// NumCycles
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return (Word)SimPlatform::instance().cycles();
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case CSR_MCYCLE_H:
|
||||
// NumCycles
|
||||
return (Word)(SimPlatform::instance().cycles() >> 32);
|
||||
case CSR_MPM_IBUF_ST:
|
||||
return perf_stats_.ibuf_stalls & 0xffffffff;
|
||||
case CSR_MPM_IBUF_ST_H:
|
||||
return perf_stats_.ibuf_stalls >> 32;
|
||||
case CSR_MPM_SCRB_ST:
|
||||
return perf_stats_.scrb_stalls & 0xffffffff;
|
||||
case CSR_MPM_SCRB_ST_H:
|
||||
return perf_stats_.scrb_stalls >> 32;
|
||||
case CSR_MPM_ALU_ST:
|
||||
return perf_stats_.alu_stalls & 0xffffffff;
|
||||
case CSR_MPM_ALU_ST_H:
|
||||
return perf_stats_.alu_stalls >> 32;
|
||||
case CSR_MPM_LSU_ST:
|
||||
return perf_stats_.lsu_stalls & 0xffffffff;
|
||||
case CSR_MPM_LSU_ST_H:
|
||||
return perf_stats_.lsu_stalls >> 32;
|
||||
case CSR_MPM_CSR_ST:
|
||||
return perf_stats_.csr_stalls & 0xffffffff;
|
||||
case CSR_MPM_CSR_ST_H:
|
||||
return perf_stats_.csr_stalls >> 32;
|
||||
case CSR_MPM_FPU_ST:
|
||||
return perf_stats_.fpu_stalls & 0xffffffff;
|
||||
case CSR_MPM_FPU_ST_H:
|
||||
return perf_stats_.fpu_stalls >> 32;
|
||||
case CSR_MPM_GPU_ST:
|
||||
return perf_stats_.gpu_stalls & 0xffffffff;
|
||||
case CSR_MPM_GPU_ST_H:
|
||||
return perf_stats_.gpu_stalls >> 32;
|
||||
|
||||
case CSR_MPM_LOADS:
|
||||
return perf_stats_.loads & 0xffffffff;
|
||||
case CSR_MPM_LOADS_H:
|
||||
return perf_stats_.loads >> 32;
|
||||
case CSR_MPM_STORES:
|
||||
return perf_stats_.stores & 0xffffffff;
|
||||
case CSR_MPM_STORES_H:
|
||||
return perf_stats_.stores >> 32;
|
||||
case CSR_MPM_BRANCHES:
|
||||
return perf_stats_.branches & 0xffffffff;
|
||||
case CSR_MPM_BRANCHES_H:
|
||||
return perf_stats_.branches >> 32;
|
||||
|
||||
case CSR_MPM_ICACHE_READS:
|
||||
return icache_->perf_stats().reads & 0xffffffff;
|
||||
case CSR_MPM_ICACHE_READS_H:
|
||||
return icache_->perf_stats().reads >> 32;
|
||||
case CSR_MPM_ICACHE_MISS_R:
|
||||
return icache_->perf_stats().read_misses & 0xffffffff;
|
||||
case CSR_MPM_ICACHE_MISS_R_H:
|
||||
return icache_->perf_stats().read_misses >> 32;
|
||||
|
||||
case CSR_MPM_DCACHE_READS:
|
||||
return dcache_->perf_stats().reads & 0xffffffff;
|
||||
case CSR_MPM_DCACHE_READS_H:
|
||||
return dcache_->perf_stats().reads >> 32;
|
||||
case CSR_MPM_DCACHE_WRITES:
|
||||
return dcache_->perf_stats().writes & 0xffffffff;
|
||||
case CSR_MPM_DCACHE_WRITES_H:
|
||||
return dcache_->perf_stats().writes >> 32;
|
||||
case CSR_MPM_DCACHE_MISS_R:
|
||||
return dcache_->perf_stats().read_misses & 0xffffffff;
|
||||
case CSR_MPM_DCACHE_MISS_R_H:
|
||||
return dcache_->perf_stats().read_misses >> 32;
|
||||
case CSR_MPM_DCACHE_MISS_W:
|
||||
return dcache_->perf_stats().write_misses & 0xffffffff;
|
||||
case CSR_MPM_DCACHE_MISS_W_H:
|
||||
return dcache_->perf_stats().write_misses >> 32;
|
||||
case CSR_MPM_DCACHE_BANK_ST:
|
||||
return dcache_->perf_stats().bank_stalls & 0xffffffff;
|
||||
case CSR_MPM_DCACHE_BANK_ST_H:
|
||||
return dcache_->perf_stats().bank_stalls >> 32;
|
||||
case CSR_MPM_DCACHE_MSHR_ST:
|
||||
return dcache_->perf_stats().mshr_stalls & 0xffffffff;
|
||||
case CSR_MPM_DCACHE_MSHR_ST_H:
|
||||
return dcache_->perf_stats().mshr_stalls >> 32;
|
||||
|
||||
case CSR_MPM_SMEM_READS:
|
||||
return shared_mem_->perf_stats().reads & 0xffffffff;
|
||||
case CSR_MPM_SMEM_READS_H:
|
||||
return shared_mem_->perf_stats().reads >> 32;
|
||||
case CSR_MPM_SMEM_WRITES:
|
||||
return shared_mem_->perf_stats().writes & 0xffffffff;
|
||||
case CSR_MPM_SMEM_WRITES_H:
|
||||
return shared_mem_->perf_stats().writes >> 32;
|
||||
case CSR_MPM_SMEM_BANK_ST:
|
||||
return shared_mem_->perf_stats().bank_stalls & 0xffffffff;
|
||||
case CSR_MPM_SMEM_BANK_ST_H:
|
||||
return shared_mem_->perf_stats().bank_stalls >> 32;
|
||||
|
||||
case CSR_MPM_MEM_READS:
|
||||
return perf_stats_.mem_reads & 0xffffffff;
|
||||
case CSR_MPM_MEM_READS_H:
|
||||
return perf_stats_.mem_reads >> 32;
|
||||
case CSR_MPM_MEM_WRITES:
|
||||
return perf_stats_.mem_writes & 0xffffffff;
|
||||
case CSR_MPM_MEM_WRITES_H:
|
||||
return perf_stats_.mem_writes >> 32;
|
||||
case CSR_MPM_MEM_LAT:
|
||||
return perf_stats_.mem_latency & 0xffffffff;
|
||||
case CSR_MPM_MEM_LAT_H:
|
||||
return perf_stats_.mem_latency >> 32;
|
||||
|
||||
#ifdef EXT_TEX_ENABLE
|
||||
case CSR_MPM_TEX_READS:
|
||||
return perf_stats_.tex_reads & 0xffffffff;
|
||||
case CSR_MPM_TEX_READS_H:
|
||||
return perf_stats_.tex_reads >> 32;
|
||||
case CSR_MPM_TEX_LAT:
|
||||
return perf_stats_.tex_latency & 0xffffffff;
|
||||
case CSR_MPM_TEX_LAT_H:
|
||||
return perf_stats_.tex_latency >> 32;
|
||||
#endif
|
||||
default:
|
||||
if ((addr >= CSR_MPM_BASE && addr < (CSR_MPM_BASE + 32))
|
||||
|| (addr >= CSR_MPM_BASE_H && addr < (CSR_MPM_BASE_H + 32))) {
|
||||
// user-defined MPM CSRs
|
||||
} else
|
||||
#ifdef EXT_TEX_ENABLE
|
||||
if (addr == CSR_TEX_UNIT) {
|
||||
return csr_tex_unit_;
|
||||
} else
|
||||
if (addr >= CSR_TEX_STATE_BEGIN
|
||||
&& addr < CSR_TEX_STATE_END) {
|
||||
uint32_t state = CSR_TEX_STATE(addr);
|
||||
return tex_units_.at(csr_tex_unit_).get_state(state);
|
||||
} else
|
||||
#endif
|
||||
{
|
||||
std::cout << std::hex << "Error: invalid CSR read addr=0x" << addr << std::endl;
|
||||
std::abort();
|
||||
}
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
void Core::set_csr(Addr addr, Word value, int /*tid*/, int wid) {
|
||||
if (addr == CSR_FFLAGS) {
|
||||
fcsrs_.at(wid) = (fcsrs_.at(wid) & ~0x1F) | (value & 0x1F);
|
||||
} else if (addr == CSR_FRM) {
|
||||
fcsrs_.at(wid) = (fcsrs_.at(wid) & ~0xE0) | (value << 5);
|
||||
} else if (addr == CSR_FCSR) {
|
||||
fcsrs_.at(wid) = value & 0xff;
|
||||
} else
|
||||
#ifdef EXT_TEX_ENABLE
|
||||
if (addr == CSR_TEX_UNIT) {
|
||||
csr_tex_unit_ = value;
|
||||
} else
|
||||
if (addr >= CSR_TEX_STATE_BEGIN
|
||||
&& addr < CSR_TEX_STATE_END) {
|
||||
uint32_t state = CSR_TEX_STATE(addr);
|
||||
tex_units_.at(csr_tex_unit_).set_state(state, value);
|
||||
return;
|
||||
} else
|
||||
#endif
|
||||
{
|
||||
csrs_.at(addr) = value;
|
||||
}
|
||||
}
|
||||
|
||||
void Core::trigger_ecall() {
|
||||
ecall_ = true;
|
||||
}
|
||||
|
||||
void Core::trigger_ebreak() {
|
||||
ebreak_ = true;
|
||||
}
|
||||
|
||||
bool Core::check_exit() const {
|
||||
return ebreak_ || ecall_;
|
||||
}
|
||||
|
||||
bool Core::running() const {
|
||||
bool is_running = (committed_instrs_ != issued_instrs_);
|
||||
return is_running;
|
||||
}
|
||||
Reference in New Issue
Block a user