rtl refactoring

2020-05-05 13:31:50 -04:00
parent b7e892ee16
commit 2ab90e9436
8 changed files with 186 additions and 207 deletions
--- a/hw/rtl/pipe_regs/VX_d_e_reg.v
+++ b/hw/rtl/pipe_regs/VX_d_e_reg.v
@@ -10,7 +10,7 @@ module VX_d_e_reg (
 );

    wire stall = freeze;
-    wire flush = (branch_stall == `STALL);
+    wire flush = (branch_stall != 0);

    VX_generic_register #(
        .N(233 + `NW_BITS-1 + 1 + `NUM_THREADS)