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adding support for non-cacheable memory addressing

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This commit is contained in:
Blaise Tine
2021-06-06 13:35:55 -07:00
parent 84391c1a06
commit 3071fb7a29
23 changed files with 1605 additions and 205 deletions
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8
hw/rtl/VX_cluster.v
View File

@@ -41,6 +41,7 @@ module VX_cluster #(
output wire busy,
output wire ebreak
);
`STATIC_ASSERT((`L2_ENABLE == 0 || `NUM_CORES > 1), ("invalid parameter"))
wire [`NUM_CORES-1:0] per_core_mem_req_valid;
wire [`NUM_CORES-1:0] per_core_mem_req_rw;
@@ -166,7 +167,7 @@ module VX_cluster #(
.CACHE_LINE_SIZE (`L2CACHE_LINE_SIZE),
.NUM_BANKS (`L2NUM_BANKS),
.WORD_SIZE (`L2WORD_SIZE),
.NUM_REQS (`NUM_CORES),
.NUM_REQS (`L2NUM_REQS),
.CREQ_SIZE (`L2CREQ_SIZE),
.MSHR_SIZE (`L2MSHR_SIZE),
.MRSQ_SIZE (`L2MRSQ_SIZE),
@@ -174,15 +175,14 @@ module VX_cluster #(
.WRITE_ENABLE (1),
.CORE_TAG_WIDTH (`XMEM_TAG_WIDTH),
.CORE_TAG_ID_BITS (0),
.MEM_TAG_WIDTH (`L2MEM_TAG_WIDTH)
.MEM_TAG_WIDTH (`L2MEM_TAG_WIDTH),
.NC_ENABLE (1)
) l2cache (
`SCOPE_BIND_VX_cluster_l2cache
.clk (clk),
.reset (reset),
.flush (1'b0),
`ifdef PERF_ENABLE
.perf_cache_if (perf_l2cache_if),
`endif

16
hw/rtl/VX_config.vh
View File

@@ -45,20 +45,20 @@
`define STARTUP_ADDR 32'h80000000
`endif
`ifndef IO_BUS_BASE_ADDR
`define IO_BUS_BASE_ADDR 32'hFF000000
`ifndef IO_BASE_ADDR
`define IO_BASE_ADDR 32'hFF000000
`endif
`ifndef SHARED_MEM_BASE_ADDR
`define SHARED_MEM_BASE_ADDR `IO_BUS_BASE_ADDR
`ifndef IO_ADDR_SIZE
`define IO_ADDR_SIZE (32'hFFFFFFFF - 32'hFF000000 + 1)
`endif
`ifndef SHARED_MEM_BASE_ADDR_ALIGN
`define SHARED_MEM_BASE_ADDR_ALIGN 64
`ifndef IO_ADDR_COUT
`define IO_ADDR_COUT 32'hFFFFFFFC
`endif
`ifndef IO_BUS_ADDR_COUT
`define IO_BUS_ADDR_COUT 32'hFFFFFFFC
`ifndef SMEM_BASE_ADDR
`define SMEM_BASE_ADDR `IO_BASE_ADDR
`endif
`ifndef FRAME_BUFFER_BASE_ADDR

4
hw/rtl/VX_core.v
View File

@@ -71,13 +71,13 @@ module VX_core #(
//--
VX_dcache_core_req_if #(
.NUM_REQS(`DNUM_REQUESTS),
.NUM_REQS(`DNUM_REQS),
.WORD_SIZE(`DWORD_SIZE),
.CORE_TAG_WIDTH(`DCORE_TAG_WIDTH)
) dcache_core_req_if();
VX_dcache_core_rsp_if #(
.NUM_REQS(`DNUM_REQUESTS),
.NUM_REQS(`DNUM_REQS),
.WORD_SIZE(`DWORD_SIZE),
.CORE_TAG_WIDTH(`DCORE_TAG_WIDTH)
) dcache_core_rsp_if();

70
hw/rtl/VX_databus_arb.v
View File

@@ -18,40 +18,36 @@ module VX_databus_arb (
// output response
VX_dcache_core_rsp_if core_rsp_if
);
localparam SMEM_ASHIFT = `CLOG2(`SHARED_MEM_BASE_ADDR_ALIGN);
localparam REQ_ASHIFT = `CLOG2(`DWORD_SIZE);
localparam REQ_ADDRW = 32 - REQ_ASHIFT;
localparam REQ_DATAW = 1 + REQ_ADDRW + 1 + `DWORD_SIZE + (`DWORD_SIZE*8) + `DCORE_TAG_WIDTH;
localparam RSP_DATAW = `NUM_THREADS + `NUM_THREADS * (`DWORD_SIZE*8) + `DCORE_TAG_WIDTH;
localparam REQ_ASHIFT = `CLOG2(`DWORD_SIZE);
localparam REQ_ADDRW = 32 - REQ_ASHIFT;
localparam REQ_DATAW = 1 + REQ_ADDRW + 1 + `DWORD_SIZE + (`DWORD_SIZE*8) + `DCORE_TAG_WIDTH;
localparam RSP_DATAW = `NUM_THREADS + `NUM_THREADS * (`DWORD_SIZE*8) + `DCORE_TAG_WIDTH;
//
// handle requests
//
for (genvar i = 0; i < `NUM_THREADS; ++i) begin
wire cache_req_valid_out, cache_req_ready_out;
wire is_smem_addr_in, is_smem_addr_out;
// select shared memory bus
assign is_smem_addr_in = `SM_ENABLE
&& (core_req_if.addr[i][REQ_ADDRW-1:SMEM_ASHIFT-REQ_ASHIFT] >= (32-SMEM_ASHIFT)'((`SHARED_MEM_BASE_ADDR - `SMEM_SIZE) >> SMEM_ASHIFT))
&& (core_req_if.addr[i][REQ_ADDRW-1:SMEM_ASHIFT-REQ_ASHIFT] < (32-SMEM_ASHIFT)'(`SHARED_MEM_BASE_ADDR >> SMEM_ASHIFT));
VX_skid_buffer #(
.DATAW (REQ_DATAW)
) out_buffer (
.clk (clk),
.reset (reset),
.valid_in (core_req_if.valid[i]),
.data_in ({is_smem_addr_in, core_req_if.addr[i], core_req_if.rw[i], core_req_if.byteen[i], core_req_if.data[i], core_req_if.tag[i]}),
.ready_in (core_req_if.ready[i]),
.valid_out (cache_req_valid_out),
.data_out ({is_smem_addr_out, cache_req_if.addr[i], cache_req_if.rw[i], cache_req_if.byteen[i], cache_req_if.data[i], cache_req_if.tag[i]}),
.ready_out (cache_req_ready_out)
);
if (`SM_ENABLE) begin
wire cache_req_valid_out;
wire cache_req_ready_out;
wire is_smem_addr_out;
wire is_smem_addr_in = core_req_if.tag[i][1];
VX_skid_buffer #(
.DATAW (REQ_DATAW)
) out_buffer (
.clk (clk),
.reset (reset),
.valid_in (core_req_if.valid[i]),
.data_in ({is_smem_addr_in, core_req_if.addr[i], core_req_if.rw[i], core_req_if.byteen[i], core_req_if.data[i], core_req_if.tag[i]}),
.ready_in (core_req_if.ready[i]),
.valid_out (cache_req_valid_out),
.data_out ({is_smem_addr_out, cache_req_if.addr[i], cache_req_if.rw[i], cache_req_if.byteen[i], cache_req_if.data[i], cache_req_if.tag[i]}),
.ready_out (cache_req_ready_out)
);
assign cache_req_if.valid[i] = cache_req_valid_out && ~is_smem_addr_out;
assign smem_req_if.valid[i] = cache_req_valid_out && is_smem_addr_out;
assign cache_req_ready_out = is_smem_addr_out ? smem_req_if.ready[i] : cache_req_if.ready[i];
@@ -61,10 +57,22 @@ module VX_databus_arb (
assign smem_req_if.byteen[i] = cache_req_if.byteen[i];
assign smem_req_if.data[i] = cache_req_if.data[i];
assign smem_req_if.tag[i] = cache_req_if.tag[i];
end else begin
`UNUSED_VAR (is_smem_addr_out)
assign cache_req_if.valid[i] = cache_req_valid_out;
assign cache_req_ready_out = cache_req_if.ready[i];
VX_skid_buffer #(
.DATAW (REQ_DATAW)
) out_buffer (
.clk (clk),
.reset (reset),
.valid_in (core_req_if.valid[i]),
.data_in ({core_req_if.addr[i], core_req_if.rw[i], core_req_if.byteen[i], core_req_if.data[i], core_req_if.tag[i]}),
.ready_in (core_req_if.ready[i]),
.valid_out (cache_req_if.valid[i]),
.data_out ({cache_req_if.addr[i], cache_req_if.rw[i], cache_req_if.byteen[i], cache_req_if.data[i], cache_req_if.tag[i]}),
.ready_out (cache_req_if.ready[i])
);
end
end
@@ -90,7 +98,7 @@ module VX_databus_arb (
VX_stream_arbiter #(
.NUM_REQS (2),
.DATAW (RSP_DATAW),
.BUFFERED (0)
.BUFFERED (1)
) rsp_arb (
.clk (clk),
.reset (reset),

62
hw/rtl/VX_define.vh
View File

@@ -237,6 +237,9 @@
`define DBG_CACHE_REQ_MDATAW 0
`endif
// Shared memory and non-cacheable flags
`define SM_NC_BITS 2
////////////////////////// Icache Configurable Knobs //////////////////////////
// Cache ID
@@ -280,10 +283,11 @@
// Word size in bytes
`define DWORD_SIZE 4
// TAG sharing enable
`define DCORE_TAG_ID_BITS `LOG2UP(`LSUQ_SIZE)
// TAG sharing enable
`define LSUQ_ADDR_BITS `LOG2UP(`LSUQ_SIZE)
`define DCORE_TAG_ID_BITS (`LSUQ_ADDR_BITS + `SM_NC_BITS)
// Core request tag bits
// Input request tag bits
`define DCORE_TAG_WIDTH (`DBG_CACHE_REQ_MDATAW + `DCORE_TAG_ID_BITS)
// Memory request data bits
@@ -295,11 +299,13 @@
// Memory byte enable bits
`define DMEM_BYTEEN_WIDTH `DCACHE_LINE_SIZE
// Memory request tag bits
`define DMEM_TAG_WIDTH `DMEM_ADDR_WIDTH
// Input request size
`define DNUM_REQS `NUM_THREADS
// Core request size
`define DNUM_REQUESTS `NUM_THREADS
// Memory request tag bits
`define _DMEM_ADDR_RATIO_W $clog2(`DCACHE_LINE_SIZE / `DWORD_SIZE)
`define _DNC_MEM_TAG_WIDTH ($clog2(`DNUM_REQS) + `_DMEM_ADDR_RATIO_W + `DCORE_TAG_WIDTH)
`define DMEM_TAG_WIDTH `MAX((`DMEM_ADDR_WIDTH + `SM_NC_BITS), `_DNC_MEM_TAG_WIDTH)
////////////////////////// SM Configurable Knobs //////////////////////////////
@@ -312,11 +318,8 @@
// bank address offset
`define SBANK_ADDR_OFFSET `CLOG2(`STACK_SIZE / `SWORD_SIZE)
// Core request size
`define SNUM_REQUESTS `NUM_THREADS
// Core request size
`define SNUM_REQUESTS `NUM_THREADS
// Input request size
`define SNUM_REQS `NUM_THREADS
////////////////////////// L2cache Configurable Knobs /////////////////////////
@@ -324,12 +327,12 @@
`define L2CACHE_ID (32'(`L3_ENABLE) + CLUSTER_ID)
// Block size in bytes
`define L2CACHE_LINE_SIZE `MEM_BLOCK_SIZE
`define L2CACHE_LINE_SIZE `MEM_BLOCK_SIZE
// Word size in bytes
`define L2WORD_SIZE `DCACHE_LINE_SIZE
// Core request tag bits
// Input request tag bits
`define L2CORE_TAG_WIDTH (`DCORE_TAG_WIDTH + `CLOG2(`NUM_CORES))
// Memory request data bits
@@ -341,8 +344,14 @@
// Memory byte enable bits
`define L2MEM_BYTEEN_WIDTH `L2CACHE_LINE_SIZE
// Input request size
`define L2NUM_REQS `NUM_CORES
// Memory request tag bits
`define L2MEM_TAG_WIDTH (`L2_ENABLE ? `L2MEM_ADDR_WIDTH : (`XMEM_TAG_WIDTH+`CLOG2(`NUM_CORES)))
`define _L2MEM_ADDR_RATIO_W $clog2(`L2CACHE_LINE_SIZE / `L2WORD_SIZE)
`define _L2NC_MEM_TAG_WIDTH ($clog2(`L2NUM_REQS) + `_L2MEM_ADDR_RATIO_W + `XMEM_TAG_WIDTH)
`define _L2MEM_TAG_WIDTH `MAX((`L2MEM_ADDR_WIDTH + `SM_NC_BITS), `_L2NC_MEM_TAG_WIDTH)
`define L2MEM_TAG_WIDTH (`L2_ENABLE ? `_L2MEM_TAG_WIDTH : (`XMEM_TAG_WIDTH + `CLOG2(`L2NUM_REQS)))
////////////////////////// L3cache Configurable Knobs /////////////////////////
@@ -350,12 +359,12 @@
`define L3CACHE_ID 0
// Block size in bytes
`define L3CACHE_LINE_SIZE `MEM_BLOCK_SIZE
`define L3CACHE_LINE_SIZE `MEM_BLOCK_SIZE
// Word size in bytes
`define L3WORD_SIZE `L2CACHE_LINE_SIZE
// Core request tag bits
// Input request tag bits
`define L3CORE_TAG_WIDTH (`L2CORE_TAG_WIDTH + `CLOG2(`NUM_CLUSTERS))
// Memory request data bits
@@ -367,21 +376,28 @@
// Memory byte enable bits
`define L3MEM_BYTEEN_WIDTH `L3CACHE_LINE_SIZE
// Input request size
`define L3NUM_REQS `NUM_CLUSTERS
// Memory request tag bits
`define L3MEM_TAG_WIDTH (`L3_ENABLE ? `L3MEM_ADDR_WIDTH : (`L2MEM_TAG_WIDTH+`CLOG2(`NUM_CLUSTERS)))
`define _L3MEM_ADDR_RATIO_W $clog2(`L3CACHE_LINE_SIZE / `L3WORD_SIZE)
`define _L3NC_MEM_TAG_WIDTH ($clog2(`L3NUM_REQS) + `_L3MEM_ADDR_RATIO_W + `L2MEM_TAG_WIDTH)
`define _L3MEM_TAG_WIDTH `MAX((`L3MEM_ADDR_WIDTH + `SM_NC_BITS), `_L3NC_MEM_TAG_WIDTH)
`define L3MEM_TAG_WIDTH (`L3_ENABLE ? `_L3MEM_TAG_WIDTH : (`L2MEM_TAG_WIDTH + `CLOG2(`L3NUM_REQS)))
///////////////////////////////////////////////////////////////////////////////
`define VX_MEM_BYTEEN_WIDTH `L3MEM_BYTEEN_WIDTH
`define VX_MEM_ADDR_WIDTH `L3MEM_ADDR_WIDTH
`define VX_MEM_LINE_WIDTH `L3MEM_LINE_WIDTH
`define VX_MEM_TAG_WIDTH `L3MEM_TAG_WIDTH
`define VX_MEM_BYTEEN_WIDTH `L3MEM_BYTEEN_WIDTH
`define VX_MEM_ADDR_WIDTH `L3MEM_ADDR_WIDTH
`define VX_MEM_LINE_WIDTH `L3MEM_LINE_WIDTH
`define VX_MEM_TAG_WIDTH `L3MEM_TAG_WIDTH
`define VX_CORE_TAG_WIDTH `L3CORE_TAG_WIDTH
`define VX_CSR_ID_WIDTH `LOG2UP(`NUM_CLUSTERS * `NUM_CORES)
`define TO_FULL_ADDR(x) {x, (32-$bits(x))'(0)}
`define XMEM_TAG_WIDTH (`DMEM_TAG_WIDTH+`CLOG2(2))
// Merged D-cache/I-cache memory tag
`define XMEM_TAG_WIDTH (`DMEM_TAG_WIDTH + `CLOG2(2))
`include "VX_types.vh"

81
hw/rtl/VX_lsu_unit.v
View File

@@ -19,8 +19,17 @@ module VX_lsu_unit #(
VX_commit_if ld_commit_if,
VX_commit_if st_commit_if
);
localparam MEM_ASHIFT = `CLOG2(`MEM_BLOCK_SIZE);
localparam MEM_ADDRW = 32 - MEM_ASHIFT;
`UNUSED_PARAM (CORE_ID)
localparam REQ_ASHIFT = `CLOG2(`DWORD_SIZE);
localparam REQ_ADDRW = 32 - REQ_ASHIFT;
localparam ADDR_TYPEW = 1 + `SM_ENABLE;
`STATIC_ASSERT(0 == (`IO_BASE_ADDR % MEM_ASHIFT), ("invalid parameter"))
`STATIC_ASSERT(0 == (`SMEM_BASE_ADDR % MEM_ASHIFT), ("invalid parameter"))
`STATIC_ASSERT(`SMEM_SIZE == `MEM_BLOCK_SIZE * (`SMEM_SIZE / `MEM_BLOCK_SIZE), ("invalid parameter"))
wire req_valid;
wire [`NUM_THREADS-1:0] req_tmask;
@@ -33,29 +42,53 @@ module VX_lsu_unit #(
wire [31:0] req_pc;
wire req_is_dup;
wire [`NUM_THREADS-1:0][31:0] full_address;
wire [`NUM_THREADS-1:0][ADDR_TYPEW-1:0] lsu_addr_type, req_addr_type;
wire [`NUM_THREADS-1:0][31:0] full_addr;
for (genvar i = 0; i < `NUM_THREADS; i++) begin
assign full_address[i] = lsu_req_if.base_addr[i] + lsu_req_if.offset;
assign full_addr[i] = lsu_req_if.base_addr[i] + lsu_req_if.offset;
end
wire [`NUM_THREADS-1:0][REQ_ADDRW-1:0] word_addr;
for (genvar i = 0; i < `NUM_THREADS; i++) begin
assign word_addr[i] = full_addr[i][REQ_ASHIFT +: REQ_ADDRW];
end
wire [`NUM_THREADS-1:0] addr_matches;
for (genvar i = 0; i < `NUM_THREADS; i++) begin
assign addr_matches[i] = (full_address[0][31:2] == full_address[i][31:2]) || ~lsu_req_if.tmask[i];
assign addr_matches[i] = (word_addr[0] == word_addr[i]) || ~lsu_req_if.tmask[i];
end
wire is_dup_load = lsu_req_if.wb && lsu_req_if.tmask[0] && (& addr_matches);
wire [`NUM_THREADS-1:0] is_addr_sm, is_addr_nc;
for (genvar i = 0; i < `NUM_THREADS; i++) begin
// is shared memory address
assign is_addr_sm[i] = (word_addr[i][(MEM_ASHIFT-REQ_ASHIFT) +: MEM_ADDRW] >= MEM_ADDRW'((`SMEM_BASE_ADDR - `SMEM_SIZE) >> MEM_ASHIFT))
& (word_addr[i][(MEM_ASHIFT-REQ_ASHIFT) +: MEM_ADDRW] < MEM_ADDRW'(`SMEM_BASE_ADDR >> MEM_ASHIFT));
// is non-cacheable address
assign is_addr_nc[i] = (word_addr[i][(MEM_ASHIFT-REQ_ASHIFT) +: MEM_ADDRW] >= MEM_ADDRW'(`IO_BASE_ADDR >> MEM_ASHIFT));
if (`SM_ENABLE) begin
assign lsu_addr_type[i] = {is_addr_sm[i], is_addr_nc[i]};
end else begin
assign lsu_addr_type[i] = {1'b0, is_addr_nc[i]};
end
end
wire ready_in;
wire stall_in = ~ready_in && req_valid;
VX_pipe_register #(
.DATAW (1 + 1 + `NW_BITS + `NUM_THREADS + 32 + (`NUM_THREADS * 32) + `LSU_BITS + `NR_BITS + 1 + (`NUM_THREADS * 32)),
.DATAW (1 + 1 + `NW_BITS + `NUM_THREADS + 32 + (`NUM_THREADS * 32) + (`NUM_THREADS * ADDR_TYPEW) + `LSU_BITS + `NR_BITS + 1 + (`NUM_THREADS * 32)),
.RESETW (1)
) req_pipe_reg (
.clk (clk),
.reset (reset),
.enable (!stall_in),
.data_in ({lsu_req_if.valid, is_dup_load, lsu_req_if.wid, lsu_req_if.tmask, lsu_req_if.PC, full_address, lsu_req_if.op_type, lsu_req_if.rd, lsu_req_if.wb, lsu_req_if.store_data}),
.data_out ({req_valid, req_is_dup, req_wid, req_tmask, req_pc, req_addr, req_type, req_rd, req_wb, req_data})
.data_in ({lsu_req_if.valid, is_dup_load, lsu_req_if.wid, lsu_req_if.tmask, lsu_req_if.PC, full_addr, lsu_addr_type, lsu_req_if.op_type, lsu_req_if.rd, lsu_req_if.wb, lsu_req_if.store_data}),
.data_out ({req_valid, req_is_dup, req_wid, req_tmask, req_pc, req_addr, req_addr_type, req_type, req_rd, req_wb, req_data})
);
// Can accept new request?
@@ -77,10 +110,10 @@ module VX_lsu_unit #(
reg [`NUM_THREADS-1:0] req_sent_mask;
wire req_ready_all;
wire [`DCORE_TAG_ID_BITS-1:0] mbuf_waddr, mbuf_raddr;
wire [`LSUQ_ADDR_BITS-1:0] mbuf_waddr, mbuf_raddr;
wire mbuf_full;
wire [`NUM_THREADS-1:0][1:0] req_offset, rsp_offset;
wire [`NUM_THREADS-1:0][REQ_ASHIFT-1:0] req_offset, rsp_offset;
for (genvar i = 0; i < `NUM_THREADS; i++) begin
assign req_offset[i] = req_addr[i][1:0];
end
@@ -95,10 +128,10 @@ module VX_lsu_unit #(
wire mbuf_pop = dcache_rsp_fire && (0 == rsp_rem_mask_n);
assign mbuf_raddr = dcache_rsp_if.tag[`DCORE_TAG_ID_BITS-1:0];
assign mbuf_raddr = dcache_rsp_if.tag[ADDR_TYPEW +: `LSUQ_ADDR_BITS];
VX_index_buffer #(
.DATAW (`NW_BITS + 32 + `NUM_THREADS + `NR_BITS + 1 + `LSU_BITS + (`NUM_THREADS * 2) + 1),
.DATAW (`NW_BITS + 32 + `NUM_THREADS + `NR_BITS + 1 + `LSU_BITS + (`NUM_THREADS * REQ_ASHIFT) + 1),
.SIZE (`LSUQ_SIZE)
) req_metadata (
.clk (clk),
@@ -132,8 +165,8 @@ module VX_lsu_unit #(
wire is_req_start = (0 == req_sent_mask);
// need to hold the acquired tag index until the full request is submitted
reg [`DCORE_TAG_ID_BITS-1:0] req_tag_hold;
wire [`DCORE_TAG_ID_BITS-1:0] req_tag = is_req_start ? mbuf_waddr : req_tag_hold;
reg [`LSUQ_ADDR_BITS-1:0] req_tag_hold;
wire [`LSUQ_ADDR_BITS-1:0] req_tag = is_req_start ? mbuf_waddr : req_tag_hold;
always @(posedge clk) begin
if (mbuf_push) begin
req_tag_hold <= mbuf_waddr;
@@ -193,11 +226,13 @@ module VX_lsu_unit #(
assign dcache_req_if.byteen = mem_req_byteen;
assign dcache_req_if.data = mem_req_data;
`ifdef DBG_CACHE_REQ_INFO
assign dcache_req_if.tag = {`NUM_THREADS{req_pc, req_wid, req_tag}};
`else
assign dcache_req_if.tag = {`NUM_THREADS{req_tag}};
`endif
for (genvar i = 0; i < `NUM_THREADS; ++i) begin
`ifdef DBG_CACHE_REQ_INFO
assign dcache_req_if.tag[i] = {req_pc, req_wid, req_tag, req_addr_type[i]};
`else
assign dcache_req_if.tag[i] = {req_tag, req_addr_type[i]};
`endif
end
assign ready_in = req_dep_ready && req_ready_all;
@@ -293,18 +328,22 @@ module VX_lsu_unit #(
if (dcache_req_if.rw[0]) begin
$write("%t: D$%0d Wr Req: wid=%0d, PC=%0h, tmask=%b, addr=", $time, CORE_ID, req_wid, req_pc, dcache_req_fire);
`PRINT_ARRAY1D(req_addr, `NUM_THREADS);
$write(", tag=%0h, byteen=%0h, data=", dcache_req_if.tag[0], dcache_req_if.byteen);
$write(", tag=%0h, byteen=%0h, type=", req_tag, dcache_req_if.byteen);
`PRINT_ARRAY1D(req_addr_type, `NUM_THREADS);
$write(", data=");
`PRINT_ARRAY1D(dcache_req_if.data, `NUM_THREADS);
$write("\n");
end else begin
$write("%t: D$%0d Rd Req: wid=%0d, PC=%0h, tmask=%b, addr=", $time, CORE_ID, req_wid, req_pc, dcache_req_fire);
`PRINT_ARRAY1D(req_addr, `NUM_THREADS);
$write(", tag=%0h, byteen=%0h, rd=%0d, is_dup=%b\n", dcache_req_if.tag[0], dcache_req_if.byteen, req_rd, req_is_dup);
$write(", tag=%0h, byteen=%0h, type=", req_tag, dcache_req_if.byteen);
`PRINT_ARRAY1D(req_addr_type, `NUM_THREADS);
$write(", rd=%0d, is_dup=%b\n", req_rd, req_is_dup);
end
end
if (dcache_rsp_fire) begin
$write("%t: D$%0d Rsp: valid=%b, wid=%0d, PC=%0h, tag=%0h, rd=%0d, data=",
$time, CORE_ID, dcache_rsp_if.valid, rsp_wid, rsp_pc, dcache_rsp_if.tag, rsp_rd);
$time, CORE_ID, dcache_rsp_if.valid, rsp_wid, rsp_pc, mbuf_raddr, rsp_rd);
`PRINT_ARRAY1D(dcache_rsp_if.data, `NUM_THREADS);
$write(", is_dup=%b\n", rsp_is_dup);
end

19
hw/rtl/VX_mem_unit.v
View File

@@ -41,25 +41,25 @@ module VX_mem_unit # (
) dcache_mem_rsp_if(), icache_mem_rsp_if();
VX_dcache_core_req_if #(
.NUM_REQS (`DNUM_REQUESTS),
.NUM_REQS (`DNUM_REQS),
.WORD_SIZE (`DWORD_SIZE),
.CORE_TAG_WIDTH (`DCORE_TAG_WIDTH)
) dcache_req_if();
VX_dcache_core_rsp_if #(
.NUM_REQS (`DNUM_REQUESTS),
.NUM_REQS (`DNUM_REQS),
.WORD_SIZE (`DWORD_SIZE),
.CORE_TAG_WIDTH (`DCORE_TAG_WIDTH)
) dcache_rsp_if();
VX_dcache_core_req_if #(
.NUM_REQS (`DNUM_REQUESTS),
.NUM_REQS (`DNUM_REQS),
.WORD_SIZE (`DWORD_SIZE),
.CORE_TAG_WIDTH (`DCORE_TAG_WIDTH)
) smem_req_if();
VX_dcache_core_rsp_if #(
.NUM_REQS (`DNUM_REQUESTS),
.NUM_REQS (`DNUM_REQS),
.WORD_SIZE (`DWORD_SIZE),
.CORE_TAG_WIDTH (`DCORE_TAG_WIDTH)
) smem_rsp_if();
@@ -108,8 +108,6 @@ module VX_mem_unit # (
.clk (clk),
.reset (icache_reset),
.flush (1'b0),
// Core request
.core_req_valid (icache_core_req_if.valid),
.core_req_rw (1'b0),
@@ -152,7 +150,7 @@ module VX_mem_unit # (
.NUM_BANKS (`DNUM_BANKS),
.NUM_PORTS (`DNUM_PORTS),
.WORD_SIZE (`DWORD_SIZE),
.NUM_REQS (`DNUM_REQUESTS),
.NUM_REQS (`DNUM_REQS),
.CREQ_SIZE (`DCREQ_SIZE),
.MSHR_SIZE (`DMSHR_SIZE),
.MRSQ_SIZE (`DMRSQ_SIZE),
@@ -160,15 +158,14 @@ module VX_mem_unit # (
.WRITE_ENABLE (1),
.CORE_TAG_WIDTH (`DCORE_TAG_WIDTH),
.CORE_TAG_ID_BITS (`DCORE_TAG_ID_BITS),
.MEM_TAG_WIDTH (`DMEM_TAG_WIDTH)
.MEM_TAG_WIDTH (`DMEM_TAG_WIDTH),
.NC_ENABLE (1)
) dcache (
`SCOPE_BIND_VX_mem_unit_dcache
.clk (clk),
.reset (dcache_reset),
.flush (1'b0),
// Core req
.core_req_valid (dcache_req_if.valid),
.core_req_rw (dcache_req_if.rw),
@@ -219,7 +216,7 @@ module VX_mem_unit # (
.CACHE_SIZE (`SMEM_SIZE),
.NUM_BANKS (`SNUM_BANKS),
.WORD_SIZE (`SWORD_SIZE),
.NUM_REQS (`SNUM_REQUESTS),
.NUM_REQS (`SNUM_REQS),
.CREQ_SIZE (`SCREQ_SIZE),
.CORE_TAG_WIDTH (`DCORE_TAG_WIDTH),
.CORE_TAG_ID_BITS (`DCORE_TAG_ID_BITS),

9
hw/rtl/Vortex.v
View File

@@ -39,6 +39,7 @@ module Vortex (
output wire busy,
output wire ebreak
);
`STATIC_ASSERT((`L3_ENABLE == 0 || `NUM_CLUSTERS > 1), ("invalid parameter"))
wire [`NUM_CLUSTERS-1:0] per_cluster_mem_req_valid;
wire [`NUM_CLUSTERS-1:0] per_cluster_mem_req_rw;
@@ -168,7 +169,7 @@ module Vortex (
.CACHE_LINE_SIZE (`L3CACHE_LINE_SIZE),
.NUM_BANKS (`L3NUM_BANKS),
.WORD_SIZE (`L3WORD_SIZE),
.NUM_REQS (`NUM_CLUSTERS),
.NUM_REQS (`L3NUM_REQS),
.CREQ_SIZE (`L3CREQ_SIZE),
.MSHR_SIZE (`L3MSHR_SIZE),
.MRSQ_SIZE (`L3MRSQ_SIZE),
@@ -176,15 +177,14 @@ module Vortex (
.WRITE_ENABLE (1),
.CORE_TAG_WIDTH (`L2MEM_TAG_WIDTH),
.CORE_TAG_ID_BITS (0),
.MEM_TAG_WIDTH (`L3MEM_TAG_WIDTH)
.MEM_TAG_WIDTH (`L3MEM_TAG_WIDTH),
.NC_ENABLE (1)
) l3cache (
`SCOPE_BIND_Vortex_l3cache
.clk (clk),
.reset (reset),
.flush (1'b0),
`ifdef PERF_ENABLE
.perf_cache_if (perf_l3cache_if),
`endif
@@ -267,7 +267,6 @@ module Vortex (
end
`SCOPE_ASSIGN (reset, reset);
`SCOPE_ASSIGN (mem_req_fire, mem_req_valid && mem_req_ready);
`SCOPE_ASSIGN (mem_req_addr, `TO_FULL_ADDR(mem_req_addr));
`SCOPE_ASSIGN (mem_req_rw, mem_req_rw);

324
hw/rtl/cache/VX_cache.v vendored
View File

@@ -36,30 +36,38 @@ module VX_cache #(
parameter CORE_TAG_ID_BITS = CORE_TAG_WIDTH,
// Memory request tag size
parameter MEM_TAG_WIDTH = (32 - $clog2(CACHE_LINE_SIZE)),
parameter MEM_TAG_WIDTH = (32 - $clog2(CACHE_LINE_SIZE)),
// bank offset from beginning of index range
parameter BANK_ADDR_OFFSET = 0
parameter BANK_ADDR_OFFSET = 0,
// enable bypass for non-cacheable addresses
parameter NC_ENABLE = 0
) (
`SCOPE_IO_VX_cache
`SCOPE_IO_VX_cache
// PERF
`ifdef PERF_ENABLE
VX_perf_cache_if perf_cache_if,
`endif
input wire clk,
input wire reset,
// Core request
input wire [NUM_REQS-1:0] core_req_valid,
input wire [NUM_REQS-1:0] core_req_rw,
input wire [NUM_REQS-1:0][`WORD_ADDR_WIDTH-1:0] core_req_addr,
input wire [NUM_REQS-1:0][WORD_SIZE-1:0] core_req_byteen,
input wire [NUM_REQS-1:0][`WORD_WIDTH-1:0] core_req_data,
input wire [NUM_REQS-1:0][CORE_TAG_WIDTH-1:0] core_req_tag,
output wire [NUM_REQS-1:0] core_req_ready,
input wire [NUM_REQS-1:0] core_req_valid,
input wire [NUM_REQS-1:0] core_req_rw,
input wire [NUM_REQS-1:0][`WORD_ADDR_WIDTH-1:0] core_req_addr,
input wire [NUM_REQS-1:0][WORD_SIZE-1:0] core_req_byteen,
input wire [NUM_REQS-1:0][`WORD_WIDTH-1:0] core_req_data,
input wire [NUM_REQS-1:0][CORE_TAG_WIDTH-1:0] core_req_tag,
output wire [NUM_REQS-1:0] core_req_ready,
// Core response
output wire [NUM_REQS-1:0] core_rsp_valid,
output wire [NUM_REQS-1:0][`WORD_WIDTH-1:0] core_rsp_data,
output wire [NUM_REQS-1:0] core_rsp_valid,
output wire [NUM_REQS-1:0][`WORD_WIDTH-1:0] core_rsp_data,
output wire [`CORE_REQ_TAG_COUNT-1:0][CORE_TAG_WIDTH-1:0] core_rsp_tag,
input wire [`CORE_REQ_TAG_COUNT-1:0] core_rsp_ready,
input wire [`CORE_REQ_TAG_COUNT-1:0] core_rsp_ready,
// Memory request
output wire mem_req_valid,
@@ -74,18 +82,206 @@ module VX_cache #(
input wire mem_rsp_valid,
input wire [`CACHE_LINE_WIDTH-1:0] mem_rsp_data,
input wire [MEM_TAG_WIDTH-1:0] mem_rsp_tag,
output wire mem_rsp_ready,
// PERF
`ifdef PERF_ENABLE
VX_perf_cache_if perf_cache_if,
`endif
// device flush
input wire flush
output wire mem_rsp_ready
);
`STATIC_ASSERT(NUM_BANKS <= NUM_REQS, ("invalid value"))
`ifdef PERF_ENABLE
wire [NUM_BANKS-1:0] perf_read_miss_per_bank;
wire [NUM_BANKS-1:0] perf_write_miss_per_bank;
wire [NUM_BANKS-1:0] perf_mshr_stall_per_bank;
wire [NUM_BANKS-1:0] perf_pipe_stall_per_bank;
`endif
///////////////////////////////////////////////////////////////////////////
// Core request
wire [NUM_REQS-1:0] core_req_valid_out;
wire [NUM_REQS-1:0] core_req_rw_out;
wire [NUM_REQS-1:0][`WORD_ADDR_WIDTH-1:0] core_req_addr_out;
wire [NUM_REQS-1:0][WORD_SIZE-1:0] core_req_byteen_out;
wire [NUM_REQS-1:0][`WORD_WIDTH-1:0] core_req_data_out;
wire [NUM_REQS-1:0][CORE_TAG_WIDTH-1:0] core_req_tag_out;
wire [NUM_REQS-1:0] core_req_ready_out;
// Core response
wire [NUM_REQS-1:0] core_rsp_valid_in;
wire [NUM_REQS-1:0][`WORD_WIDTH-1:0] core_rsp_data_in;
wire [`CORE_REQ_TAG_COUNT-1:0][CORE_TAG_WIDTH-1:0] core_rsp_tag_in;
wire [`CORE_REQ_TAG_COUNT-1:0] core_rsp_ready_in;
// Memory request
wire mem_req_valid_in;
wire mem_req_rw_in;
wire [CACHE_LINE_SIZE-1:0] mem_req_byteen_in;
wire [`MEM_ADDR_WIDTH-1:0] mem_req_addr_in;
wire [`CACHE_LINE_WIDTH-1:0] mem_req_data_in;
wire [MEM_TAG_WIDTH-1:0] mem_req_tag_in;
wire mem_req_ready_in;
// Memory response
wire mem_rsp_valid_out;
wire [`CACHE_LINE_WIDTH-1:0] mem_rsp_data_out;
wire [MEM_TAG_WIDTH-1:0] mem_rsp_tag_out;
wire mem_rsp_ready_out;
if (NC_ENABLE) begin
VX_nc_bypass #(
.NUM_REQS (NUM_REQS),
.NUM_RSP_TAGS (`CORE_REQ_TAG_COUNT),
.NC_TAG_BIT (0),
.CORE_ADDR_WIDTH(`WORD_ADDR_WIDTH),
.CORE_DATA_SIZE (WORD_SIZE),
.CORE_TAG_WIDTH (CORE_TAG_WIDTH),
.MEM_ADDR_WIDTH (`MEM_ADDR_WIDTH),
.MEM_DATA_SIZE (CACHE_LINE_SIZE),
.MEM_TAG_WIDTH (MEM_TAG_WIDTH)
) nc_bypass (
.clk (clk),
.reset (reset),
// Core request in
.core_req_valid_in (core_req_valid),
.core_req_rw_in (core_req_rw),
.core_req_byteen_in (core_req_byteen),
.core_req_addr_in (core_req_addr),
.core_req_data_in (core_req_data),
.core_req_tag_in (core_req_tag),
.core_req_ready_in (core_req_ready),
// Core request out
.core_req_valid_out (core_req_valid_out),
.core_req_rw_out (core_req_rw_out),
.core_req_byteen_out(core_req_byteen_out),
.core_req_addr_out (core_req_addr_out),
.core_req_data_out (core_req_data_out),
.core_req_tag_out (core_req_tag_out),
.core_req_ready_out (core_req_ready_out),
// Core response in
.core_rsp_valid_in (core_rsp_valid_in),
.core_rsp_data_in (core_rsp_data_in),
.core_rsp_tag_in (core_rsp_tag_in),
.core_rsp_ready_in (core_rsp_ready_in),
// Core response out
.core_rsp_valid_out (core_rsp_valid),
.core_rsp_data_out (core_rsp_data),
.core_rsp_tag_out (core_rsp_tag),
.core_rsp_ready_out (core_rsp_ready),
// Memory request in
.mem_req_valid_in (mem_req_valid_in),
.mem_req_rw_in (mem_req_rw_in),
.mem_req_byteen_in (mem_req_byteen_in),
.mem_req_addr_in (mem_req_addr_in),
.mem_req_data_in (mem_req_data_in),
.mem_req_tag_in (mem_req_tag_in),
.mem_req_ready_in (mem_req_ready_in),
// Memory request out
.mem_req_valid_out (mem_req_valid),
.mem_req_rw_out (mem_req_rw),
.mem_req_byteen_out (mem_req_byteen),
.mem_req_addr_out (mem_req_addr),
.mem_req_data_out (mem_req_data),
.mem_req_tag_out (mem_req_tag),
.mem_req_ready_out (mem_req_ready),
// Memory response in
.mem_rsp_valid_in (mem_rsp_valid),
.mem_rsp_data_in (mem_rsp_data),
.mem_rsp_tag_in (mem_rsp_tag),
.mem_rsp_ready_in (mem_rsp_ready),
// Memory response out
.mem_rsp_valid_out (mem_rsp_valid_out),
.mem_rsp_data_out (mem_rsp_data_out),
.mem_rsp_tag_out (mem_rsp_tag_out),
.mem_rsp_ready_out (mem_rsp_ready_out)
);
end else begin
assign core_req_valid_out = core_req_valid;
assign core_req_rw_out = core_req_rw;
assign core_req_addr_out = core_req_addr;
assign core_req_byteen_out = core_req_byteen;
assign core_req_data_out = core_req_data;
assign core_req_tag_out = core_req_tag;
assign core_req_ready = core_req_ready_out;
assign core_rsp_valid = core_rsp_valid_in;
assign core_rsp_data = core_rsp_data_in;
assign core_rsp_tag = core_rsp_tag_in;
assign core_rsp_ready_in = core_rsp_ready;
assign mem_req_valid = mem_req_valid_in;
assign mem_req_rw = mem_req_rw_in;
assign mem_req_addr = mem_req_addr_in;
assign mem_req_byteen = mem_req_byteen_in;
assign mem_req_data = mem_req_data_in;
assign mem_req_tag = mem_req_tag_in;
assign mem_req_ready_in = mem_req_ready;
assign mem_rsp_valid_out = mem_rsp_valid;
assign mem_rsp_data_out = mem_rsp_data;
assign mem_rsp_tag_out = mem_rsp_tag;
assign mem_rsp_ready = mem_rsp_ready_out;
end
///////////////////////////////////////////////////////////////////////////
wire [`CACHE_LINE_WIDTH-1:0] mem_rsp_data_qual;
wire [`MEM_ADDR_WIDTH-1:0] mem_rsp_tag_out_a, mem_rsp_tag_qual;
wire mrsq_full, mrsq_empty;
wire mrsq_push, mrsq_pop;
assign mrsq_push = mem_rsp_valid_out && mem_rsp_ready_out;
assign mem_rsp_ready_out = !mrsq_full;
// trim out shared memory and non-cacheable flags
assign mem_rsp_tag_out_a = mem_rsp_tag_out[2 +: `MEM_ADDR_WIDTH];
VX_fifo_queue #(
.DATAW (`MEM_ADDR_WIDTH + `CACHE_LINE_WIDTH),
.SIZE (MRSQ_SIZE),
.BUFFERED (1)
) mem_rsp_queue (
.clk (clk),
.reset (reset),
.push (mrsq_push),
.pop (mrsq_pop),
.data_in ({mem_rsp_tag_out_a, mem_rsp_data_out}),
.data_out ({mem_rsp_tag_qual, mem_rsp_data_qual}),
.empty (mrsq_empty),
.full (mrsq_full),
`UNUSED_PIN (alm_full),
`UNUSED_PIN (alm_empty),
`UNUSED_PIN (size)
);
`UNUSED_VAR (mem_rsp_tag_out)
///////////////////////////////////////////////////////////////////////////
wire [`LINE_SELECT_BITS-1:0] flush_addr;
wire flush_enable;
VX_flush_ctrl #(
.CACHE_SIZE (CACHE_SIZE),
.CACHE_LINE_SIZE (CACHE_LINE_SIZE),
.NUM_BANKS (NUM_BANKS)
) flush_ctrl (
.clk (clk),
.reset (reset),
.addr_out (flush_addr),
.valid_out (flush_enable)
);
///////////////////////////////////////////////////////////////////////////
wire [NUM_BANKS-1:0][NUM_PORTS-1:0] per_bank_core_req_valid;
wire [NUM_BANKS-1:0][NUM_PORTS-1:0][`UP(`WORD_SELECT_BITS)-1:0] per_bank_core_req_wsel;
@@ -112,44 +308,6 @@ module VX_cache #(
wire [NUM_BANKS-1:0] per_bank_mem_req_ready;
wire [NUM_BANKS-1:0] per_bank_mem_rsp_ready;
wire [`CACHE_LINE_WIDTH-1:0] mem_rsp_data_qual;
wire [MEM_TAG_WIDTH-1:0] mem_rsp_tag_qual;
wire [`LINE_SELECT_BITS-1:0] flush_addr;
wire flush_enable;
`ifdef PERF_ENABLE
wire [NUM_BANKS-1:0] perf_read_miss_per_bank;
wire [NUM_BANKS-1:0] perf_write_miss_per_bank;
wire [NUM_BANKS-1:0] perf_mshr_stall_per_bank;
wire [NUM_BANKS-1:0] perf_pipe_stall_per_bank;
`endif
///////////////////////////////////////////////////////////////////////////
wire mrsq_full, mrsq_empty;
wire mrsq_push, mrsq_pop;
assign mrsq_push = mem_rsp_valid && mem_rsp_ready;
assign mem_rsp_ready = !mrsq_full;
VX_fifo_queue #(
.DATAW (MEM_TAG_WIDTH + `CACHE_LINE_WIDTH),
.SIZE (MRSQ_SIZE),
.BUFFERED (1)
) mem_rsp_queue (
.clk (clk),
.reset (reset),
.push (mrsq_push),
.pop (mrsq_pop),
.data_in ({mem_rsp_tag, mem_rsp_data}),
.data_out ({mem_rsp_tag_qual, mem_rsp_data_qual}),
.empty (mrsq_empty),
.full (mrsq_full),
`UNUSED_PIN (alm_full),
`UNUSED_PIN (alm_empty),
`UNUSED_PIN (size)
);
if (NUM_BANKS == 1) begin
`UNUSED_VAR (mem_rsp_tag_qual)
@@ -158,21 +316,6 @@ module VX_cache #(
assign mrsq_pop = !mrsq_empty && per_bank_mem_rsp_ready[`MEM_ADDR_BANK(mem_rsp_tag_qual)];
end
///////////////////////////////////////////////////////////////////////////
VX_flush_ctrl #(
.CACHE_SIZE (CACHE_SIZE),
.CACHE_LINE_SIZE (CACHE_LINE_SIZE),
.NUM_BANKS (NUM_BANKS)
) flush_ctrl (
.clk (clk),
.reset (reset || flush),
.addr_out (flush_addr),
.valid_out (flush_enable)
);
///////////////////////////////////////////////////////////////////////////
VX_cache_core_req_bank_sel #(
.CACHE_ID (CACHE_ID),
.CACHE_LINE_SIZE (CACHE_LINE_SIZE),
@@ -188,13 +331,13 @@ module VX_cache #(
`ifdef PERF_ENABLE
.bank_stalls(perf_cache_if.bank_stalls),
`endif
.core_req_valid (core_req_valid),
.core_req_rw (core_req_rw),
.core_req_addr (core_req_addr),
.core_req_byteen(core_req_byteen),
.core_req_data (core_req_data),
.core_req_tag (core_req_tag),
.core_req_ready (core_req_ready),
.core_req_valid (core_req_valid_out),
.core_req_rw (core_req_rw_out),
.core_req_addr (core_req_addr_out),
.core_req_byteen(core_req_byteen_out),
.core_req_data (core_req_data_out),
.core_req_tag (core_req_tag_out),
.core_req_ready (core_req_ready_out),
.per_bank_core_req_valid (per_bank_core_req_valid),
.per_bank_core_req_rw (per_bank_core_req_rw),
.per_bank_core_req_addr (per_bank_core_req_addr),
@@ -365,10 +508,10 @@ module VX_cache #(
.per_bank_core_rsp_tag (per_bank_core_rsp_tag),
.per_bank_core_rsp_tid (per_bank_core_rsp_tid),
.per_bank_core_rsp_ready (per_bank_core_rsp_ready),
.core_rsp_valid (core_rsp_valid),
.core_rsp_tag (core_rsp_tag),
.core_rsp_data (core_rsp_data),
.core_rsp_ready (core_rsp_ready)
.core_rsp_valid (core_rsp_valid_in),
.core_rsp_tag (core_rsp_tag_in),
.core_rsp_data (core_rsp_data_in),
.core_rsp_ready (core_rsp_ready_in)
);
wire [NUM_BANKS-1:0][(`MEM_ADDR_WIDTH + 1 + CACHE_LINE_SIZE + `CACHE_LINE_WIDTH)-1:0] data_in;
@@ -386,12 +529,13 @@ module VX_cache #(
.valid_in (per_bank_mem_req_valid),
.data_in (data_in),
.ready_in (per_bank_mem_req_ready),
.valid_out (mem_req_valid),
.data_out ({mem_req_addr, mem_req_rw, mem_req_byteen, mem_req_data}),
.ready_out (mem_req_ready)
.valid_out (mem_req_valid_in),
.data_out ({mem_req_addr_in, mem_req_rw_in, mem_req_byteen_in, mem_req_data_in}),
.ready_out (mem_req_ready_in)
);
assign mem_req_tag = mem_req_addr;
// build memory tag adding shared memory and non-cacheable flags
assign mem_req_tag_in = MEM_TAG_WIDTH'({mem_req_addr_in, 1'b0, 1'b0});
`ifdef PERF_ENABLE
// per cycle: core_reads, core_writes

301
hw/rtl/cache/VX_nc_bypass.v vendored Normal file
View File

@@ -0,0 +1,301 @@
`include "VX_cache_define.vh"
module VX_nc_bypass #(
parameter NUM_REQS = 1,
parameter NUM_RSP_TAGS = 0,
parameter NC_TAG_BIT = 0,
parameter CORE_ADDR_WIDTH = 1,
parameter CORE_DATA_SIZE = 1,
parameter CORE_TAG_WIDTH = 1,
parameter MEM_ADDR_WIDTH = 1,
parameter MEM_DATA_SIZE = 1,
parameter MEM_TAG_WIDTH = 1,
parameter CORE_DATA_WIDTH = CORE_DATA_SIZE * 8,
parameter MEM_DATA_WIDTH = MEM_DATA_SIZE * 8
) (
input wire clk,
input wire reset,
// Core request in
input wire [NUM_REQS-1:0] core_req_valid_in,
input wire [NUM_REQS-1:0] core_req_rw_in,
input wire [NUM_REQS-1:0][CORE_ADDR_WIDTH-1:0] core_req_addr_in,
input wire [NUM_REQS-1:0][CORE_DATA_SIZE-1:0] core_req_byteen_in,
input wire [NUM_REQS-1:0][CORE_DATA_WIDTH-1:0] core_req_data_in,
input wire [NUM_REQS-1:0][CORE_TAG_WIDTH-1:0] core_req_tag_in,
output wire [NUM_REQS-1:0] core_req_ready_in,
// Core request out
output wire [NUM_REQS-1:0] core_req_valid_out,
output wire [NUM_REQS-1:0] core_req_rw_out,
output wire [NUM_REQS-1:0][CORE_ADDR_WIDTH-1:0] core_req_addr_out,
output wire [NUM_REQS-1:0][CORE_DATA_SIZE-1:0] core_req_byteen_out,
output wire [NUM_REQS-1:0][CORE_DATA_WIDTH-1:0] core_req_data_out,
output wire [NUM_REQS-1:0][CORE_TAG_WIDTH-1:0] core_req_tag_out,
input wire [NUM_REQS-1:0] core_req_ready_out,
// Core response in
input wire [NUM_REQS-1:0] core_rsp_valid_in,
input wire [NUM_REQS-1:0][CORE_DATA_WIDTH-1:0] core_rsp_data_in,
input wire [NUM_RSP_TAGS-1:0][CORE_TAG_WIDTH-1:0] core_rsp_tag_in,
output wire [NUM_RSP_TAGS-1:0] core_rsp_ready_in,
// Core response out
output wire [NUM_REQS-1:0] core_rsp_valid_out,
output wire [NUM_REQS-1:0][CORE_DATA_WIDTH-1:0] core_rsp_data_out,
output wire [NUM_RSP_TAGS-1:0][CORE_TAG_WIDTH-1:0] core_rsp_tag_out,
input wire [NUM_RSP_TAGS-1:0] core_rsp_ready_out,
// Memory request in
input wire mem_req_valid_in,
input wire mem_req_rw_in,
input wire [MEM_ADDR_WIDTH-1:0] mem_req_addr_in,
input wire [MEM_DATA_SIZE-1:0] mem_req_byteen_in,
input wire [MEM_DATA_WIDTH-1:0] mem_req_data_in,
input wire [MEM_TAG_WIDTH-1:0] mem_req_tag_in,
output wire mem_req_ready_in,
// Memory request out
output wire mem_req_valid_out,
output wire mem_req_rw_out,
output wire [MEM_ADDR_WIDTH-1:0] mem_req_addr_out,
output wire [MEM_DATA_SIZE-1:0] mem_req_byteen_out,
output wire [MEM_DATA_WIDTH-1:0] mem_req_data_out,
output wire [MEM_TAG_WIDTH-1:0] mem_req_tag_out,
input wire mem_req_ready_out,
// Memory response in
input wire mem_rsp_valid_in,
input wire [MEM_DATA_WIDTH-1:0] mem_rsp_data_in,
input wire [MEM_TAG_WIDTH-1:0] mem_rsp_tag_in,
output wire mem_rsp_ready_in,
// Memory response out
output wire mem_rsp_valid_out,
output wire [MEM_DATA_WIDTH-1:0] mem_rsp_data_out,
output wire [MEM_TAG_WIDTH-1:0] mem_rsp_tag_out,
input wire mem_rsp_ready_out
);
`STATIC_ASSERT((NUM_RSP_TAGS == 1 || NUM_RSP_TAGS == NUM_REQS), ("invalid paramter"))
`UNUSED_VAR (clk)
`UNUSED_VAR (reset)
localparam CORE_REQ_TIDW = $clog2(NUM_REQS);
localparam CORE_LDATAW = $clog2(CORE_DATA_WIDTH);
localparam MEM_LDATAW = $clog2(MEM_DATA_WIDTH);
localparam D = MEM_LDATAW - CORE_LDATAW;
localparam P = 2**D;
// core request handling
reg [NUM_REQS-1:0] core_req_valid_out_r;
reg [NUM_REQS-1:0] core_req_ready_in_r;
wire [NUM_REQS-1:0] core_req_valid_in_nc;
wire [CORE_REQ_TIDW-1:0] core_req_nc_tid;
for (genvar i = 0; i < NUM_REQS; ++i) begin
assign core_req_valid_in_nc[i] = core_req_valid_in[i] && core_req_tag_in[i][NC_TAG_BIT];
end
always @(*) begin
for (integer i = 0; i < NUM_REQS; ++i) begin
if (core_req_valid_in_nc[i]) begin
core_req_valid_out_r[i] = 0;
core_req_ready_in_r[i] = mem_req_ready_out && (core_req_nc_tid == CORE_REQ_TIDW'(i));
end else begin
core_req_valid_out_r[i] = core_req_valid_in[i];
core_req_ready_in_r[i] = core_req_ready_out[i];
end
end
end
assign core_req_valid_out = core_req_valid_out_r;
assign core_req_rw_out = core_req_rw_in;
assign core_req_addr_out = core_req_addr_in;
assign core_req_byteen_out = core_req_byteen_in;
assign core_req_data_out = core_req_data_in;
assign core_req_tag_out = core_req_tag_in;
assign core_req_ready_in = core_req_ready_in_r;
// memory request handling
reg mem_req_valid_out_r;
reg mem_req_rw_out_r;
reg [MEM_DATA_SIZE-1:0] mem_req_byteen_out_r;
reg [MEM_ADDR_WIDTH-1:0] mem_req_addr_out_r;
reg [MEM_DATA_WIDTH-1:0] mem_req_data_out_r;
reg [MEM_TAG_WIDTH-1:0] mem_req_tag_out_r;
reg mem_req_ready_in_r;
wire core_req_nc_valid;
VX_priority_encoder #(
.N (NUM_REQS)
) core_req_sel (
.data_in (core_req_valid_in_nc),
.index (core_req_nc_tid),
`UNUSED_PIN (onehot),
.valid_out (core_req_nc_valid)
);
always @(*) begin
if (core_req_nc_valid) begin
mem_req_valid_out_r = 1;
mem_req_rw_out_r = core_req_rw_in[core_req_nc_tid];
mem_req_addr_out_r = core_req_addr_in[core_req_nc_tid][D +: MEM_ADDR_WIDTH];
for (integer i = 0; i < P; ++i) begin
mem_req_data_out_r[i * CORE_DATA_WIDTH +: CORE_DATA_WIDTH] = core_req_data_in[core_req_nc_tid];
end
mem_req_ready_in_r = 0;
end else begin
mem_req_valid_out_r = mem_req_valid_in;
mem_req_rw_out_r = mem_req_rw_in;
mem_req_addr_out_r = mem_req_addr_in;
mem_req_data_out_r = mem_req_data_in;
mem_req_ready_in_r = mem_req_ready_out;
end
end
if (D != 0) begin
wire [D-1:0] req_addr_idx = core_req_addr_in[core_req_nc_tid][D-1:0];
always @(*) begin
if (core_req_nc_valid) begin
mem_req_byteen_out_r = 0;
mem_req_byteen_out_r[req_addr_idx * CORE_DATA_SIZE +: CORE_DATA_SIZE] = core_req_byteen_in[core_req_nc_tid];
mem_req_tag_out_r = MEM_TAG_WIDTH'({core_req_nc_tid, req_addr_idx, core_req_tag_in[core_req_nc_tid]});
end else begin
mem_req_byteen_out_r = mem_req_byteen_in;
mem_req_tag_out_r = mem_req_tag_in;
end
end
end else begin
always @(*) begin
if (core_req_nc_valid) begin
mem_req_byteen_out_r = core_req_byteen_in[core_req_nc_tid];
mem_req_tag_out_r = MEM_TAG_WIDTH'({core_req_nc_tid, core_req_tag_in[core_req_nc_tid]});
end else begin
mem_req_byteen_out_r = mem_req_byteen_in;
mem_req_tag_out_r = mem_req_tag_in;
end
end
end
assign mem_req_valid_out = mem_req_valid_out_r;
assign mem_req_rw_out = mem_req_rw_out_r;
assign mem_req_addr_out = mem_req_addr_out_r;
assign mem_req_byteen_out = mem_req_byteen_out_r;
assign mem_req_data_out = mem_req_data_out_r;
assign mem_req_tag_out = mem_req_tag_out_r;
assign mem_req_ready_in = mem_req_ready_in_r;
// core response handling
reg [NUM_REQS-1:0] core_rsp_valid_out_r;
reg [NUM_REQS-1:0][CORE_DATA_WIDTH-1:0] core_rsp_data_out_r;
reg [NUM_RSP_TAGS-1:0][CORE_TAG_WIDTH-1:0] core_rsp_tag_out_r;
reg [NUM_RSP_TAGS-1:0] core_rsp_ready_in_r;
wire [CORE_REQ_TIDW-1:0] rsp_tid = mem_rsp_tag_in[(CORE_TAG_WIDTH + D) +: CORE_REQ_TIDW];
wire is_mem_rsp_nc = mem_rsp_valid_in && mem_rsp_tag_in[NC_TAG_BIT];
if (NUM_REQS > 1) begin
always @(*) begin
if (is_mem_rsp_nc) begin
core_rsp_valid_out_r = 0;
core_rsp_valid_out_r[rsp_tid] = 1;
for (integer i = 0; i < NUM_RSP_TAGS; ++i) begin
core_rsp_tag_out_r[i] = mem_rsp_tag_in[CORE_TAG_WIDTH-1:0];
end
core_rsp_ready_in_r = 0;
end else begin
core_rsp_valid_out_r = core_rsp_valid_in;
core_rsp_tag_out_r = core_rsp_tag_in;
core_rsp_ready_in_r = core_rsp_ready_out;
end
end
end else begin
always @(*) begin
if (is_mem_rsp_nc) begin
core_rsp_valid_out_r = 1;
core_rsp_tag_out_r = mem_rsp_tag_in[CORE_TAG_WIDTH-1:0];
core_rsp_ready_in_r = 0;
end else begin
core_rsp_valid_out_r = core_rsp_valid_in;
core_rsp_tag_out_r = core_rsp_tag_in;
core_rsp_ready_in_r = core_rsp_ready_out;
end
end
end
if (D != 0) begin
wire [D-1:0] rsp_addr_idx = mem_rsp_tag_in[CORE_TAG_WIDTH +: D];
always @(*) begin
if (is_mem_rsp_nc) begin
for (integer i = 0; i < NUM_REQS; ++i) begin
core_rsp_data_out_r[i] = mem_rsp_data_in[rsp_addr_idx * CORE_DATA_WIDTH +: CORE_DATA_WIDTH];
end
end else begin
core_rsp_data_out_r = core_rsp_data_in;
end
end
end else begin
always @(*) begin
if (is_mem_rsp_nc) begin
for (integer i = 0; i < NUM_REQS; ++i) begin
core_rsp_data_out_r[i] = mem_rsp_data_in;
end
end else begin
core_rsp_data_out_r = core_rsp_data_in;
end
end
end
assign core_rsp_valid_out = core_rsp_valid_out_r;
assign core_rsp_data_out = core_rsp_data_out_r;
assign core_rsp_tag_out = core_rsp_tag_out_r;
assign core_rsp_ready_in = core_rsp_ready_in_r;
// memory response handling
reg mem_rsp_valid_out_r;
reg mem_rsp_ready_in_r;
always @(*) begin
if (is_mem_rsp_nc) begin
mem_rsp_valid_out_r = 0;
end else begin
mem_rsp_valid_out_r = mem_rsp_valid_in;
end
end
if (NUM_RSP_TAGS > 1) begin
always @(*) begin
if (is_mem_rsp_nc) begin
mem_rsp_ready_in_r = core_rsp_ready_out[rsp_tid];
end else begin
mem_rsp_ready_in_r = mem_rsp_ready_out;
end
end
end else begin
always @(*) begin
if (is_mem_rsp_nc) begin
mem_rsp_ready_in_r = core_rsp_ready_out;
end else begin
mem_rsp_ready_in_r = mem_rsp_ready_out;
end
end
end
assign mem_rsp_valid_out = mem_rsp_valid_out_r;
assign mem_rsp_data_out = mem_rsp_data_in;
assign mem_rsp_tag_out = mem_rsp_tag_in;
assign mem_rsp_ready_in = mem_rsp_ready_in_r;
endmodule

8
hw/scripts/scope.json
View File

@@ -111,9 +111,9 @@
"!cci_pending_writes_full": 1,
"?afu_mem_req_fire": 1,
"afu_mem_req_addr": 26,
"afu_mem_req_tag": 28,
"afu_mem_req_tag": 30,
"?afu_mem_rsp_fire": 1,
"afu_mem_rsp_tag": 28
"afu_mem_rsp_tag": 30
},
"afu/vortex": {
"!reset": 1,
@@ -167,10 +167,10 @@
"dcache_req_rw": 1,
"dcache_req_byteen":"`NUM_THREADS * 4",
"dcache_req_data": "`NUM_THREADS * 32",
"dcache_req_tag":"`DCORE_TAG_ID_BITS",
"dcache_req_tag":"`LSUQ_ADDR_BITS",
"?dcache_rsp_fire":"`NUM_THREADS",
"dcache_rsp_data":"`NUM_THREADS * 32",
"dcache_rsp_tag":"`DCORE_TAG_ID_BITS"
"dcache_rsp_tag":"`LSUQ_ADDR_BITS"
},
"afu/vortex/cluster/core/pipeline/issue": {
"?issue_fire": 1,

2
hw/simulate/simulator.cpp
View File

@@ -309,7 +309,7 @@ void Simulator::run() {
}
int Simulator::get_last_wb_value(int reg) const {
return (int)vortex_->Vortex->genblk1__BRA__0__KET____DOT__cluster->genblk1__BRA__0__KET____DOT__core->pipeline->commit->writeback->last_wb_value[reg];
return (int)vortex_->Vortex->genblk2__BRA__0__KET____DOT__cluster->genblk2__BRA__0__KET____DOT__core->pipeline->commit->writeback->last_wb_value[reg];
}
void Simulator::load_bin(const char* program_file) {

2
hw/simulate/simulator.h
View File

@@ -50,7 +50,7 @@ private:
int cycles_left;
std::array<uint8_t, MEM_BLOCK_SIZE> block;
uint32_t addr;
uint32_t tag;
uint64_t tag;
} mem_req_t;
std::unordered_map<int, std::stringstream> print_bufs_;