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adding support for non-cacheable memory addressing

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This commit is contained in:
Blaise Tine
2021-06-06 13:35:55 -07:00
parent 84391c1a06
commit 3071fb7a29
23 changed files with 1605 additions and 205 deletions
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8
simX/core.cpp
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@@ -321,8 +321,8 @@ Word Core::dcache_read(Addr addr, Size size) {
++loads_;
Word data = 0;
#ifdef SM_ENABLE
if ((addr >= (SHARED_MEM_BASE_ADDR - SMEM_SIZE))
&& ((addr + 3) < SHARED_MEM_BASE_ADDR)) {
if ((addr >= (SMEM_BASE_ADDR - SMEM_SIZE))
&& ((addr + 3) < SMEM_BASE_ADDR)) {
shared_mem_.read(addr & (SMEM_SIZE-1), &data, size);
return data;
}
@@ -334,8 +334,8 @@ Word Core::dcache_read(Addr addr, Size size) {
void Core::dcache_write(Addr addr, Word data, Size size) {
++stores_;
#ifdef SM_ENABLE
if ((addr >= (SHARED_MEM_BASE_ADDR - SMEM_SIZE))
&& ((addr + 3) < SHARED_MEM_BASE_ADDR)) {
if ((addr >= (SMEM_BASE_ADDR - SMEM_SIZE))
&& ((addr + 3) < SMEM_BASE_ADDR)) {
shared_mem_.write(addr & (SMEM_SIZE-1), &data, size);
return;
}