scope bug fixes
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@@ -291,56 +291,6 @@ def load_config(filename):
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print("condfig=", config)
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return config
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def gen_cc_header(file, ports):
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header = '''
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#pragma once\n
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struct scope_signal_t {
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int width;
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const char* name;
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};\n
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inline constexpr int __clog2(int n) { return (n > 1) ? 1 + __clog2((n + 1) >> 1) : 0; }\n
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static constexpr scope_signal_t scope_signals[] = {'''
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footer = "};"
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def eval_macro(text):
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expanded = expand_text(text)
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if expanded:
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text = expanded
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text = text.replace('$clog2', '__clog2')
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return text
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def asize_name(asize):
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def Q(arr, ss, asize, idx, N):
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for i in range(asize[idx]):
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tmp = ss + "_" + str(i)
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if (idx + 1) < N:
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Q(arr, tmp, asize, idx + 1, N)
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else:
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arr.append(tmp)
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l = len(asize)
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if l == 0:
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return [""]
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arr = []
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Q(arr, "", asize, 0, l)
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return arr
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with open(file, 'w') as f:
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print(header, file=f)
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i = 0
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for port in ports:
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name = port[0]
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size = eval_macro(str(port[1]))
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for ss in asize_name(port[2]):
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if i > 0:
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print(",", file=f)
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print("\t{" + size + ", \"" + name + ss + "\"}", file=f, end='')
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i += 1
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print("", file=f)
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print(footer, file=f)
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def gen_vl_header(file, taps, triggers):
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header = '''
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@@ -590,6 +540,68 @@ def gen_vl_header(file, taps, triggers):
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return all_ports
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def gen_cc_header(file, ports):
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header = '''
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#pragma once\n
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struct scope_signal_t {
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int width;
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const char* name;
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};\n
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inline constexpr int __clog2(int n) { return (n > 1) ? 1 + __clog2((n + 1) >> 1) : 0; }\n
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static constexpr scope_signal_t scope_signals[] = {'''
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footer = "};"
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def eval_macro(text):
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expanded = expand_text(text)
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if expanded:
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text = expanded
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text = text.replace('$clog2', '__clog2')
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return text
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def asize_name(asize):
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def Q(arr, ss, asize, idx, N):
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for i in range(asize[idx]):
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tmp = ss + "_" + str(i)
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if (idx + 1) < N:
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Q(arr, tmp, asize, idx + 1, N)
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else:
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arr.append(tmp)
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l = len(asize)
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if l == 0:
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return [""]
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arr = []
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Q(arr, "", asize, 0, l)
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return arr
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with open(file, 'w') as f:
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print(header, file=f)
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i = 0
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for port in ports:
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if port[3]:
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continue
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name = port[0]
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size = eval_macro(str(port[1]))
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for ss in asize_name(port[2]):
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if i > 0:
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print(",", file=f)
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print("\t{" + size + ", \"" + name + ss + "\"}", file=f, end='')
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i += 1
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for port in ports:
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if not port[3]:
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continue
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name = port[0]
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size = eval_macro(str(port[1]))
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for ss in asize_name(port[2]):
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if i > 0:
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print(",", file=f)
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print("\t{" + size + ", \"" + name + ss + "\"}", file=f, end='')
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i += 1
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print("", file=f)
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print(footer, file=f)
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def main():
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parser = argparse.ArgumentParser(description='Scope headers generator.')
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parser.add_argument('-vl', nargs='?', default='scope-defs.vh', metavar='file', help='Output Verilog header')
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