RTL code refactoring
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@@ -6,26 +6,26 @@ module VX_front_end (
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input wire schedule_delay,
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VX_warp_ctl_inter vx_warp_ctl,
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VX_warp_ctl_if vx_warp_ctl,
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VX_gpu_dcache_rsp_inter vx_icache_rsp,
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VX_gpu_dcache_req_inter vx_icache_req,
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VX_gpu_dcache_rsp_if vx_icache_rsp,
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VX_gpu_dcache_req_if vx_icache_req,
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VX_jal_response_inter vx_jal_rsp,
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VX_branch_response_inter vx_branch_rsp,
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VX_jal_response_if vx_jal_rsp,
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VX_branch_response_if vx_branch_rsp,
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VX_frE_to_bckE_req_inter vx_bckE_req,
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VX_frE_to_bckE_req_if vx_bckE_req,
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output wire fetch_ebreak
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);
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VX_inst_meta_inter fe_inst_meta_fi();
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VX_inst_meta_inter fe_inst_meta_fi2();
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VX_inst_meta_inter fe_inst_meta_id();
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VX_inst_meta_if fe_inst_meta_fi();
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VX_inst_meta_if fe_inst_meta_fi2();
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VX_inst_meta_if fe_inst_meta_id();
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VX_frE_to_bckE_req_inter vx_frE_to_bckE_req();
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VX_inst_meta_inter fd_inst_meta_de();
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VX_frE_to_bckE_req_if vx_frE_to_bckE_req();
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VX_inst_meta_if fd_inst_meta_de();
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wire total_freeze = schedule_delay;
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wire icache_stage_delay;
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@@ -48,8 +48,8 @@ end
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assign fetch_ebreak = vortex_ebreak || terminate_sim || old_ebreak;
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VX_wstall_inter vx_wstall();
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VX_join_inter vx_join();
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VX_wstall_if vx_wstall();
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VX_join_if vx_join();
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VX_fetch vx_fetch(
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.clk (clk),
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