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RTL code refactoring

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This commit is contained in:
Blaise Tine
2020-04-19 08:45:46 -04:00
parent 164eb5454c
commit 3139d37610
62 changed files with 261 additions and 256 deletions
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4
hw/rtl/pipe_regs/VX_d_e_reg.v
View File

@@ -5,8 +5,8 @@ module VX_d_e_reg (
input wire reset,
input wire in_branch_stall,
input wire in_freeze,
VX_frE_to_bckE_req_inter vx_frE_to_bckE_req,
VX_frE_to_bckE_req_inter vx_bckE_req
VX_frE_to_bckE_req_if vx_frE_to_bckE_req,
VX_frE_to_bckE_req_if vx_bckE_req
);
wire stall = in_freeze;

4
hw/rtl/pipe_regs/VX_f_d_reg.v
View File

@@ -5,8 +5,8 @@ module VX_f_d_reg (
input wire reset,
input wire in_freeze,
VX_inst_meta_inter fe_inst_meta_fd,
VX_inst_meta_inter fd_inst_meta_de
VX_inst_meta_if fe_inst_meta_fd,
VX_inst_meta_if fd_inst_meta_de
);

4
hw/rtl/pipe_regs/VX_i_d_reg.v
View File

@@ -5,8 +5,8 @@ module VX_i_d_reg (
input wire reset,
input wire in_freeze,
VX_inst_meta_inter fe_inst_meta_fd,
VX_inst_meta_inter fd_inst_meta_de
VX_inst_meta_if fe_inst_meta_fd,
VX_inst_meta_if fd_inst_meta_de
);