merged fpu_port branch
This commit is contained in:
Blaise Tine
@@ -173,7 +173,7 @@ extern int vx_dev_open(vx_device_h* hdevice) {
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{
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// Load device CAPS
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int ret = 0;
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ret |= vx_csr_get(device, 0, CSR_IMPL_ID, &device->implementation_id);
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ret |= vx_csr_get(device, 0, CSR_MIMPID, &device->implementation_id);
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ret |= vx_csr_get(device, 0, CSR_NC, &device->num_cores);
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ret |= vx_csr_get(device, 0, CSR_NW, &device->num_warps);
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ret |= vx_csr_get(device, 0, CSR_NT, &device->num_threads);
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@@ -217,14 +217,14 @@ extern int vx_dev_close(vx_device_h hdevice) {
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unsigned value;
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int ret = 0;
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ret |= vx_csr_get(hdevice, 0, CSR_INSTR_H, &value);
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ret |= vx_csr_get(hdevice, 0, CSR_INSTRET_H, &value);
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instrs = value;
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ret |= vx_csr_get(hdevice, 0, CSR_INSTR_L, &value);
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ret |= vx_csr_get(hdevice, 0, CSR_INSTRET, &value);
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instrs = (instrs << 32) | value;
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ret |= vx_csr_get(hdevice, 0, CSR_CYCLE_H, &value);
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cycles = value;
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ret |= vx_csr_get(hdevice, 0, CSR_CYCLE_L, &value);
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ret |= vx_csr_get(hdevice, 0, CSR_CYCLE, &value);
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cycles = (cycles << 32) | value;
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float IPC = (float)(double(instrs) / double(cycles));
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@@ -21,7 +21,7 @@ DBG_FLAGS += -DDBG_CORE_REQ_INFO
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#CONFIGS += -DNUM_CLUSTERS=1 -DNUM_CORES=2 -DL2_ENABLE=0
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CONFIGS += -DNUM_CLUSTERS=1 -DNUM_CORES=1
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DEBUG=1
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#DEBUG=1
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#AFU=1
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CFLAGS += -fPIC
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@@ -35,11 +35,13 @@ TOP = Vortex
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SRCS = vortex.cpp ../common/vx_utils.cpp ../../hw/simulate/simulator.cpp
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RTL_INCLUDE = -I../../hw/rtl -I../../hw/rtl/libs -I../../hw/rtl/interfaces -I../../hw/rtl/cache
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FPU_INCLUDE = -I../../hw/rtl/fp_cores/fpnew/src/common_cells/include -I../../hw/rtl/fp_cores/fpnew/src/common_cells/src -I../../hw/rtl/fp_cores/fpnew/src/fpu_div_sqrt_mvp/hdl -I../../hw/rtl/fp_cores/fpnew/src
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RTL_INCLUDE = -I../../hw/rtl -I../../hw/rtl/libs -I../../hw/rtl/interfaces -I../../hw/rtl/cache -I../../hw/rtl/fp_cores $(FPU_INCLUDE)
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VL_FLAGS += --language 1800-2009 --assert -Wall -Wpedantic $(CONFIGS)
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VL_FLAGS += -Wno-DECLFILENAME
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VL_FLAGS += --x-initial unique --x-assign unique
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VL_FLAGS += verilator.vlt
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# Enable Verilator multithreaded simulation
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#THREADS ?= $(shell python3 -c 'import multiprocessing as mp; print(max(1, mp.cpu_count() // 2))')
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@@ -70,7 +72,7 @@ PROJECT = libvortex.so
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all: $(PROJECT)
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$(PROJECT): $(SRCS)
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verilator --exe --cc $(TOP) $(RTL_INCLUDE) $(VL_FLAGS) $(SRCS) -CFLAGS '$(CFLAGS)' -LDFLAGS '$(LDFLAGS)' -o ../$(PROJECT)
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verilator --exe --cc $(TOP) --top-module $(TOP) $(RTL_INCLUDE) $(VL_FLAGS) $(SRCS) -CFLAGS '$(CFLAGS)' -LDFLAGS '$(LDFLAGS)' -o ../$(PROJECT)
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make -j -C obj_dir -f V$(TOP).mk
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clean:
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@@ -1,70 +0,0 @@
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#include "simulator.h"
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#include <iostream>
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#include <fstream>
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#include <iomanip>
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uint64_t timestamp = 0;
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double sc_time_stamp() {
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return timestamp;
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}
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Simulator::Simulator() {
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// force random values for unitialized signals
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const char* args[] = {"", "+verilator+rand+reset+2", "+verilator+seed+50"};
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Verilated::commandArgs(3, args);
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vortex_ = new Vvortex_afu_sim();
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#ifdef VCD_OUTPUT
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Verilated::traceEverOn(true);
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trace_ = new VerilatedVcdC;
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vortex_->trace(trace_, 99);
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trace_->open("trace.vcd");
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#endif
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}
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Simulator::~Simulator() {
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#ifdef VCD_OUTPUT
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trace_->close();
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#endif
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delete vortex_;
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}
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void Simulator::reset() {
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#ifndef NDEBUG
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std::cout << timestamp << ": [sim] reset()" << std::endl;
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#endif
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vortex_->reset = 1;
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this->step();
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vortex_->reset = 0;
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dram_rsp_vec_.clear();
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}
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void Simulator::step() {
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vortex_->clk = 0;
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this->eval();
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vortex_->clk = 1;
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this->eval();
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avs_driver();
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ccip_driver();
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}
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void Simulator::eval() {
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vortex_->eval();
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#ifdef VCD_OUTPUT
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trace_->dump(timestamp);
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#endif
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++timestamp;
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}
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void Simulator::avs_driver() {
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//--
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}
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void Simulator::ccip_driver() {
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//--
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}
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@@ -1,59 +0,0 @@
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#pragma once
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#include "Vvortex_afu_sim.h"
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#include "Vvortex_afu_sim__Syms.h"
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#include "verilated.h"
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#ifdef VCD_OUTPUT
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#include <verilated_vcd_c.h>
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#endif
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#include <VX_config.h>
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#include "ram.h"
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#include <ostream>
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#include <vector>
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#define ENABLE_DRAM_STALLS
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#define DRAM_LATENCY 100
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#define DRAM_RQ_SIZE 16
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#define DRAM_STALLS_MODULO 16
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typedef struct {
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int cycles_left;
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uint8_t *data;
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unsigned tag;
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} dram_req_t;
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class Simulator {
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public:
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Simulator();
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virtual ~Simulator();
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void reset();
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void step();
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int mmio_read(uint64_t addr, uint64_t* value);
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int mmio_write(uint64_t addr, uint64_t value);
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private:
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void eval();
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void avs_driver();
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void ccip_driver();
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std::vector<dram_req_t> dram_rsp_vec_;
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RAM ram_;
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Vvortex_afu_sim *vortex_;
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#ifdef VCD_OUTPUT
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VerilatedVcdC *trace_;
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#endif
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};
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9
driver/rtlsim/verilator.vlt
Normal file
9
driver/rtlsim/verilator.vlt
Normal file
@@ -0,0 +1,9 @@
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`verilator_config
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lint_off -rule BLKANDNBLK -file "../../hw/rtl/fp_cores/fpnew/*"
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lint_off -rule UNOPTFLAT -file "../../hw/rtl/fp_cores/fpnew/*"
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lint_off -rule WIDTH -file "../../hw/rtl/fp_cores/fpnew/*"
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lint_off -rule UNUSED -file "../../hw/rtl/fp_cores/fpnew/*"
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lint_off -rule LITENDIAN -file "../../hw/rtl/fp_cores/fpnew/*"
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lint_off -rule IMPORTSTAR -file "../../hw/rtl/fp_cores/fpnew/*"
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lint_off -rule PINCONNECTEMPTY -file "../../hw/rtl/fp_cores/fpnew/*"
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@@ -36,16 +36,16 @@ $(PROJECT): $(SRCS)
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$(CXX) $(CXXFLAGS) $^ $(LDFLAGS) -L../../stub -lvortex -o $@
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run-fpga: $(PROJECT)
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LD_LIBRARY_PATH=../../opae:$(LD_LIBRARY_PATH) ./$(PROJECT) -n 16
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LD_LIBRARY_PATH=../../opae:$(LD_LIBRARY_PATH) ./$(PROJECT) -n 64
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run-ase: $(PROJECT)
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ASE_LOG=0 LD_LIBRARY_PATH=../../opae/ase:$(LD_LIBRARY_PATH) ./$(PROJECT) -n 16
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ASE_LOG=0 LD_LIBRARY_PATH=../../opae/ase:$(LD_LIBRARY_PATH) ./$(PROJECT) -n 64
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run-rtlsim: $(PROJECT)
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LD_LIBRARY_PATH=../../rtlsim:$(LD_LIBRARY_PATH) ./$(PROJECT) -n 16
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LD_LIBRARY_PATH=../../rtlsim:$(LD_LIBRARY_PATH) ./$(PROJECT) -n 64
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run-simx: $(PROJECT)
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LD_LIBRARY_PATH=../../simx:$(LD_LIBRARY_PATH) ./$(PROJECT) -n 16
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LD_LIBRARY_PATH=../../simx:$(LD_LIBRARY_PATH) ./$(PROJECT) -n 64
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.depend: $(SRCS)
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$(CXX) $(CXXFLAGS) -MM $^ > .depend;
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BIN
driver/tests/demo/kernel.bin
Normal file → Executable file
BIN
driver/tests/demo/kernel.bin
Normal file → Executable file
Binary file not shown.
@@ -97,7 +97,7 @@ Disassembly of section .text:
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80000134: 0005006b 0x5006b
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80000138: 00002197 auipc gp,0x2
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8000013c: d3818193 addi gp,gp,-712 # 80001e70 <__global_pointer$>
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80000140: f14025f3 csrr a1,mhartid
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80000140: 022025f3 csrr a1,0x22
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80000144: 00a59593 slli a1,a1,0xa
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80000148: 02002673 csrr a2,0x20
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8000014c: 00261613 slli a2,a2,0x2
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@@ -145,7 +145,7 @@ Disassembly of section .text:
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800001ac: 00008067 ret
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800001b0 <vx_thread_gid>:
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800001b0: f1402573 csrr a0,mhartid
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800001b0: 02202573 csrr a0,0x22
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800001b4: 00008067 ret
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800001b8 <vx_core_id>:
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Binary file not shown.
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