From 31f906f9fd7913151c718c704fc22753acb3ec31 Mon Sep 17 00:00:00 2001 From: Blaise Tine Date: Thu, 16 Apr 2020 10:22:46 -0400 Subject: [PATCH] fixed all build warnings --- driver/rtlsim/Makefile | 7 +- hw/Makefile | 83 ++++++------ hw/modelsim/vortex_tb.v | 2 +- hw/rtl/VX_config.vh | 40 +++--- hw/rtl/VX_csr_pipe.v | 4 +- hw/rtl/VX_dmem_controller.v | 20 +-- hw/rtl/Vortex.v | 10 +- hw/rtl/Vortex_Cluster.v | 44 +++---- hw/rtl/Vortex_Socket.v | 40 +++--- hw/rtl/cache/VX_Cache_Bank.v | 4 +- hw/rtl/cache/VX_cache_bank_valid.v | 6 +- hw/rtl/cache/VX_cache_data.v | 4 +- hw/rtl/cache/VX_cache_data_per_index.v | 4 +- hw/rtl/cache/VX_d_cache.v | 6 +- hw/rtl/cache/VX_d_cache_encapsulate.v | 12 +- hw/rtl/cache/VX_d_cache_tb.v | 6 +- hw/rtl/cache/d_cache_test_bench.h | 16 +-- hw/rtl/generic_cache/VX_bank.v | 73 +++++------ hw/rtl/generic_cache/VX_cache.v | 122 +++++++++--------- hw/rtl/generic_cache/VX_cache_config.vh | 56 +------- .../VX_cache_core_req_bank_sel.v | 14 +- hw/rtl/generic_cache/VX_cache_dfq_queue.v | 37 +++--- hw/rtl/generic_cache/VX_cache_dram_req_arb.v | 44 +++---- hw/rtl/generic_cache/VX_cache_miss_resrv.v | 22 ++-- hw/rtl/generic_cache/VX_cache_req_queue.v | 88 ++++++------- hw/rtl/generic_cache/VX_cache_wb_sel_merge.v | 71 +++++----- .../VX_dcache_llv_resp_bank_sel.v | 26 ++-- hw/rtl/generic_cache/VX_fill_invalidator.v | 10 +- hw/rtl/generic_cache/VX_prefetcher.v | 4 +- hw/rtl/generic_cache/VX_snp_fwd_arb.v | 15 +-- hw/rtl/generic_cache/VX_tag_data_access.v | 10 +- hw/rtl/generic_cache/VX_tag_data_structure.v | 8 +- hw/rtl/interfaces/VX_dram_req_rsp_inter.v | 6 +- hw/rtl/interfaces/VX_gpu_dcache_req_inter.v | 22 ++-- hw/rtl/interfaces/VX_gpu_dcache_res_inter.v | 16 +-- hw/scripts/gen_config.py | 6 +- hw/scripts/gen_synth_configs.py | 4 +- hw/simulate/simulator.cpp | 4 +- hw/simulate/simulator.h | 4 +- hw/syn/yosys/diagram.ys | 5 + hw/syn/yosys/synthesis.ys | 27 ++++ simX/include/core.h | 4 +- 42 files changed, 497 insertions(+), 509 deletions(-) create mode 100644 hw/syn/yosys/diagram.ys create mode 100644 hw/syn/yosys/synthesis.ys diff --git a/driver/rtlsim/Makefile b/driver/rtlsim/Makefile index f6202085..6e092f0c 100644 --- a/driver/rtlsim/Makefile +++ b/driver/rtlsim/Makefile @@ -1,6 +1,5 @@ -# CFLAGS += -std=c++11 -O3 -Wall -Wextra -pedantic -Wfatal-errors -CFLAGS += -std=c++11 -O2 -Wall -Wextra -pedantic -Wfatal-errors -# CFLAGS += -std=c++11 -g -O0 -Wall -Wextra -pedantic -Wfatal-errors +CFLAGS += -std=c++11 -O2 -Wall -Wextra -Wfatal-errors +# CFLAGS += -std=c++11 -g -O0 -Wall -Wextra -Wfatal-errors USE_MULTICORE=1 @@ -28,8 +27,6 @@ RTL_INCLUDE = -I../../hw/rtl -I../../hw/rtl/interfaces -I../../hw/rtl/cache -I.. #THREADS ?= $(shell python3 -c 'import multiprocessing as mp; print(max(1, mp.cpu_count() // 2))') #VL_FLAGS += --threads $(THREADS) -VL_FLAGS += -Wno-UNDRIVEN --Wno-PINMISSING -Wno-STMTDLY -Wno-WIDTH -Wno-UNSIGNED -Wno-UNOPTFLAT -Wno-LITENDIAN -Wno-BLKLOOPINIT - # Debugigng #VL_FLAGS += --trace -DVL_DEBUG=1 #CFLAGS += -DVCD_OUTPUT diff --git a/hw/Makefile b/hw/Makefile index 5e20894d..8692902f 100644 --- a/hw/Makefile +++ b/hw/Makefile @@ -1,4 +1,4 @@ -all: RUNFILE +all: singlecore INCLUDE = -I./rtl/ -I./rtl/shared_memory -I./rtl/cache -I./rtl/generic_cache -I./rtl/generic_cache/interfaces -I./rtl/interfaces/ -I./rtl/pipe_regs/ -I./rtl/compat/ -I./rtl/simulate @@ -10,12 +10,6 @@ EXE += --exe ./simulate/testbench.cpp ./simulate/simulator.cpp VF += -compiler gcc --language 1800-2009 -WNO += -Wno-UNDRIVEN --Wno-PINMISSING -Wno-STMTDLY -Wno-WIDTH -Wno-UNSIGNED -Wno-UNOPTFLAT -Wno-LITENDIAN -# WNO= - -# LIGHTW= -LIGHTW += -Wno-UNOPTFLAT - # LIB=-LDFLAGS '-L/usr/local/systemc/' LIB += @@ -23,63 +17,70 @@ CF += -std=c++11 -fms-extensions DEB += --trace -DVL_DEBUG=1 -MAKECPP += (cd obj_dir && make -j -f VVortex.mk OPT='-DVL_DEBUG' VL_DEBUG=1 DVL_DEBUG=1) +MAKECPP_S += (cd obj_dir && make -j -f VVortex.mk) -MAKECPPRel += (cd obj_dir && make -j -f VVortex.mk) - -MAKEMULTICPP += (cd obj_dir && make -j -f VVortex_Socket.mk OPT='-DVL_DEBUG' VL_DEBUG=1 DVL_DEBUG=1) +MAKECPP_M += (cd obj_dir && make -j -f VVortex_Socket.mk) THREADS ?= $(shell python3 -c 'import multiprocessing as mp; print(max(1, mp.cpu_count() // 2))') .PHONY: build_config + build_config: ./scripts/gen_config.py --outv ./rtl/VX_user_config.vh --outc ./simulate/VX_config.h -# -LDFLAGS '-lsystemc' -VERILATOR: build_config - verilator $(VF) -cc $(SINGLE_CORE) $(INCLUDE) $(EXE) $(LIB) -CFLAGS '$(CF)' $(LIGHTW) +gen-singlecore: build_config + verilator $(VF) -cc $(SINGLE_CORE) $(INCLUDE) $(EXE) $(LIB) -CFLAGS '$(CF)' -VERILATORnoWarnings: build_config - verilator $(VF) -cc $(SINGLE_CORE) $(INCLUDE) $(EXE) $(LIB) -CFLAGS '$(CF)' $(WNO) $(DEB) +gen-singlecore-t: build_config + verilator $(VF) -cc $(SINGLE_CORE) $(INCLUDE) $(EXE) $(LIB) -CFLAGS '$(CF) -O3' --threads $(THREADS) -VERILATORnoWarningsRel: build_config - verilator $(VF) -cc $(SINGLE_CORE) $(INCLUDE) $(EXE) $(LIB) -CFLAGS '$(CF) -O3 -DVL_THREADED' $(WNO) --threads $(THREADS) +gen-singlecore-d: build_config + verilator $(VF) -cc $(SINGLE_CORE) $(INCLUDE) $(EXE) $(LIB) -CFLAGS '$(CF) -DVCD_OUTPUT' $(DEB) -VERILATORMULTInoWarnings: build_config - verilator $(VF) -cc $(MULTI_CORE) $(INCLUDE) $(EXE) $(LIB) -CFLAGS '$(CF) -DUSE_MULTICORE' $(WNO) $(DEB) +gen-multicore: build_config + verilator $(VF) -cc $(MULTI_CORE) $(INCLUDE) $(EXE) $(LIB) -CFLAGS '$(CF) -DUSE_MULTICORE' + +gen-multicore-t: build_config + verilator $(VF) -cc $(MULTI_CORE) $(INCLUDE) $(EXE) $(LIB) -CFLAGS '$(CF) -DUSE_MULTICORE -O3' --threads $(THREADS) -compdebug: build_config - verilator_bin_dbg $(VF) -cc $(SINGLE_CORE) $(INCLUDE) $(EXE) $(LIB) -CFLAGS '$(CF) -DVCD_OUTPUT -DVL_DEBUG' $(WNO) $(DEB) +gen-multicore-d: build_config + verilator $(VF) -cc $(MULTI_CORE) $(INCLUDE) $(EXE) $(LIB) -CFLAGS '$(CF) -DVCD_OUTPUT -DUSE_MULTICORE' $(DEB) -compdebugmulti: build_config - verilator_bin_dbg $(VF) -cc $(MULTI_CORE) $(INCLUDE) $(EXE) $(LIB) -CFLAGS '$(CF) -DUSE_MULTICORE -DVCD_OUTPUT -DVL_DEBUG' $(WNO) $(DEB) +singlecore: gen-singlecore + (cd obj_dir && make -j -f VVortex.mk) -RUNFILE: VERILATOR - $(MAKECPP) +singlecore-t: gen-singlecore-t + (cd obj_dir && make -j -f VVortex.mk) -debug: compdebug - $(MAKECPP) +singlecore-d: gen-singlecore-d + (cd obj_dir && make -j -f VVortex.mk) -w: VERILATORnoWarnings - $(MAKECPP) +multicore: gen-multicore + (cd obj_dir && make -j -f VVortex_Socket.mk) -wRel: VERILATORnoWarningsRel - $(MAKECPPRel) +multicore-t: gen-multicore-t + (cd obj_dir && make -j -f VVortex_Socket.mk) -multicore: VERILATORMULTInoWarnings - $(MAKEMULTICPP) +multicore-d: gen-multicore-d + (cd obj_dir && make -j -f VVortex_Socket.mk) -dmulticore: compdebugmulti - $(MAKEMULTICPP) - -run: w +run: singlecore (cd obj_dir && ./VVortex) -run-multicore: multicore +run-d: singlecore-d + (cd obj_dir && ./VVortex) + +run-t: singlecore-t + (cd obj_dir && ./VVortex) + +run-m: multicore (cd obj_dir && ./VVortex_Socket) -runRel: wRel - (cd obj_dir && ./VVortex) +run-md: multicore-d + (cd obj_dir && ./VVortex_Socket) + +run-mt: multicore-t + (cd obj_dir && ./VVortex_Socket) clean: rm -rf obj_dir \ No newline at end of file diff --git a/hw/modelsim/vortex_tb.v b/hw/modelsim/vortex_tb.v index 93bcdcc0..64dfef13 100644 --- a/hw/modelsim/vortex_tb.v +++ b/hw/modelsim/vortex_tb.v @@ -1,7 +1,7 @@ `include "../VX_define.vh" -//`define NUMBER_BANKS 8 +//`define NUM_BANKS 8 //`define NUM_WORDS_PER_BLOCK 4 `define ARM_UD_MODEL diff --git a/hw/rtl/VX_config.vh b/hw/rtl/VX_config.vh index e6dc8366..2ed92322 100644 --- a/hw/rtl/VX_config.vh +++ b/hw/rtl/VX_config.vh @@ -45,8 +45,8 @@ `define DBANK_LINE_SIZE (`DBANK_LINE_SIZE_BYTES * 8) // Number of banks {1, 2, 4, 8,...} -`ifndef DNUMBER_BANKS -`define DNUMBER_BANKS 8 +`ifndef DNUM_BANKS +`define DNUM_BANKS 8 `endif // Size of a word in bytes @@ -55,8 +55,8 @@ `endif // Number of Word requests per cycle {1, 2, 4, 8, ...} -`ifndef DNUMBER_REQUESTS -`define DNUMBER_REQUESTS `NUM_THREADS +`ifndef DNUM_REQUESTS +`define DNUM_REQUESTS `NUM_THREADS `endif // Number of cycles to complete stage 1 (read from memory) @@ -141,8 +141,8 @@ `endif // Number of banks {1, 2, 4, 8,...} -`ifndef INUMBER_BANKS -`define INUMBER_BANKS 8 +`ifndef INUM_BANKS +`define INUM_BANKS 8 `endif // Size of a word in bytes @@ -151,8 +151,8 @@ `endif // Number of Word requests per cycle {1, 2, 4, 8, ...} -`ifndef INUMBER_REQUESTS -`define INUMBER_REQUESTS 1 +`ifndef INUM_REQUESTS +`define INUM_REQUESTS 1 `endif // Number of cycles to complete stage 1 (read from memory) @@ -237,8 +237,8 @@ `endif // Number of banks {1, 2, 4, 8,...} -`ifndef SNUMBER_BANKS -`define SNUMBER_BANKS 8 +`ifndef SNUM_BANKS +`define SNUM_BANKS 8 `endif // Size of a word in bytes @@ -247,8 +247,8 @@ `endif // Number of Word requests per cycle {1, 2, 4, 8, ...} -`ifndef SNUMBER_REQUESTS -`define SNUMBER_REQUESTS `NUM_THREADS +`ifndef SNUM_REQUESTS +`define SNUM_REQUESTS `NUM_THREADS `endif // Number of cycles to complete stage 1 (read from memory) @@ -333,8 +333,8 @@ `endif // Number of banks {1, 2, 4, 8,...} -`ifndef L2NUMBER_BANKS -`define L2NUMBER_BANKS 8 +`ifndef L2NUM_BANKS +`define L2NUM_BANKS 8 `endif // Size of a word in bytes @@ -343,8 +343,8 @@ `endif // Number of Word requests per cycle {1, 2, 4, 8, ...} -`ifndef L2NUMBER_REQUESTS -`define L2NUMBER_REQUESTS (2*`NUM_CORES_PER_CLUSTER) +`ifndef L2NUM_REQUESTS +`define L2NUM_REQUESTS (2*`NUM_CORES_PER_CLUSTER) `endif // Number of cycles to complete stage 1 (read from memory) @@ -429,8 +429,8 @@ `endif // Number of banks {1, 2, 4, 8,...} -`ifndef L3NUMBER_BANKS -`define L3NUMBER_BANKS 8 +`ifndef L3NUM_BANKS +`define L3NUM_BANKS 8 `endif // Size of a word in bytes @@ -439,8 +439,8 @@ `endif // Number of Word requests per cycle {1, 2, 4, 8, ...} -`ifndef L3NUMBER_REQUESTS -`define L3NUMBER_REQUESTS (`NUM_CLUSTERS) +`ifndef L3NUM_REQUESTS +`define L3NUM_REQUESTS (`NUM_CLUSTERS) `endif // Number of cycles to complete stage 1 (read from memory) diff --git a/hw/rtl/VX_csr_pipe.v b/hw/rtl/VX_csr_pipe.v index f2a84da9..6434e671 100644 --- a/hw/rtl/VX_csr_pipe.v +++ b/hw/rtl/VX_csr_pipe.v @@ -84,8 +84,8 @@ module VX_csr_pipe genvar cur_tw; for (cur_tw = 0; cur_tw < `NUM_THREADS; cur_tw = cur_tw + 1) begin - assign warp_ids[cur_tw] = warp_num_s2; - assign warp_idz[cur_tw] = 32'(warp_num_s2 + (CORE_ID * `NUM_WARPS)); + assign warp_ids[cur_tw] = 32'(warp_num_s2); + assign warp_idz[cur_tw] = 32'(warp_num_s2) + (CORE_ID * `NUM_WARPS); end genvar cur_v; diff --git a/hw/rtl/VX_dmem_controller.v b/hw/rtl/VX_dmem_controller.v index 25304e6b..8e8c4adf 100644 --- a/hw/rtl/VX_dmem_controller.v +++ b/hw/rtl/VX_dmem_controller.v @@ -24,12 +24,12 @@ module VX_dmem_controller ( ); - VX_gpu_dcache_res_inter #(.NUMBER_REQUESTS(`DNUMBER_REQUESTS)) VX_dcache_rsp_smem(); - VX_gpu_dcache_req_inter #(.NUMBER_REQUESTS(`DNUMBER_REQUESTS)) VX_dcache_req_smem(); + VX_gpu_dcache_res_inter #(.NUM_REQUESTS(`DNUM_REQUESTS)) VX_dcache_rsp_smem(); + VX_gpu_dcache_req_inter #(.NUM_REQUESTS(`DNUM_REQUESTS)) VX_dcache_req_smem(); - VX_gpu_dcache_res_inter #(.NUMBER_REQUESTS(`DNUMBER_REQUESTS)) VX_dcache_rsp_dcache(); - VX_gpu_dcache_req_inter #(.NUMBER_REQUESTS(`DNUMBER_REQUESTS)) VX_dcache_req_dcache(); + VX_gpu_dcache_res_inter #(.NUM_REQUESTS(`DNUM_REQUESTS)) VX_dcache_rsp_dcache(); + VX_gpu_dcache_req_inter #(.NUM_REQUESTS(`DNUM_REQUESTS)) VX_dcache_req_dcache(); wire to_shm = VX_dcache_req.core_req_addr[0][31:24] == 8'hFF; @@ -81,9 +81,9 @@ module VX_dmem_controller ( VX_cache #( .CACHE_SIZE_BYTES (`SCACHE_SIZE_BYTES), .BANK_LINE_SIZE_BYTES (`SBANK_LINE_SIZE_BYTES), - .NUMBER_BANKS (`SNUMBER_BANKS), + .NUM_BANKS (`SNUM_BANKS), .WORD_SIZE_BYTES (`SWORD_SIZE_BYTES), - .NUMBER_REQUESTS (`SNUMBER_REQUESTS), + .NUM_REQUESTS (`SNUM_REQUESTS), .STAGE_1_CYCLES (`SSTAGE_1_CYCLES), .FUNC_ID (`SFUNC_ID), .REQQ_SIZE (`SREQQ_SIZE), @@ -166,9 +166,9 @@ module VX_dmem_controller ( VX_cache #( .CACHE_SIZE_BYTES (`DCACHE_SIZE_BYTES), .BANK_LINE_SIZE_BYTES (`DBANK_LINE_SIZE_BYTES), - .NUMBER_BANKS (`DNUMBER_BANKS), + .NUM_BANKS (`DNUM_BANKS), .WORD_SIZE_BYTES (`DWORD_SIZE_BYTES), - .NUMBER_REQUESTS (`DNUMBER_REQUESTS), + .NUM_REQUESTS (`DNUM_REQUESTS), .STAGE_1_CYCLES (`DSTAGE_1_CYCLES), .FUNC_ID (`DFUNC_ID), .REQQ_SIZE (`DREQQ_SIZE), @@ -254,9 +254,9 @@ module VX_dmem_controller ( VX_cache #( .CACHE_SIZE_BYTES (`ICACHE_SIZE_BYTES), .BANK_LINE_SIZE_BYTES (`IBANK_LINE_SIZE_BYTES), - .NUMBER_BANKS (`INUMBER_BANKS), + .NUM_BANKS (`INUM_BANKS), .WORD_SIZE_BYTES (`IWORD_SIZE_BYTES), - .NUMBER_REQUESTS (`INUMBER_REQUESTS), + .NUM_REQUESTS (`INUM_REQUESTS), .STAGE_1_CYCLES (`ISTAGE_1_CYCLES), .FUNC_ID (`IFUNC_ID), .REQQ_SIZE (`IREQQ_SIZE), diff --git a/hw/rtl/Vortex.v b/hw/rtl/Vortex.v index f63dba0b..d515952b 100644 --- a/hw/rtl/Vortex.v +++ b/hw/rtl/Vortex.v @@ -122,9 +122,9 @@ module Vortex wire schedule_delay; // Dcache Interface - VX_gpu_dcache_res_inter #(.NUMBER_REQUESTS(`DNUMBER_REQUESTS)) VX_dcache_rsp(); - VX_gpu_dcache_req_inter #(.NUMBER_REQUESTS(`DNUMBER_REQUESTS)) VX_dcache_req(); - VX_gpu_dcache_req_inter #(.NUMBER_REQUESTS(`DNUMBER_REQUESTS)) VX_dcache_req_qual(); + VX_gpu_dcache_res_inter #(.NUM_REQUESTS(`DNUM_REQUESTS)) VX_dcache_rsp(); + VX_gpu_dcache_req_inter #(.NUM_REQUESTS(`DNUM_REQUESTS)) VX_dcache_req(); + VX_gpu_dcache_req_inter #(.NUM_REQUESTS(`DNUM_REQUESTS)) VX_dcache_req_qual(); VX_gpu_dcache_dram_req_inter #(.BANK_LINE_WORDS(`DBANK_LINE_WORDS)) VX_gpu_dcache_dram_req(); VX_gpu_dcache_dram_res_inter #(.BANK_LINE_WORDS(`DBANK_LINE_WORDS)) VX_gpu_dcache_dram_res(); @@ -172,8 +172,8 @@ module Vortex assign VX_dcache_req_qual.core_no_wb_slot = VX_dcache_req.core_no_wb_slot; - VX_gpu_dcache_res_inter #(.NUMBER_REQUESTS(`INUMBER_REQUESTS)) VX_icache_rsp(); - VX_gpu_dcache_req_inter #(.NUMBER_REQUESTS(`INUMBER_REQUESTS)) VX_icache_req(); + VX_gpu_dcache_res_inter #(.NUM_REQUESTS(`INUM_REQUESTS)) VX_icache_rsp(); + VX_gpu_dcache_req_inter #(.NUM_REQUESTS(`INUM_REQUESTS)) VX_icache_req(); VX_gpu_dcache_dram_req_inter #(.BANK_LINE_WORDS(`IBANK_LINE_WORDS)) VX_gpu_icache_dram_req(); VX_gpu_dcache_dram_res_inter #(.BANK_LINE_WORDS(`IBANK_LINE_WORDS)) VX_gpu_icache_dram_res(); diff --git a/hw/rtl/Vortex_Cluster.v b/hw/rtl/Vortex_Cluster.v index 86598907..afaae66b 100644 --- a/hw/rtl/Vortex_Cluster.v +++ b/hw/rtl/Vortex_Cluster.v @@ -43,14 +43,14 @@ module Vortex_Cluster wire[`NUM_CORES_PER_CLUSTER-1:0] per_core_dram_req_read; wire[`NUM_CORES_PER_CLUSTER-1:0] [31:0] per_core_dram_req_addr; wire[`NUM_CORES_PER_CLUSTER-1:0] [31:0] per_core_dram_req_size; - wire[`NUM_CORES_PER_CLUSTER-1:0][`DBANK_LINE_WORDS-1:0][31:0] per_core_dram_req_data; + wire[`NUM_CORES_PER_CLUSTER-1:0][`DBANK_LINE_WORDS-1:0][31:0] per_core_dram_req_data; wire[`NUM_CORES_PER_CLUSTER-1:0] [31:0] per_core_dram_expected_lat; // DRAM Dcache Res wire[`NUM_CORES_PER_CLUSTER-1:0] per_core_dram_fill_accept; wire[`NUM_CORES_PER_CLUSTER-1:0] per_core_dram_fill_rsp; wire[`NUM_CORES_PER_CLUSTER-1:0] [31:0] per_core_dram_fill_rsp_addr; - wire[`NUM_CORES_PER_CLUSTER-1:0][`DBANK_LINE_WORDS-1:0][31:0] per_core_dram_fill_rsp_data; + wire[`NUM_CORES_PER_CLUSTER-1:0][`DBANK_LINE_WORDS-1:0][31:0] per_core_dram_fill_rsp_data; // DRAM Icache Req wire[`NUM_CORES_PER_CLUSTER-1:0] per_core_I_dram_req; @@ -58,14 +58,14 @@ module Vortex_Cluster wire[`NUM_CORES_PER_CLUSTER-1:0] per_core_I_dram_req_read; wire[`NUM_CORES_PER_CLUSTER-1:0] [31:0] per_core_I_dram_req_addr; wire[`NUM_CORES_PER_CLUSTER-1:0] [31:0] per_core_I_dram_req_size; - wire[`NUM_CORES_PER_CLUSTER-1:0][`IBANK_LINE_WORDS-1:0][31:0] per_core_I_dram_req_data; + wire[`NUM_CORES_PER_CLUSTER-1:0][`IBANK_LINE_WORDS-1:0][31:0] per_core_I_dram_req_data; wire[`NUM_CORES_PER_CLUSTER-1:0] [31:0] per_core_I_dram_expected_lat; // DRAM Icache Res wire[`NUM_CORES_PER_CLUSTER-1:0] per_core_I_dram_fill_accept; wire[`NUM_CORES_PER_CLUSTER-1:0] per_core_I_dram_fill_rsp; wire[`NUM_CORES_PER_CLUSTER-1:0] [31:0] per_core_I_dram_fill_rsp_addr; - wire[`NUM_CORES_PER_CLUSTER-1:0][`IBANK_LINE_WORDS-1:0][31:0] per_core_I_dram_fill_rsp_data; + wire[`NUM_CORES_PER_CLUSTER-1:0][`IBANK_LINE_WORDS-1:0][31:0] per_core_I_dram_fill_rsp_data; // Out ebreak wire[`NUM_CORES_PER_CLUSTER-1:0] per_core_out_ebreak; @@ -73,10 +73,10 @@ module Vortex_Cluster wire[`NUM_CORES_PER_CLUSTER-1:0] per_core_io_valid; wire[`NUM_CORES_PER_CLUSTER-1:0][31:0] per_core_io_data; - wire l2c_core_accept; + wire l2c_core_accept; - wire snp_fwd; - wire[31:0] snp_fwd_addr; + wire snp_fwd; + wire[31:0] snp_fwd_addr; wire[`NUM_CORES_PER_CLUSTER-1:0] snp_fwd_delay; assign out_ebreak = (&per_core_out_ebreak); @@ -137,21 +137,21 @@ module Vortex_Cluster endgenerate //////////////////// L2 Cache //////////////////// - wire[`L2NUMBER_REQUESTS-1:0] l2c_core_req; - wire[`L2NUMBER_REQUESTS-1:0][2:0] l2c_core_req_mem_write; - wire[`L2NUMBER_REQUESTS-1:0][2:0] l2c_core_req_mem_read; - wire[`L2NUMBER_REQUESTS-1:0][31:0] l2c_core_req_addr; - wire[`L2NUMBER_REQUESTS-1:0][`IBANK_LINE_WORDS-1:0][31:0] l2c_core_req_data; - wire[`L2NUMBER_REQUESTS-1:0][1:0] l2c_core_req_wb; + wire[`L2NUM_REQUESTS-1:0] l2c_core_req; + wire[`L2NUM_REQUESTS-1:0][2:0] l2c_core_req_mem_write; + wire[`L2NUM_REQUESTS-1:0][2:0] l2c_core_req_mem_read; + wire[`L2NUM_REQUESTS-1:0][31:0] l2c_core_req_addr; + wire[`L2NUM_REQUESTS-1:0][`IBANK_LINE_WORDS-1:0][31:0] l2c_core_req_data; + wire[`L2NUM_REQUESTS-1:0][1:0] l2c_core_req_wb; - wire[`L2NUMBER_REQUESTS-1:0] l2c_core_no_wb_slot; + wire[`L2NUM_REQUESTS-1:0] l2c_core_no_wb_slot; - wire[`L2NUMBER_REQUESTS-1:0] l2c_wb; - wire[`L2NUMBER_REQUESTS-1:0] [31:0] l2c_wb_addr; - wire[`L2NUMBER_REQUESTS-1:0][`IBANK_LINE_WORDS-1:0][31:0] l2c_wb_data; + wire[`L2NUM_REQUESTS-1:0] l2c_wb; + wire[`L2NUM_REQUESTS-1:0] [31:0] l2c_wb_addr; + wire[`L2NUM_REQUESTS-1:0][`IBANK_LINE_WORDS-1:0][31:0] l2c_wb_data; - wire[`DBANK_LINE_WORDS-1:0][31:0] dram_req_data_port; - wire[`DBANK_LINE_WORDS-1:0][31:0] dram_fill_rsp_data_port; + wire[`DBANK_LINE_WORDS-1:0][31:0] dram_req_data_port; + wire[`DBANK_LINE_WORDS-1:0][31:0] dram_fill_rsp_data_port; genvar llb_index; generate @@ -163,7 +163,7 @@ module Vortex_Cluster genvar l2c_curr_core; generate - for (l2c_curr_core = 0; l2c_curr_core < `L2NUMBER_REQUESTS; l2c_curr_core=l2c_curr_core+2) begin + for (l2c_curr_core = 0; l2c_curr_core < `L2NUM_REQUESTS; l2c_curr_core=l2c_curr_core+2) begin // Core Request assign l2c_core_req [l2c_curr_core] = per_core_dram_req [(l2c_curr_core/2)]; assign l2c_core_req [l2c_curr_core+1] = per_core_I_dram_req[(l2c_curr_core/2)]; @@ -204,9 +204,9 @@ module Vortex_Cluster VX_cache #( .CACHE_SIZE_BYTES (`L2CACHE_SIZE_BYTES), .BANK_LINE_SIZE_BYTES (`L2BANK_LINE_SIZE_BYTES), - .NUMBER_BANKS (`L2NUMBER_BANKS), + .NUM_BANKS (`L2NUM_BANKS), .WORD_SIZE_BYTES (`L2WORD_SIZE_BYTES), - .NUMBER_REQUESTS (`L2NUMBER_REQUESTS), + .NUM_REQUESTS (`L2NUM_REQUESTS), .STAGE_1_CYCLES (`L2STAGE_1_CYCLES), .FUNC_ID (`L2FUNC_ID), .REQQ_SIZE (`L2REQQ_SIZE), diff --git a/hw/rtl/Vortex_Socket.v b/hw/rtl/Vortex_Socket.v index 87d1cb34..5cfec2ac 100644 --- a/hw/rtl/Vortex_Socket.v +++ b/hw/rtl/Vortex_Socket.v @@ -93,17 +93,17 @@ module Vortex_Socket ( wire[`NUM_CLUSTERS-1:0] [31:0] per_cluster_dram_req_addr; wire[`NUM_CLUSTERS-1:0] [31:0] per_cluster_dram_req_size; wire[`NUM_CLUSTERS-1:0] [31:0] per_cluster_dram_expected_lat; - wire[`NUM_CLUSTERS-1:0][`DBANK_LINE_WORDS-1:0][31:0] per_cluster_dram_req_data; - wire[31:0] per_cluster_dram_req_data_up[`NUM_CLUSTERS-1:0][`DBANK_LINE_WORDS-1:0]; + wire[`NUM_CLUSTERS-1:0][`DBANK_LINE_WORDS-1:0][31:0] per_cluster_dram_req_data; + wire[31:0] per_cluster_dram_req_data_up[`NUM_CLUSTERS-1:0][`DBANK_LINE_WORDS-1:0]; - wire l3c_core_accept; + wire l3c_core_accept; // // DRAM Dcache Res wire[`NUM_CLUSTERS-1:0] per_cluster_dram_fill_accept; wire[`NUM_CLUSTERS-1:0] per_cluster_dram_fill_rsp; wire[`NUM_CLUSTERS-1:0] [31:0] per_cluster_dram_fill_rsp_addr; - wire[`NUM_CLUSTERS-1:0][`DBANK_LINE_WORDS-1:0][31:0] per_cluster_dram_fill_rsp_data; - wire[31:0] per_cluster_dram_fill_rsp_data_up[`NUM_CLUSTERS-1:0][`DBANK_LINE_WORDS-1:0]; + wire[`NUM_CLUSTERS-1:0][`DBANK_LINE_WORDS-1:0][31:0] per_cluster_dram_fill_rsp_data; + wire[31:0] per_cluster_dram_fill_rsp_data_up[`NUM_CLUSTERS-1:0][`DBANK_LINE_WORDS-1:0]; wire[`NUM_CLUSTERS-1:0][`NUM_CORES_PER_CLUSTER-1:0] per_cluster_io_valid; wire[`NUM_CLUSTERS-1:0][`NUM_CORES_PER_CLUSTER-1:0][31:0] per_cluster_io_data; @@ -155,22 +155,22 @@ module Vortex_Socket ( end //////////////////// L3 Cache //////////////////// - wire[`L3NUMBER_REQUESTS-1:0] l3c_core_req; - wire[`L3NUMBER_REQUESTS-1:0][2:0] l3c_core_req_mem_write; - wire[`L3NUMBER_REQUESTS-1:0][2:0] l3c_core_req_mem_read; - wire[`L3NUMBER_REQUESTS-1:0][31:0] l3c_core_req_addr; - wire[`L3NUMBER_REQUESTS-1:0][`IBANK_LINE_WORDS-1:0][31:0] l3c_core_req_data; - wire[`L3NUMBER_REQUESTS-1:0][1:0] l3c_core_req_wb; + wire[`L3NUM_REQUESTS-1:0] l3c_core_req; + wire[`L3NUM_REQUESTS-1:0][2:0] l3c_core_req_mem_write; + wire[`L3NUM_REQUESTS-1:0][2:0] l3c_core_req_mem_read; + wire[`L3NUM_REQUESTS-1:0][31:0] l3c_core_req_addr; + wire[`L3NUM_REQUESTS-1:0][`IBANK_LINE_WORDS-1:0][31:0] l3c_core_req_data; + wire[`L3NUM_REQUESTS-1:0][1:0] l3c_core_req_wb; - wire[`L3NUMBER_REQUESTS-1:0] l3c_core_no_wb_slot; + wire[`L3NUM_REQUESTS-1:0] l3c_core_no_wb_slot; - wire[`L3NUMBER_REQUESTS-1:0] l3c_wb; - wire[`L3NUMBER_REQUESTS-1:0] [31:0] l3c_wb_addr; - wire[`L3NUMBER_REQUESTS-1:0][`IBANK_LINE_WORDS-1:0][31:0] l3c_wb_data; + wire[`L3NUM_REQUESTS-1:0] l3c_wb; + wire[`L3NUM_REQUESTS-1:0] [31:0] l3c_wb_addr; + wire[`L3NUM_REQUESTS-1:0][`IBANK_LINE_WORDS-1:0][31:0] l3c_wb_data; - wire[`DBANK_LINE_WORDS-1:0][31:0] dram_req_data_port; - wire[`DBANK_LINE_WORDS-1:0][31:0] dram_fill_rsp_data_port; + wire[`DBANK_LINE_WORDS-1:0][31:0] dram_req_data_port; + wire[`DBANK_LINE_WORDS-1:0][31:0] dram_fill_rsp_data_port; genvar llb_index; for (llb_index = 0; llb_index < `DBANK_LINE_WORDS; llb_index=llb_index+1) begin @@ -180,7 +180,7 @@ module Vortex_Socket ( // genvar l3c_curr_cluster; - for (l3c_curr_cluster = 0; l3c_curr_cluster < `L3NUMBER_REQUESTS; l3c_curr_cluster=l3c_curr_cluster+1) begin + for (l3c_curr_cluster = 0; l3c_curr_cluster < `L3NUM_REQUESTS; l3c_curr_cluster=l3c_curr_cluster+1) begin // Core Request assign l3c_core_req [l3c_curr_cluster] = per_cluster_dram_req [l3c_curr_cluster]; @@ -208,9 +208,9 @@ module Vortex_Socket ( VX_cache #( .CACHE_SIZE_BYTES (`L3CACHE_SIZE_BYTES), .BANK_LINE_SIZE_BYTES (`L3BANK_LINE_SIZE_BYTES), - .NUMBER_BANKS (`L3NUMBER_BANKS), + .NUM_BANKS (`L3NUM_BANKS), .WORD_SIZE_BYTES (`L3WORD_SIZE_BYTES), - .NUMBER_REQUESTS (`L3NUMBER_REQUESTS), + .NUM_REQUESTS (`L3NUM_REQUESTS), .STAGE_1_CYCLES (`L3STAGE_1_CYCLES), .FUNC_ID (`L2FUNC_ID), .REQQ_SIZE (`L3REQQ_SIZE), diff --git a/hw/rtl/cache/VX_Cache_Bank.v b/hw/rtl/cache/VX_Cache_Bank.v index 669e40e5..aaf33954 100644 --- a/hw/rtl/cache/VX_Cache_Bank.v +++ b/hw/rtl/cache/VX_Cache_Bank.v @@ -57,10 +57,10 @@ module VX_Cache_Bank evicted_way ); - // localparam NUMBER_BANKS = `CACHE_BANKS; + // localparam NUM_BANKS = `CACHE_BANKS; // localparam CACHE_BLOCK_PER_BANK = (`CACHE_BLOCK / `CACHE_BANKS); // localparam NUM_WORDS_PER_BLOCK = `CACHE_BLOCK / (`CACHE_BANKS*4); - // localparam NUMBER_INDEXES = `NUM_IND; + // localparam NUM_INDEXES = `NUM_IND; localparam CACHE_IDLE = 0; // Idle localparam SEND_MEM_REQ = 1; // Write back this block into memory diff --git a/hw/rtl/cache/VX_cache_bank_valid.v b/hw/rtl/cache/VX_cache_bank_valid.v index f9befcf2..ff0b95f1 100644 --- a/hw/rtl/cache/VX_cache_bank_valid.v +++ b/hw/rtl/cache/VX_cache_bank_valid.v @@ -2,14 +2,14 @@ module VX_cache_bank_valid #( - parameter NUMBER_BANKS = 8, + parameter NUM_BANKS = 8, parameter LOG_NUM_BANKS = 3, parameter NUM_REQ = 1 ) ( input wire [NUM_REQ-1:0] i_p_valid, input wire [NUM_REQ-1:0][31:0] i_p_addr, - output reg [NUMBER_BANKS - 1 : 0][NUM_REQ-1:0] thread_track_banks + output reg [NUM_BANKS - 1 : 0][NUM_REQ-1:0] thread_track_banks ); generate @@ -18,7 +18,7 @@ module VX_cache_bank_valid thread_track_banks = 0; for (t_id = 0; t_id < NUM_REQ; t_id = t_id + 1) begin - if (NUMBER_BANKS != 1) begin + if (NUM_BANKS != 1) begin thread_track_banks[i_p_addr[t_id][2+LOG_NUM_BANKS-1:2]][t_id] = i_p_valid[t_id]; end else begin thread_track_banks[0][t_id] = i_p_valid[t_id]; diff --git a/hw/rtl/cache/VX_cache_data.v b/hw/rtl/cache/VX_cache_data.v index dc2e7594..0046070c 100644 --- a/hw/rtl/cache/VX_cache_data.v +++ b/hw/rtl/cache/VX_cache_data.v @@ -46,10 +46,10 @@ module VX_cache_data ); - //localparam NUMBER_BANKS = CACHE_BANKS; + //localparam NUM_BANKS = CACHE_BANKS; //localparam CACHE_BLOCK_PER_BANK = (CACHE_BLOCK / CACHE_BANKS); // localparam NUM_WORDS_PER_BLOCK = CACHE_BLOCK / (CACHE_BANKS*4); - //localparam NUMBER_INDEXES = NUM_IND; + //localparam NUM_INDEXES = NUM_IND; wire currently_writing = (|we); wire update_dirty = ((!dirty_use) && currently_writing) || (evict); diff --git a/hw/rtl/cache/VX_cache_data_per_index.v b/hw/rtl/cache/VX_cache_data_per_index.v index 11e7b99b..0f824edc 100644 --- a/hw/rtl/cache/VX_cache_data_per_index.v +++ b/hw/rtl/cache/VX_cache_data_per_index.v @@ -33,10 +33,10 @@ module VX_cache_data_per_index output wire dirty_use ); - //localparam NUMBER_BANKS = CACHE_BANKS; + //localparam NUM_BANKS = CACHE_BANKS; //localparam CACHE_BLOCK_PER_BANK = (CACHE_BLOCK / CACHE_BANKS); // localparam NUM_WORDS_PER_BLOCK = CACHE_BLOCK / (CACHE_BANKS*4); - //localparam NUMBER_INDEXES = `DCACHE_NUM_IND; + //localparam NUM_INDEXES = `DCACHE_NUM_IND; wire [CACHE_WAYS-1:0][TAG_SIZE_END:TAG_SIZE_START] tag_use_per_way; wire [CACHE_WAYS-1:0][NUM_WORDS_PER_BLOCK-1:0][31:0] data_use_per_way; diff --git a/hw/rtl/cache/VX_d_cache.v b/hw/rtl/cache/VX_d_cache.v index 5b305571..85fb1427 100644 --- a/hw/rtl/cache/VX_d_cache.v +++ b/hw/rtl/cache/VX_d_cache.v @@ -66,7 +66,7 @@ module VX_d_cache i_m_ready ); - //parameter NUMBER_BANKS = `CACHE_BANKS; + //parameter NUM_BANKS = `CACHE_BANKS; //localparam NUM_WORDS_PER_BLOCK = `CACHE_BLOCK / (`CACHE_BANKS*4); //localparam CACHE_BLOCK_PER_BANK = (`CACHE_BLOCK / `CACHE_BANKS); @@ -148,7 +148,7 @@ module VX_d_cache - VX_cache_bank_valid #(.NUMBER_BANKS (CACHE_BANKS), + VX_cache_bank_valid #(.NUM_BANKS (CACHE_BANKS), .LOG_NUM_BANKS (LOG_NUM_BANKS), .NUM_REQ (NUM_REQ)) multip_banks( .i_p_valid (use_valid), @@ -261,7 +261,7 @@ module VX_d_cache miss_addr <= 0; // evict_addr <= 0; // threads_serviced_Qual = 0; - // for (init_b = 0; init_b < NUMBER_BANKS; init_b=init_b+1) + // for (init_b = 0; init_b < NUM_BANKS; init_b=init_b+1) // begin // debug_hit_per_bank_mask[init_b] <= 0; // end diff --git a/hw/rtl/cache/VX_d_cache_encapsulate.v b/hw/rtl/cache/VX_d_cache_encapsulate.v index 1d7413f5..98ce64a4 100644 --- a/hw/rtl/cache/VX_d_cache_encapsulate.v +++ b/hw/rtl/cache/VX_d_cache_encapsulate.v @@ -25,7 +25,7 @@ module VX_d_cache_encapsulate ( i_m_ready ); - parameter NUMBER_BANKS = 8; + parameter NUM_BANKS = 8; @@ -39,7 +39,7 @@ module VX_d_cache_encapsulate ( input wire [31:0] i_p_writedata[`NUM_THREADS-1:0]; input wire i_p_read_or_write; - input wire [31:0] i_m_readdata[NUMBER_BANKS - 1:0][`NUM_WORDS_PER_BLOCK-1:0]; + input wire [31:0] i_m_readdata[NUM_BANKS - 1:0][`NUM_WORDS_PER_BLOCK-1:0]; input wire i_m_ready; output reg [31:0] o_p_readdata[`NUM_THREADS-1:0]; @@ -48,7 +48,7 @@ module VX_d_cache_encapsulate ( output reg [31:0] o_m_addr; output reg o_m_valid; - output reg [31:0] o_m_writedata[NUMBER_BANKS - 1:0][`NUM_WORDS_PER_BLOCK-1:0]; + output reg [31:0] o_m_writedata[NUM_BANKS - 1:0][`NUM_WORDS_PER_BLOCK-1:0]; output reg o_m_read_or_write; @@ -60,8 +60,8 @@ module VX_d_cache_encapsulate ( reg [`NUM_THREADS-1:0][31:0] o_p_readdata_inter; reg [`NUM_THREADS-1:0] o_p_readdata_valid_inter; - reg[NUMBER_BANKS - 1:0][`NUM_WORDS_PER_BLOCK-1:0][31:0] o_m_writedata_inter; - wire[NUMBER_BANKS - 1:0][`NUM_WORDS_PER_BLOCK-1:0][31:0] i_m_readdata_inter; + reg[NUM_BANKS - 1:0][`NUM_WORDS_PER_BLOCK-1:0][31:0] o_m_writedata_inter; + wire[NUM_BANKS - 1:0][`NUM_WORDS_PER_BLOCK-1:0][31:0] i_m_readdata_inter; genvar curr_thraed, curr_bank, curr_word; @@ -74,7 +74,7 @@ module VX_d_cache_encapsulate ( assign o_p_readdata_valid[curr_thraed] = o_p_readdata_valid_inter[curr_thraed]; end - for (curr_bank = 0; curr_bank < NUMBER_BANKS; curr_bank = curr_bank + 1) begin : banks + for (curr_bank = 0; curr_bank < NUM_BANKS; curr_bank = curr_bank + 1) begin : banks for (curr_word = 0; curr_word < `NUM_WORDS_PER_BLOCK; curr_word = curr_word + 1) begin : words assign o_m_writedata[curr_bank][curr_word] = o_m_writedata_inter[curr_bank][curr_word]; diff --git a/hw/rtl/cache/VX_d_cache_tb.v b/hw/rtl/cache/VX_d_cache_tb.v index a29b648f..530ce792 100644 --- a/hw/rtl/cache/VX_d_cache_tb.v +++ b/hw/rtl/cache/VX_d_cache_tb.v @@ -3,7 +3,7 @@ module VX_d_cache_tb; - parameter NUMBER_BANKS = 8; + parameter NUM_BANKS = 8; reg clk, reset, im_ready; reg [`NUM_THREADS-1:0] i_p_valid; @@ -16,9 +16,9 @@ module VX_d_cache_tb; reg o_p_waitrequest; reg [13:0] o_m_addr; // Only one address is sent out at a time to memory reg o_m_valid; - reg [(NUMBER_BANKS * 32) - 1:0] o_m_writedata; + reg [(NUM_BANKS * 32) - 1:0] o_m_writedata; reg o_m_read_or_write; //, o_m_write; - reg [(NUMBER_BANKS * 32) - 1:0] i_m_readdata; // Read Data that is passed from the memory module back to the controller + reg [(NUM_BANKS * 32) - 1:0] i_m_readdata; // Read Data that is passed from the memory module back to the controller VX_d_cache d_cache(.clk(clk), diff --git a/hw/rtl/cache/d_cache_test_bench.h b/hw/rtl/cache/d_cache_test_bench.h index 112aeb9a..a9ce9470 100644 --- a/hw/rtl/cache/d_cache_test_bench.h +++ b/hw/rtl/cache/d_cache_test_bench.h @@ -38,9 +38,9 @@ class VX_d_cache long int curr_cycle; int stats_total_cycles = 0; int stats_dram_accesses = 0; - #ifdef VCD_OUTPUT + #ifdef VCD_OUTPUT VerilatedVcdC *m_trace; - #endif + #endif }; @@ -49,22 +49,20 @@ VX_d_cache::VX_d_cache() : curr_cycle(0), stats_total_cycles(0), stats_dram_acce { this->vx_d_cache_ = new VVX_d_cache_encapsulate; - #ifdef VCD_OUTPUT +#ifdef VCD_OUTPUT this->m_trace = new VerilatedVcdC; this->vx_d_cache_->trace(m_trace, 99); this->m_trace->open("trace.vcd"); - #endif +#endif //this->results.open("../results.txt"); } VX_d_cache::~VX_d_cache() -{ - - +{ delete this->vx_d_cache_; - #ifdef VCD_OUTPUT +#ifdef VCD_OUTPUT m_trace->close(); - #endif +#endif } bool VX_d_cache::operation(int counter_value, bool do_op) { diff --git a/hw/rtl/generic_cache/VX_bank.v b/hw/rtl/generic_cache/VX_bank.v index 62da49d0..d20c9b0d 100644 --- a/hw/rtl/generic_cache/VX_bank.v +++ b/hw/rtl/generic_cache/VX_bank.v @@ -7,11 +7,11 @@ module VX_bank // Size of line inside a bank in bytes parameter BANK_LINE_SIZE_BYTES = 16, // Number of banks {1, 2, 4, 8,...} - parameter NUMBER_BANKS = 8, + parameter NUM_BANKS = 8, // Size of a word in bytes parameter WORD_SIZE_BYTES = 4, // Number of Word requests per cycle {1, 2, 4, 8, ...} - parameter NUMBER_REQUESTS = 2, + parameter NUM_REQUESTS = 2, // Number of cycles to complete stage 1 (read from memory) parameter STAGE_1_CYCLES = 2, // Function ID, {Dcache=0, Icache=1, Sharedmemory=2} @@ -54,24 +54,24 @@ module VX_bank // Input Core Request input wire delay_req, - input wire [NUMBER_REQUESTS-1:0] bank_valids, - input wire [NUMBER_REQUESTS-1:0][31:0] bank_addr, - input wire [NUMBER_REQUESTS-1:0][`WORD_SIZE_RNG] bank_writedata, + input wire [NUM_REQUESTS-1:0] bank_valids, + input wire [NUM_REQUESTS-1:0][31:0] bank_addr, + input wire [NUM_REQUESTS-1:0][`WORD_SIZE_RNG] bank_writedata, input wire [4:0] bank_rd, - input wire [NUMBER_REQUESTS-1:0][1:0] bank_wb, + input wire [NUM_REQUESTS-1:0][1:0] bank_wb, input wire [31:0] bank_pc, - input wire [`NW_BITS-1:0] bank_warp_num, - input wire [NUMBER_REQUESTS-1:0][2:0] bank_mem_read, - input wire [NUMBER_REQUESTS-1:0][2:0] bank_mem_write, + input wire [`NW_BITS-1:0] bank_warp_num, + input wire [NUM_REQUESTS-1:0][2:0] bank_mem_read, + input wire [NUM_REQUESTS-1:0][2:0] bank_mem_write, output wire reqq_full, // Output Core WB input wire bank_wb_pop, output wire bank_wb_valid, - output wire [`vx_clog2(NUMBER_REQUESTS)-1:0] bank_wb_tid, + output wire [`LOG2UP(NUM_REQUESTS)-1:0] bank_wb_tid, output wire [4:0] bank_wb_rd, output wire [1:0] bank_wb_wb, - output wire [`NW_BITS-1:0] bank_wb_warp_num, + output wire [`NW_BITS-1:0] bank_wb_warp_num, output wire [`WORD_SIZE_RNG] bank_wb_data, output wire [31:0] bank_wb_pc, output wire [31:0] bank_wb_address, @@ -105,7 +105,6 @@ module VX_bank input wire snp_fwd_pop ); - reg snoop_state = 0; always @(posedge clk) begin @@ -152,19 +151,18 @@ module VX_bank .out_data({dfpq_addr_st0, dfpq_filldata_st0}), .empty (dfpq_empty), .full (dfpq_full) - ); - + ); wire reqq_pop; wire reqq_push; wire reqq_empty; wire reqq_req_st0; - wire[`vx_clog2(NUMBER_REQUESTS)-1:0] reqq_req_tid_st0; + wire[`LOG2UP(NUM_REQUESTS)-1:0] reqq_req_tid_st0; wire [31:0] reqq_req_addr_st0; wire [`WORD_SIZE_RNG] reqq_req_writeword_st0; wire [4:0] reqq_req_rd_st0; wire [1:0] reqq_req_wb_st0; - wire [`NW_BITS-1:0] reqq_req_warp_num_st0; + wire [`NW_BITS-1:0] reqq_req_warp_num_st0; wire [2:0] reqq_req_mem_read_st0; wire [2:0] reqq_req_mem_write_st0; wire [31:0] reqq_req_pc_st0; @@ -174,9 +172,9 @@ module VX_bank VX_cache_req_queue #( .CACHE_SIZE_BYTES (CACHE_SIZE_BYTES), .BANK_LINE_SIZE_BYTES (BANK_LINE_SIZE_BYTES), - .NUMBER_BANKS (NUMBER_BANKS), + .NUM_BANKS (NUM_BANKS), .WORD_SIZE_BYTES (WORD_SIZE_BYTES), - .NUMBER_REQUESTS (NUMBER_REQUESTS), + .NUM_REQUESTS (NUM_REQUESTS), .STAGE_1_CYCLES (STAGE_1_CYCLES), .REQQ_SIZE (REQQ_SIZE), .MRVQ_SIZE (MRVQ_SIZE), @@ -225,37 +223,37 @@ module VX_bank wire mrvq_full; wire mrvq_stop; wire mrvq_valid_st0; - wire[`vx_clog2(NUMBER_REQUESTS)-1:0] mrvq_tid_st0; + wire[`LOG2UP(NUM_REQUESTS)-1:0] mrvq_tid_st0; wire [31:0] mrvq_addr_st0; wire [`WORD_SIZE_RNG] mrvq_writeword_st0; wire [4:0] mrvq_rd_st0; wire [1:0] mrvq_wb_st0; wire [31:0] miss_resrv_pc_st0; - wire [`NW_BITS-1:0] mrvq_warp_num_st0; + wire [`NW_BITS-1:0] mrvq_warp_num_st0; wire [2:0] mrvq_mem_read_st0; wire [2:0] mrvq_mem_write_st0; wire miss_add; wire[31:0] miss_add_addr; wire[`WORD_SIZE_RNG] miss_add_data; - wire[`vx_clog2(NUMBER_REQUESTS)-1:0] miss_add_tid; + wire[`LOG2UP(NUM_REQUESTS)-1:0] miss_add_tid; wire[4:0] miss_add_rd; wire[1:0] miss_add_wb; - wire[`NW_BITS-1:0] miss_add_warp_num; + wire[`NW_BITS-1:0] miss_add_warp_num; wire[2:0] miss_add_mem_read; wire[2:0] miss_add_mem_write; wire[31:0] miss_add_pc; - wire[31:0] addr_st2; - wire is_fill_st2; + wire[31:0] addr_st2; + wire is_fill_st2; VX_cache_miss_resrv #( .CACHE_SIZE_BYTES (CACHE_SIZE_BYTES), .BANK_LINE_SIZE_BYTES (BANK_LINE_SIZE_BYTES), - .NUMBER_BANKS (NUMBER_BANKS), + .NUM_BANKS (NUM_BANKS), .WORD_SIZE_BYTES (WORD_SIZE_BYTES), - .NUMBER_REQUESTS (NUMBER_REQUESTS), + .NUM_REQUESTS (NUM_REQUESTS), .STAGE_1_CYCLES (STAGE_1_CYCLES), .REQQ_SIZE (REQQ_SIZE), .MRVQ_SIZE (MRVQ_SIZE), @@ -312,7 +310,7 @@ module VX_bank wire going_to_write_st1[STAGE_1_CYCLES-1:0]; wire [31:0] addr_st1 [STAGE_1_CYCLES-1:0]; - reg[16:0] p_stage; + integer p_stage; always @(*) begin is_fill_in_pipe = 0; for (p_stage = 0; p_stage < STAGE_1_CYCLES; p_stage=p_stage+1) begin @@ -322,8 +320,7 @@ module VX_bank if (is_fill_st2) is_fill_in_pipe = 1; end -// assign is_fill_in_pipe = (|is_fill_st1) || is_fill_st2; - +// assign is_fill_in_pipe = (|is_fill_st1) || is_fill_st2; assign mrvq_pop = mrvq_valid_st0 && !stall_bank_pipe; assign dfpq_pop = !mrvq_pop && !dfpq_empty && !stall_bank_pipe; @@ -421,10 +418,10 @@ module VX_bank wire [4:0] rd_st1e; wire [1:0] wb_st1e; - wire [`NW_BITS-1:0] warp_num_st1e; + wire [`NW_BITS-1:0] warp_num_st1e; wire [2:0] mem_read_st1e; wire [2:0] mem_write_st1e; - wire [`vx_clog2(NUMBER_REQUESTS)-1:0] tid_st1e; + wire [`LOG2UP(NUM_REQUESTS)-1:0] tid_st1e; wire fill_saw_dirty_st1e; wire is_snp_st1e; @@ -436,9 +433,9 @@ module VX_bank VX_tag_data_access #( .CACHE_SIZE_BYTES (CACHE_SIZE_BYTES), .BANK_LINE_SIZE_BYTES (BANK_LINE_SIZE_BYTES), - .NUMBER_BANKS (NUMBER_BANKS), + .NUM_BANKS (NUM_BANKS), .WORD_SIZE_BYTES (WORD_SIZE_BYTES), - .NUMBER_REQUESTS (NUMBER_REQUESTS), + .NUM_REQUESTS (NUM_REQUESTS), .STAGE_1_CYCLES (STAGE_1_CYCLES), .FUNC_ID (FUNC_ID), .REQQ_SIZE (REQQ_SIZE), @@ -527,15 +524,15 @@ module VX_bank // Enqueue to CWB Queue wire cwbq_push = (valid_st2 && !miss_st2) && !cwbq_full && !((FUNC_ID == `L2FUNC_ID) && (miss_add_wb == 0)) && !((is_snp_st2 && valid_st2 && ffsq_full) || (((valid_st2 && miss_st2 && dirty_st2) || fill_saw_dirty_st2) && dwbq_full) || (valid_st2 && miss_st2 && mrvq_full) || (valid_st2 && miss_st2 && !invalidate_fill && dram_fill_req_queue_full)); wire [`WORD_SIZE_RNG] cwbq_data = readword_st2; - wire [`vx_clog2(NUMBER_REQUESTS)-1:0] cwbq_tid = miss_add_tid; + wire [`LOG2UP(NUM_REQUESTS)-1:0] cwbq_tid = miss_add_tid; wire [4:0] cwbq_rd = miss_add_rd; wire [1:0] cwbq_wb = miss_add_wb; - wire [`NW_BITS-1:0] cwbq_warp_num = miss_add_warp_num; + wire [`NW_BITS-1:0] cwbq_warp_num = miss_add_warp_num; wire [31:0] cwbq_pc = pc_st2; wire cwbq_empty; assign bank_wb_valid = !cwbq_empty; - VX_generic_queue_ll #(.DATAW( `vx_clog2(NUMBER_REQUESTS) + 5 + 2 + (`NW_BITS-1+1) + `WORD_SIZE + 32 + 32), .SIZE(CWBQ_SIZE)) cwb_queue( + VX_generic_queue_ll #(.DATAW( `LOG2UP(NUM_REQUESTS) + 5 + 2 + (`NW_BITS-1+1) + `WORD_SIZE + 32 + 32), .SIZE(CWBQ_SIZE)) cwb_queue( .clk (clk), .reset (reset), @@ -570,9 +567,9 @@ module VX_bank VX_fill_invalidator #( .CACHE_SIZE_BYTES (CACHE_SIZE_BYTES), .BANK_LINE_SIZE_BYTES (BANK_LINE_SIZE_BYTES), - .NUMBER_BANKS (NUMBER_BANKS), + .NUM_BANKS (NUM_BANKS), .WORD_SIZE_BYTES (WORD_SIZE_BYTES), - .NUMBER_REQUESTS (NUMBER_REQUESTS), + .NUM_REQUESTS (NUM_REQUESTS), .STAGE_1_CYCLES (STAGE_1_CYCLES), .REQQ_SIZE (REQQ_SIZE), .MRVQ_SIZE (MRVQ_SIZE), diff --git a/hw/rtl/generic_cache/VX_cache.v b/hw/rtl/generic_cache/VX_cache.v index a6047e33..d8211a70 100644 --- a/hw/rtl/generic_cache/VX_cache.v +++ b/hw/rtl/generic_cache/VX_cache.v @@ -7,11 +7,11 @@ module VX_cache // Size of line inside a bank in bytes parameter BANK_LINE_SIZE_BYTES = 16, // Number of banks {1, 2, 4, 8,...} - parameter NUMBER_BANKS = 8, + parameter NUM_BANKS = 8, // Size of a word in bytes parameter WORD_SIZE_BYTES = 16, // Number of Word requests per cycle {1, 2, 4, 8, ...} - parameter NUMBER_REQUESTS = 2, + parameter NUM_REQUESTS = 2, // Number of cycles to complete stage 1 (read from memory) parameter STAGE_1_CYCLES = 2, // Function ID, {Dcache=0, Icache=1, Sharedmemory=2} @@ -57,28 +57,28 @@ module VX_cache input wire reset, // Req Info - input wire [NUMBER_REQUESTS-1:0] core_req_valid, - input wire [NUMBER_REQUESTS-1:0][31:0] core_req_addr, - input wire [NUMBER_REQUESTS-1:0][`WORD_SIZE_RNG] core_req_writedata, - input wire[NUMBER_REQUESTS-1:0][2:0] core_req_mem_read, - input wire[NUMBER_REQUESTS-1:0][2:0] core_req_mem_write, + input wire [NUM_REQUESTS-1:0] core_req_valid, + input wire [NUM_REQUESTS-1:0][31:0] core_req_addr, + input wire [NUM_REQUESTS-1:0][`WORD_SIZE_RNG] core_req_writedata, + input wire[NUM_REQUESTS-1:0][2:0] core_req_mem_read, + input wire[NUM_REQUESTS-1:0][2:0] core_req_mem_write, // Req meta input wire [4:0] core_req_rd, - input wire [NUMBER_REQUESTS-1:0][1:0] core_req_wb, - input wire [`NW_BITS-1:0] core_req_warp_num, + input wire [NUM_REQUESTS-1:0][1:0] core_req_wb, + input wire [`NW_BITS-1:0] core_req_warp_num, input wire [31:0] core_req_pc, output wire delay_req, // Core Writeback input wire core_no_wb_slot, - output wire [NUMBER_REQUESTS-1:0] core_wb_valid, + output wire [NUM_REQUESTS-1:0] core_wb_valid, output wire [4:0] core_wb_req_rd, output wire [1:0] core_wb_req_wb, - output wire [`NW_BITS-1:0] core_wb_warp_num, - output wire [NUMBER_REQUESTS-1:0][`WORD_SIZE_RNG] core_wb_readdata, - output wire [NUMBER_REQUESTS-1:0][31:0] core_wb_pc, - output wire [NUMBER_REQUESTS-1:0][31:0] core_wb_address, + output wire [`NW_BITS-1:0] core_wb_warp_num, + output wire [NUM_REQUESTS-1:0][`WORD_SIZE_RNG] core_wb_readdata, + output wire [NUM_REQUESTS-1:0][31:0] core_wb_pc, + output wire [NUM_REQUESTS-1:0][31:0] core_wb_address, // Dram Fill Response @@ -113,36 +113,36 @@ module VX_cache ); - wire [NUMBER_BANKS-1:0][NUMBER_REQUESTS-1:0] per_bank_valids; - wire [NUMBER_BANKS-1:0] per_bank_wb_pop; - wire [NUMBER_BANKS-1:0] per_bank_wb_valid; - wire [NUMBER_BANKS-1:0][`vx_clog2(NUMBER_REQUESTS)-1:0] per_bank_wb_tid; - wire [NUMBER_BANKS-1:0][4:0] per_bank_wb_rd; - wire [NUMBER_BANKS-1:0][1:0] per_bank_wb_wb; - wire [NUMBER_BANKS-1:0][`NW_BITS-1:0] per_bank_wb_warp_num; - wire [NUMBER_BANKS-1:0][`WORD_SIZE_RNG] per_bank_wb_data; - wire [NUMBER_BANKS-1:0][31:0] per_bank_wb_pc; - wire [NUMBER_BANKS-1:0][31:0] per_bank_wb_address; + wire [NUM_BANKS-1:0][NUM_REQUESTS-1:0] per_bank_valids; + wire [NUM_BANKS-1:0] per_bank_wb_pop; + wire [NUM_BANKS-1:0] per_bank_wb_valid; + wire [NUM_BANKS-1:0][`LOG2UP(NUM_REQUESTS)-1:0] per_bank_wb_tid; + wire [NUM_BANKS-1:0][4:0] per_bank_wb_rd; + wire [NUM_BANKS-1:0][1:0] per_bank_wb_wb; + wire [NUM_BANKS-1:0][`NW_BITS-1:0] per_bank_wb_warp_num; + wire [NUM_BANKS-1:0][`WORD_SIZE_RNG] per_bank_wb_data; + wire [NUM_BANKS-1:0][31:0] per_bank_wb_pc; + wire [NUM_BANKS-1:0][31:0] per_bank_wb_address; - wire dfqq_full; - wire[NUMBER_BANKS-1:0] per_bank_dram_fill_req; - wire[NUMBER_BANKS-1:0][31:0] per_bank_dram_fill_req_addr; - wire[NUMBER_BANKS-1:0] per_bank_dram_fill_accept; + wire dfqq_full; + wire[NUM_BANKS-1:0] per_bank_dram_fill_req; + wire[NUM_BANKS-1:0][31:0] per_bank_dram_fill_req_addr; + wire[NUM_BANKS-1:0] per_bank_dram_fill_accept; - wire[NUMBER_BANKS-1:0] per_bank_dram_wb_queue_pop; - wire[NUMBER_BANKS-1:0] per_bank_dram_wb_req; - wire[NUMBER_BANKS-1:0] per_bank_dram_because_of_snp; - wire[NUMBER_BANKS-1:0][31:0] per_bank_dram_wb_req_addr; - wire[NUMBER_BANKS-1:0][`BANK_LINE_WORDS-1:0][`WORD_SIZE-1:0] per_bank_dram_wb_req_data; + wire[NUM_BANKS-1:0] per_bank_dram_wb_queue_pop; + wire[NUM_BANKS-1:0] per_bank_dram_wb_req; + wire[NUM_BANKS-1:0] per_bank_dram_because_of_snp; + wire[NUM_BANKS-1:0][31:0] per_bank_dram_wb_req_addr; + wire[NUM_BANKS-1:0][`BANK_LINE_WORDS-1:0][`WORD_SIZE-1:0] per_bank_dram_wb_req_data; - wire[NUMBER_BANKS-1:0] per_bank_reqq_full; + wire[NUM_BANKS-1:0] per_bank_reqq_full; - wire[NUMBER_BANKS-1:0] per_bank_snrq_full; + wire[NUM_BANKS-1:0] per_bank_snrq_full; - wire[NUMBER_BANKS-1:0] per_bank_snp_fwd; - wire[NUMBER_BANKS-1:0][31:0] per_bank_snp_fwd_addr; - wire[NUMBER_BANKS-1:0] per_bank_snp_fwd_pop; + wire[NUM_BANKS-1:0] per_bank_snp_fwd; + wire[NUM_BANKS-1:0][31:0] per_bank_snp_fwd_addr; + wire[NUM_BANKS-1:0] per_bank_snp_fwd_pop; assign delay_req = (|per_bank_reqq_full); @@ -151,15 +151,15 @@ module VX_cache assign snp_req_delay = (|per_bank_snrq_full); - // assign dram_fill_accept = (NUMBER_BANKS == 1) ? per_bank_dram_fill_accept[0] : per_bank_dram_fill_accept[dram_fill_rsp_addr[`BANK_SELECT_ADDR_RNG]]; + // assign dram_fill_accept = (NUM_BANKS == 1) ? per_bank_dram_fill_accept[0] : per_bank_dram_fill_accept[dram_fill_rsp_addr[`BANK_SELECT_ADDR_RNG]]; assign dram_fill_accept = (|per_bank_dram_fill_accept); VX_cache_dram_req_arb #( .CACHE_SIZE_BYTES (CACHE_SIZE_BYTES), .BANK_LINE_SIZE_BYTES (BANK_LINE_SIZE_BYTES), - .NUMBER_BANKS (NUMBER_BANKS), + .NUM_BANKS (NUM_BANKS), .WORD_SIZE_BYTES (WORD_SIZE_BYTES), - .NUMBER_REQUESTS (NUMBER_REQUESTS), + .NUM_REQUESTS (NUM_REQUESTS), .STAGE_1_CYCLES (STAGE_1_CYCLES), .REQQ_SIZE (REQQ_SIZE), .MRVQ_SIZE (MRVQ_SIZE), @@ -200,9 +200,9 @@ module VX_cache VX_cache_core_req_bank_sel #( .CACHE_SIZE_BYTES (CACHE_SIZE_BYTES), .BANK_LINE_SIZE_BYTES (BANK_LINE_SIZE_BYTES), - .NUMBER_BANKS (NUMBER_BANKS), + .NUM_BANKS (NUM_BANKS), .WORD_SIZE_BYTES (WORD_SIZE_BYTES), - .NUMBER_REQUESTS (NUMBER_REQUESTS), + .NUM_REQUESTS (NUM_REQUESTS), .STAGE_1_CYCLES (STAGE_1_CYCLES), .REQQ_SIZE (REQQ_SIZE), .MRVQ_SIZE (MRVQ_SIZE), @@ -226,9 +226,9 @@ module VX_cache VX_cache_wb_sel_merge #( .CACHE_SIZE_BYTES (CACHE_SIZE_BYTES), .BANK_LINE_SIZE_BYTES (BANK_LINE_SIZE_BYTES), - .NUMBER_BANKS (NUMBER_BANKS), + .NUM_BANKS (NUM_BANKS), .WORD_SIZE_BYTES (WORD_SIZE_BYTES), - .NUMBER_REQUESTS (NUMBER_REQUESTS), + .NUM_REQUESTS (NUM_REQUESTS), .STAGE_1_CYCLES (STAGE_1_CYCLES), .FUNC_ID (FUNC_ID), .REQQ_SIZE (REQQ_SIZE), @@ -268,7 +268,7 @@ module VX_cache // Snoop Forward Logic - VX_snp_fwd_arb #(.NUMBER_BANKS(NUMBER_BANKS)) VX_snp_fwd_arb( + VX_snp_fwd_arb #(.NUM_BANKS(NUM_BANKS)) VX_snp_fwd_arb( .per_bank_snp_fwd (per_bank_snp_fwd), .per_bank_snp_fwd_addr(per_bank_snp_fwd_addr), .per_bank_snp_fwd_pop (per_bank_snp_fwd_pop), @@ -281,30 +281,30 @@ module VX_cache genvar curr_bank; generate - for (curr_bank = 0; curr_bank < NUMBER_BANKS; curr_bank=curr_bank+1) begin - wire [NUMBER_REQUESTS-1:0] curr_bank_valids; - wire [NUMBER_REQUESTS-1:0][31:0] curr_bank_addr; - wire [NUMBER_REQUESTS-1:0][`WORD_SIZE_RNG] curr_bank_writedata; + for (curr_bank = 0; curr_bank < NUM_BANKS; curr_bank=curr_bank+1) begin + wire [NUM_REQUESTS-1:0] curr_bank_valids; + wire [NUM_REQUESTS-1:0][31:0] curr_bank_addr; + wire [NUM_REQUESTS-1:0][`WORD_SIZE_RNG] curr_bank_writedata; wire [4:0] curr_bank_rd; - wire [NUMBER_REQUESTS-1:0][1:0] curr_bank_wb; - wire [`NW_BITS-1:0] curr_bank_warp_num; - wire [NUMBER_REQUESTS-1:0][2:0] curr_bank_mem_read; - wire [NUMBER_REQUESTS-1:0][2:0] curr_bank_mem_write; + wire [NUM_REQUESTS-1:0][1:0] curr_bank_wb; + wire [`NW_BITS-1:0] curr_bank_warp_num; + wire [NUM_REQUESTS-1:0][2:0] curr_bank_mem_read; + wire [NUM_REQUESTS-1:0][2:0] curr_bank_mem_write; wire [31:0] curr_bank_pc; wire curr_bank_wb_pop; wire curr_bank_wb_valid; - wire [`vx_clog2(NUMBER_REQUESTS)-1:0] curr_bank_wb_tid; + wire [`LOG2UP(NUM_REQUESTS)-1:0] curr_bank_wb_tid; wire [31:0] curr_bank_wb_pc; wire [4:0] curr_bank_wb_rd; wire [1:0] curr_bank_wb_wb; - wire [`NW_BITS-1:0] curr_bank_wb_warp_num; + wire [`NW_BITS-1:0] curr_bank_wb_warp_num; wire [`WORD_SIZE_RNG] curr_bank_wb_data; wire [31:0] curr_bank_wb_address; wire curr_bank_dram_fill_rsp; wire [31:0] curr_bank_dram_fill_rsp_addr; - wire [`BANK_LINE_WORDS-1:0][`WORD_SIZE-1:0] curr_bank_dram_fill_rsp_data; + wire [`BANK_LINE_WORDS-1:0][`WORD_SIZE-1:0] curr_bank_dram_fill_rsp_data; wire curr_bank_dram_fill_accept; wire curr_bank_dfqq_full; @@ -326,7 +326,7 @@ module VX_cache wire curr_bank_snp_fwd; wire[31:0] curr_bank_snp_fwd_addr; wire curr_bank_snp_fwd_pop; - wire curr_bank_snrq_full; + wire curr_bank_snrq_full; @@ -359,7 +359,7 @@ module VX_cache assign per_bank_dram_fill_req_addr[curr_bank] = curr_bank_dram_fill_req_addr; // Dram fill response - assign curr_bank_dram_fill_rsp = (NUMBER_BANKS == 1) || (dram_fill_rsp && (curr_bank_dram_fill_rsp_addr[`BANK_SELECT_ADDR_RNG] == curr_bank)); + assign curr_bank_dram_fill_rsp = (NUM_BANKS == 1) || (dram_fill_rsp && (curr_bank_dram_fill_rsp_addr[`BANK_SELECT_ADDR_RNG] == curr_bank)); assign curr_bank_dram_fill_rsp_addr = dram_fill_rsp_addr; assign curr_bank_dram_fill_rsp_data = dram_fill_rsp_data; assign per_bank_dram_fill_accept[curr_bank] = curr_bank_dram_fill_accept; @@ -385,9 +385,9 @@ module VX_cache VX_bank #( .CACHE_SIZE_BYTES (CACHE_SIZE_BYTES), .BANK_LINE_SIZE_BYTES (BANK_LINE_SIZE_BYTES), - .NUMBER_BANKS (NUMBER_BANKS), + .NUM_BANKS (NUM_BANKS), .WORD_SIZE_BYTES (WORD_SIZE_BYTES), - .NUMBER_REQUESTS (NUMBER_REQUESTS), + .NUM_REQUESTS (NUM_REQUESTS), .STAGE_1_CYCLES (STAGE_1_CYCLES), .FUNC_ID (FUNC_ID), .REQQ_SIZE (REQQ_SIZE), diff --git a/hw/rtl/generic_cache/VX_cache_config.vh b/hw/rtl/generic_cache/VX_cache_config.vh index 9d44f4ba..ef88a195 100644 --- a/hw/rtl/generic_cache/VX_cache_config.vh +++ b/hw/rtl/generic_cache/VX_cache_config.vh @@ -3,59 +3,17 @@ `include "../VX_define.vh" - // data tid rd wb warp_num read write - - -`define vx_clog2(value) ((value == 1) ? 1 : $clog2(value)) - - -`define MRVQ_METADATA_SIZE (`WORD_SIZE + `vx_clog2(NUMBER_REQUESTS) + 5 + 2 + (`NW_BITS-1 + 1) + 3 + 3) +`define MRVQ_METADATA_SIZE (`WORD_SIZE + `LOG2UP(NUM_REQUESTS) + 5 + 2 + (`NW_BITS-1 + 1) + 3 + 3) // 5 + 2 + 4 + 3 + 3 + 1 -`define REQ_INST_META_SIZE (5 + 2 + (`NW_BITS-1+1) + 3 + 3 + `vx_clog2(NUMBER_REQUESTS)) - -// `define vx_clog2_h(value, x) (value == (1 << x)) ? (x) - -// `define vx_clog2(value) (value == 0 ) ? 0 : \ -// (value == 1 ) ? 1 : \ -// `vx_clog2_h(value, 2 ) : \ -// `vx_clog2_h(value, 3 ) : \ -// `vx_clog2_h(value, 4 ) : \ -// `vx_clog2_h(value, 5 ) : \ -// `vx_clog2_h(value, 6 ) : \ -// `vx_clog2_h(value, 7 ) : \ -// `vx_clog2_h(value, 8 ) : \ -// `vx_clog2_h(value, 9 ) : \ -// `vx_clog2_h(value, 10) : \ -// `vx_clog2_h(value, 11) : \ -// `vx_clog2_h(value, 12) : \ -// `vx_clog2_h(value, 13) : \ -// `vx_clog2_h(value, 14) : \ -// `vx_clog2_h(value, 15) : \ -// `vx_clog2_h(value, 16) : \ -// `vx_clog2_h(value, 17) : \ -// `vx_clog2_h(value, 18) : \ -// `vx_clog2_h(value, 19) : \ -// `vx_clog2_h(value, 20) : \ -// `vx_clog2_h(value, 21) : \ -// `vx_clog2_h(value, 22) : \ -// `vx_clog2_h(value, 23) : \ -// `vx_clog2_h(value, 24) : \ -// `vx_clog2_h(value, 25) : \ -// `vx_clog2_h(value, 26) : \ -// `vx_clog2_h(value, 27) : \ -// `vx_clog2_h(value, 28) : \ -// `vx_clog2_h(value, 29) : \ -// `vx_clog2_h(value, 30) : \ -// `vx_clog2_h(value, 31) : \ -// 0 +`define REQ_INST_META_SIZE (5 + 2 + (`NW_BITS-1+1) + 3 + 3 + `LOG2UP(NUM_REQUESTS)) `define WORD_SIZE (8*WORD_SIZE_BYTES) `define WORD_SIZE_RNG (`WORD_SIZE)-1:0 // 128 -`define BANK_SIZE_BYTES CACHE_SIZE_BYTES/NUMBER_BANKS +`define BANK_SIZE_BYTES CACHE_SIZE_BYTES/NUM_BANKS // 8 `define BANK_LINE_COUNT (`BANK_SIZE_BYTES/BANK_LINE_SIZE_BYTES) @@ -71,7 +29,7 @@ `define OFFSET_SIZE_RNG `OFFSET_SIZE_END:0 // 2 -`define WORD_SELECT_NUM_BITS (`vx_clog2(`BANK_LINE_WORDS)) +`define WORD_SELECT_NUM_BITS (`LOG2UP(`BANK_LINE_WORDS)) // 2 `define WORD_SELECT_SIZE_END (`WORD_SELECT_NUM_BITS) // 2 @@ -83,7 +41,7 @@ `define WORD_SELECT_SIZE_RNG `WORD_SELECT_SIZE_END-1:0 // 3 -`define BANK_SELECT_NUM_BITS (`vx_clog2(NUMBER_BANKS)) +`define BANK_SELECT_NUM_BITS (`LOG2UP(NUM_BANKS)) // 3 `define BANK_SELECT_SIZE_END (`BANK_SELECT_NUM_BITS) // 4 @@ -96,7 +54,7 @@ `define BANK_SELECT_SIZE_RNG `BANK_SELECT_SIZE_END-1:0 // 3 -`define LINE_SELECT_NUM_BITS (`vx_clog2(`BANK_LINE_COUNT)) +`define LINE_SELECT_NUM_BITS (`LOG2UP(`BANK_LINE_COUNT)) // 3 `define LINE_SELECT_SIZE_END (`LINE_SELECT_NUM_BITS) // 7 @@ -120,9 +78,7 @@ // 21:0 `define TAG_SELECT_SIZE_RNG `TAG_SELECT_SIZE_END-1:0 - `define BASE_ADDR_MASK (~((1<<(`WORD_SELECT_ADDR_END+1))-1)) - `endif diff --git a/hw/rtl/generic_cache/VX_cache_core_req_bank_sel.v b/hw/rtl/generic_cache/VX_cache_core_req_bank_sel.v index 9b49336d..428f729f 100644 --- a/hw/rtl/generic_cache/VX_cache_core_req_bank_sel.v +++ b/hw/rtl/generic_cache/VX_cache_core_req_bank_sel.v @@ -8,11 +8,11 @@ module VX_cache_core_req_bank_sel // Size of line inside a bank in bytes parameter BANK_LINE_SIZE_BYTES = 16, // Number of banks {1, 2, 4, 8,...} - parameter NUMBER_BANKS = 8, + parameter NUM_BANKS = 8, // Size of a word in bytes parameter WORD_SIZE_BYTES = 4, // Number of Word requests per cycle {1, 2, 4, 8, ...} - parameter NUMBER_REQUESTS = 2, + parameter NUM_REQUESTS = 2, // Number of cycles to complete stage 1 (read from memory) parameter STAGE_1_CYCLES = 2, // Function ID, {Dcache=0, Icache=1, Sharedmemory=2} @@ -48,10 +48,10 @@ module VX_cache_core_req_bank_sel ) ( - input wire [NUMBER_REQUESTS-1:0] core_req_valid, - input wire [NUMBER_REQUESTS-1:0][31:0] core_req_addr, + input wire [NUM_REQUESTS-1:0] core_req_valid, + input wire [NUM_REQUESTS-1:0][31:0] core_req_addr, - output reg [NUMBER_BANKS-1:0][NUMBER_REQUESTS-1:0] per_bank_valids + output reg [NUM_BANKS-1:0][NUM_REQUESTS-1:0] per_bank_valids ); wire[31:0] req_address; @@ -60,8 +60,8 @@ module VX_cache_core_req_bank_sel integer curr_req; always @(*) begin per_bank_valids = 0; - for (curr_req = 0; curr_req < NUMBER_REQUESTS; curr_req = curr_req + 1) begin - if (NUMBER_BANKS == 1) begin + for (curr_req = 0; curr_req < NUM_REQUESTS; curr_req = curr_req + 1) begin + if (NUM_BANKS == 1) begin // If there is only one bank, then only map requests to that bank per_bank_valids[0][curr_req] = core_req_valid[curr_req]; end else begin diff --git a/hw/rtl/generic_cache/VX_cache_dfq_queue.v b/hw/rtl/generic_cache/VX_cache_dfq_queue.v index 9f586f22..09ec7cc6 100644 --- a/hw/rtl/generic_cache/VX_cache_dfq_queue.v +++ b/hw/rtl/generic_cache/VX_cache_dfq_queue.v @@ -7,11 +7,11 @@ module VX_cache_dfq_queue // Size of line inside a bank in bytes parameter BANK_LINE_SIZE_BYTES = 16, // Number of banks {1, 2, 4, 8,...} - parameter NUMBER_BANKS = 8, + parameter NUM_BANKS = 8, // Size of a word in bytes parameter WORD_SIZE_BYTES = 4, // Number of Word requests per cycle {1, 2, 4, 8, ...} - parameter NUMBER_REQUESTS = 2, + parameter NUM_REQUESTS = 2, // Number of cycles to complete stage 1 (read from memory) parameter STAGE_1_CYCLES = 2, @@ -45,11 +45,11 @@ module VX_cache_dfq_queue ) ( - input wire clk, - input wire reset, - input wire dfqq_push, - input wire[NUMBER_BANKS-1:0] per_bank_dram_fill_req, - input wire[NUMBER_BANKS-1:0][31:0] per_bank_dram_fill_req_addr, + input wire clk, + input wire reset, + input wire dfqq_push, + input wire[NUM_BANKS-1:0] per_bank_dram_fill_req, + input wire[NUM_BANKS-1:0][31:0] per_bank_dram_fill_req_addr, input wire dfqq_pop, output wire dfqq_req, @@ -58,18 +58,18 @@ module VX_cache_dfq_queue output wire dfqq_full ); - wire[NUMBER_BANKS-1:0] out_per_bank_dram_fill_req; - wire[NUMBER_BANKS-1:0][31:0] out_per_bank_dram_fill_req_addr; + wire[NUM_BANKS-1:0] out_per_bank_dram_fill_req; + wire[NUM_BANKS-1:0][31:0] out_per_bank_dram_fill_req_addr; - reg [NUMBER_BANKS-1:0] use_per_bank_dram_fill_req; - reg [NUMBER_BANKS-1:0][31:0] use_per_bank_dram_fill_req_addr; + reg [NUM_BANKS-1:0] use_per_bank_dram_fill_req; + reg [NUM_BANKS-1:0][31:0] use_per_bank_dram_fill_req_addr; - wire[NUMBER_BANKS-1:0] qual_bank_dram_fill_req; - wire[NUMBER_BANKS-1:0][31:0] qual_bank_dram_fill_req_addr; + wire[NUM_BANKS-1:0] qual_bank_dram_fill_req; + wire[NUM_BANKS-1:0][31:0] qual_bank_dram_fill_req_addr; - wire[NUMBER_BANKS-1:0] updated_bank_dram_fill_req; + wire[NUM_BANKS-1:0] updated_bank_dram_fill_req; wire o_empty; @@ -79,7 +79,7 @@ module VX_cache_dfq_queue wire push_qual = dfqq_push && !dfqq_full; wire pop_qual = dfqq_pop && use_empty && !out_empty; - VX_generic_queue_ll #(.DATAW(NUMBER_BANKS * (1+32)), .SIZE(DFQQ_SIZE)) dfqq_queue( + VX_generic_queue_ll #(.DATAW(NUM_BANKS * (1+32)), .SIZE(DFQQ_SIZE)) dfqq_queue( .clk (clk), .reset (reset), .push (push_qual), @@ -90,13 +90,12 @@ module VX_cache_dfq_queue .full (dfqq_full) ); - - assign qual_bank_dram_fill_req = use_empty ? (out_per_bank_dram_fill_req & {NUMBER_BANKS{!o_empty}}) : (use_per_bank_dram_fill_req & {NUMBER_BANKS{!use_empty}}); + assign qual_bank_dram_fill_req = use_empty ? (out_per_bank_dram_fill_req & {NUM_BANKS{!o_empty}}) : (use_per_bank_dram_fill_req & {NUM_BANKS{!use_empty}}); assign qual_bank_dram_fill_req_addr = use_empty ? out_per_bank_dram_fill_req_addr : use_per_bank_dram_fill_req_addr; - wire[`vx_clog2(NUMBER_BANKS)-1:0] qual_request_index; + wire[`LOG2UP(NUM_BANKS)-1:0] qual_request_index; wire qual_has_request; - VX_generic_priority_encoder #(.N(NUMBER_BANKS)) VX_sel_bank( + VX_generic_priority_encoder #(.N(NUM_BANKS)) VX_sel_bank( .valids(qual_bank_dram_fill_req), .index (qual_request_index), .found (qual_has_request) diff --git a/hw/rtl/generic_cache/VX_cache_dram_req_arb.v b/hw/rtl/generic_cache/VX_cache_dram_req_arb.v index 42adcff7..7a19db32 100644 --- a/hw/rtl/generic_cache/VX_cache_dram_req_arb.v +++ b/hw/rtl/generic_cache/VX_cache_dram_req_arb.v @@ -7,11 +7,11 @@ module VX_cache_dram_req_arb // Size of line inside a bank in bytes parameter BANK_LINE_SIZE_BYTES = 16, // Number of banks {1, 2, 4, 8,...} - parameter NUMBER_BANKS = 8, + parameter NUM_BANKS = 8, // Size of a word in bytes parameter WORD_SIZE_BYTES = 4, // Number of Word requests per cycle {1, 2, 4, 8, ...} - parameter NUMBER_REQUESTS = 2, + parameter NUM_REQUESTS = 2, // Number of cycles to complete stage 1 (read from memory) parameter STAGE_1_CYCLES = 2, @@ -54,27 +54,27 @@ module VX_cache_dram_req_arb // Fill Request - output wire dfqq_full, - input wire[NUMBER_BANKS-1:0] per_bank_dram_fill_req, - input wire[NUMBER_BANKS-1:0][31:0] per_bank_dram_fill_req_addr, + output wire dfqq_full, + input wire[NUM_BANKS-1:0] per_bank_dram_fill_req, + input wire[NUM_BANKS-1:0][31:0] per_bank_dram_fill_req_addr, // DFQ Request - output wire[NUMBER_BANKS-1:0] per_bank_dram_wb_queue_pop, - input wire[NUMBER_BANKS-1:0] per_bank_dram_wb_req, - input wire[NUMBER_BANKS-1:0][31:0] per_bank_dram_wb_req_addr, - input wire[NUMBER_BANKS-1:0][`BANK_LINE_WORDS-1:0][`WORD_SIZE-1:0] per_bank_dram_wb_req_data, - input wire[NUMBER_BANKS-1:0] per_bank_dram_because_of_snp, + output wire[NUM_BANKS-1:0] per_bank_dram_wb_queue_pop, + input wire[NUM_BANKS-1:0] per_bank_dram_wb_req, + input wire[NUM_BANKS-1:0][31:0] per_bank_dram_wb_req_addr, + input wire[NUM_BANKS-1:0][`BANK_LINE_WORDS-1:0][`WORD_SIZE-1:0] per_bank_dram_wb_req_data, + input wire[NUM_BANKS-1:0] per_bank_dram_because_of_snp, // real Dram request - output wire dram_req, - output wire dram_req_write, - output wire dram_req_read, - output wire [31:0] dram_req_addr, - output wire [31:0] dram_req_size, - output wire [`IBANK_LINE_WORDS-1:0][31:0] dram_req_data, - output wire dram_req_because_of_wb, + output wire dram_req, + output wire dram_req_write, + output wire dram_req_read, + output wire [31:0] dram_req_addr, + output wire [31:0] dram_req_size, + output wire [`IBANK_LINE_WORDS-1:0][31:0] dram_req_data, + output wire dram_req_because_of_wb, - input wire dram_req_delay + input wire dram_req_delay ); @@ -126,10 +126,10 @@ module VX_cache_dram_req_arb .dfqq_full (dfqq_full) ); - wire[`vx_clog2(NUMBER_BANKS)-1:0] dwb_bank; - // wire[NUMBER_BANKS-1:0] use_wb_valid = per_bank_dram_wb_req | per_bank_dram_because_of_snp; - wire[NUMBER_BANKS-1:0] use_wb_valid = per_bank_dram_wb_req; - VX_generic_priority_encoder #(.N(NUMBER_BANKS)) VX_sel_dwb( + wire[`LOG2UP(NUM_BANKS)-1:0] dwb_bank; + // wire[NUM_BANKS-1:0] use_wb_valid = per_bank_dram_wb_req | per_bank_dram_because_of_snp; + wire[NUM_BANKS-1:0] use_wb_valid = per_bank_dram_wb_req; + VX_generic_priority_encoder #(.N(NUM_BANKS)) VX_sel_dwb( .valids(use_wb_valid), .index (dwb_bank), .found (dwb_valid) diff --git a/hw/rtl/generic_cache/VX_cache_miss_resrv.v b/hw/rtl/generic_cache/VX_cache_miss_resrv.v index 4f13f0b9..c68dbb77 100644 --- a/hw/rtl/generic_cache/VX_cache_miss_resrv.v +++ b/hw/rtl/generic_cache/VX_cache_miss_resrv.v @@ -8,11 +8,11 @@ module VX_cache_miss_resrv // Size of line inside a bank in bytes parameter BANK_LINE_SIZE_BYTES = 16, // Number of banks {1, 2, 4, 8,...} - parameter NUMBER_BANKS = 8, + parameter NUM_BANKS = 8, // Size of a word in bytes parameter WORD_SIZE_BYTES = 4, // Number of Word requests per cycle {1, 2, 4, 8, ...} - parameter NUMBER_REQUESTS = 2, + parameter NUM_REQUESTS = 2, // Number of cycles to complete stage 1 (read from memory) parameter STAGE_1_CYCLES = 2, @@ -53,10 +53,10 @@ module VX_cache_miss_resrv input wire miss_add, input wire[31:0] miss_add_addr, input wire[`WORD_SIZE_RNG] miss_add_data, - input wire[`vx_clog2(NUMBER_REQUESTS)-1:0] miss_add_tid, + input wire[`LOG2UP(NUM_REQUESTS)-1:0] miss_add_tid, input wire[4:0] miss_add_rd, input wire[1:0] miss_add_wb, - input wire[`NW_BITS-1:0] miss_add_warp_num, + input wire[`NW_BITS-1:0] miss_add_warp_num, input wire[2:0] miss_add_mem_read, input wire[2:0] miss_add_mem_write, input wire[31:0] miss_add_pc, @@ -72,24 +72,24 @@ module VX_cache_miss_resrv output wire miss_resrv_valid_st0, output wire[31:0] miss_resrv_addr_st0, output wire[`WORD_SIZE_RNG] miss_resrv_data_st0, - output wire[`vx_clog2(NUMBER_REQUESTS)-1:0] miss_resrv_tid_st0, + output wire[`LOG2UP(NUM_REQUESTS)-1:0] miss_resrv_tid_st0, output wire[4:0] miss_resrv_rd_st0, output wire[1:0] miss_resrv_wb_st0, - output wire[`NW_BITS-1:0] miss_resrv_warp_num_st0, + output wire[`NW_BITS-1:0] miss_resrv_warp_num_st0, output wire[2:0] miss_resrv_mem_read_st0, output wire[31:0] miss_resrv_pc_st0, output wire[2:0] miss_resrv_mem_write_st0 ); - // Size of metadata = 32 + `vx_clog2(NUMBER_REQUESTS) + 5 + 2 + (`NW_BITS-1 + 1) + // Size of metadata = 32 + `LOG2UP(NUM_REQUESTS) + 5 + 2 + (`NW_BITS-1 + 1) reg[`MRVQ_METADATA_SIZE-1:0] metadata_table[MRVQ_SIZE-1:0]; reg[MRVQ_SIZE-1:0][31:0] addr_table; reg[MRVQ_SIZE-1:0][31:0] pc_table; reg[MRVQ_SIZE-1:0] valid_table; reg[MRVQ_SIZE-1:0] ready_table; - reg[`vx_clog2(MRVQ_SIZE)-1:0] head_ptr; - reg[`vx_clog2(MRVQ_SIZE)-1:0] tail_ptr; + reg[`LOG2UP(MRVQ_SIZE)-1:0] head_ptr; + reg[`LOG2UP(MRVQ_SIZE)-1:0] tail_ptr; reg[31:0] size; @@ -99,7 +99,7 @@ module VX_cache_miss_resrv assign miss_resrv_stop = (MRVQ_SIZE != 2) && (size > (MRVQ_SIZE-5)); wire enqueue_possible = !miss_resrv_full; - wire[`vx_clog2(MRVQ_SIZE)-1:0] enqueue_index = tail_ptr; + wire[`LOG2UP(MRVQ_SIZE)-1:0] enqueue_index = tail_ptr; reg[MRVQ_SIZE-1:0] make_ready; genvar curr_e; @@ -112,7 +112,7 @@ module VX_cache_miss_resrv wire dequeue_possible = valid_table[head_ptr] && ready_table[head_ptr]; - wire[`vx_clog2(MRVQ_SIZE)-1:0] dequeue_index = head_ptr; + wire[`LOG2UP(MRVQ_SIZE)-1:0] dequeue_index = head_ptr; assign miss_resrv_valid_st0 = (MRVQ_SIZE != 2) && dequeue_possible; assign miss_resrv_pc_st0 = pc_table[dequeue_index]; diff --git a/hw/rtl/generic_cache/VX_cache_req_queue.v b/hw/rtl/generic_cache/VX_cache_req_queue.v index 7de0a745..65581783 100644 --- a/hw/rtl/generic_cache/VX_cache_req_queue.v +++ b/hw/rtl/generic_cache/VX_cache_req_queue.v @@ -7,11 +7,11 @@ module VX_cache_req_queue // Size of line inside a bank in bytes parameter BANK_LINE_SIZE_BYTES = 16, // Number of banks {1, 2, 4, 8,...} - parameter NUMBER_BANKS = 8, + parameter NUM_BANKS = 8, // Size of a word in bytes parameter WORD_SIZE_BYTES = 4, // Number of Word requests per cycle {1, 2, 4, 8, ...} - parameter NUMBER_REQUESTS = 2, + parameter NUM_REQUESTS = 2, // Number of cycles to complete stage 1 (read from memory) parameter STAGE_1_CYCLES = 2, @@ -50,25 +50,25 @@ module VX_cache_req_queue // Enqueue Data input wire reqq_push, - input wire [NUMBER_REQUESTS-1:0] bank_valids, - input wire [NUMBER_REQUESTS-1:0][31:0] bank_addr, - input wire [NUMBER_REQUESTS-1:0][`WORD_SIZE_RNG] bank_writedata, + input wire [NUM_REQUESTS-1:0] bank_valids, + input wire [NUM_REQUESTS-1:0][31:0] bank_addr, + input wire [NUM_REQUESTS-1:0][`WORD_SIZE_RNG] bank_writedata, input wire [4:0] bank_rd, - input wire [NUMBER_REQUESTS-1:0][1:0] bank_wb, - input wire [`NW_BITS-1:0] bank_warp_num, - input wire [NUMBER_REQUESTS-1:0][2:0] bank_mem_read, - input wire [NUMBER_REQUESTS-1:0][2:0] bank_mem_write, + input wire [NUM_REQUESTS-1:0][1:0] bank_wb, + input wire [`NW_BITS-1:0] bank_warp_num, + input wire [NUM_REQUESTS-1:0][2:0] bank_mem_read, + input wire [NUM_REQUESTS-1:0][2:0] bank_mem_write, input wire [31:0] bank_pc, // Dequeue Data input wire reqq_pop, output wire reqq_req_st0, - output wire [`vx_clog2(NUMBER_REQUESTS)-1:0] reqq_req_tid_st0, + output wire [`LOG2UP(NUM_REQUESTS)-1:0] reqq_req_tid_st0, output wire [31:0] reqq_req_addr_st0, output wire [`WORD_SIZE_RNG] reqq_req_writedata_st0, output wire [4:0] reqq_req_rd_st0, output wire [1:0] reqq_req_wb_st0, - output wire [`NW_BITS-1:0] reqq_req_warp_num_st0, + output wire [`NW_BITS-1:0] reqq_req_warp_num_st0, output wire [2:0] reqq_req_mem_read_st0, output wire [2:0] reqq_req_mem_write_st0, output wire [31:0] reqq_req_pc_st0, @@ -78,39 +78,39 @@ module VX_cache_req_queue output wire reqq_full ); - wire [NUMBER_REQUESTS-1:0] out_per_valids; - wire [NUMBER_REQUESTS-1:0][31:0] out_per_addr; - wire [NUMBER_REQUESTS-1:0][`WORD_SIZE_RNG] out_per_writedata; - wire [4:0] out_per_rd; - wire [NUMBER_REQUESTS-1:0][1:0] out_per_wb; - wire [`NW_BITS-1:0] out_per_warp_num; - wire [NUMBER_REQUESTS-1:0][2:0] out_per_mem_read; - wire [NUMBER_REQUESTS-1:0][2:0] out_per_mem_write; - wire [31:0] out_per_pc; + wire [NUM_REQUESTS-1:0] out_per_valids; + wire [NUM_REQUESTS-1:0][31:0] out_per_addr; + wire [NUM_REQUESTS-1:0][`WORD_SIZE_RNG] out_per_writedata; + wire [4:0] out_per_rd; + wire [NUM_REQUESTS-1:0][1:0] out_per_wb; + wire [`NW_BITS-1:0] out_per_warp_num; + wire [NUM_REQUESTS-1:0][2:0] out_per_mem_read; + wire [NUM_REQUESTS-1:0][2:0] out_per_mem_write; + wire [31:0] out_per_pc; - reg [NUMBER_REQUESTS-1:0] use_per_valids; - reg [NUMBER_REQUESTS-1:0][31:0] use_per_addr; - reg [NUMBER_REQUESTS-1:0][`WORD_SIZE_RNG] use_per_writedata; - reg [4:0] use_per_rd; - reg [NUMBER_REQUESTS-1:0][1:0] use_per_wb; - reg [31:0] use_per_pc; - reg [`NW_BITS-1:0] use_per_warp_num; - reg [NUMBER_REQUESTS-1:0][2:0] use_per_mem_read; - reg [NUMBER_REQUESTS-1:0][2:0] use_per_mem_write; + reg [NUM_REQUESTS-1:0] use_per_valids; + reg [NUM_REQUESTS-1:0][31:0] use_per_addr; + reg [NUM_REQUESTS-1:0][`WORD_SIZE_RNG] use_per_writedata; + reg [4:0] use_per_rd; + reg [NUM_REQUESTS-1:0][1:0] use_per_wb; + reg [31:0] use_per_pc; + reg [`NW_BITS-1:0] use_per_warp_num; + reg [NUM_REQUESTS-1:0][2:0] use_per_mem_read; + reg [NUM_REQUESTS-1:0][2:0] use_per_mem_write; - wire [NUMBER_REQUESTS-1:0] qual_valids; - wire [NUMBER_REQUESTS-1:0][31:0] qual_addr; - wire [NUMBER_REQUESTS-1:0][`WORD_SIZE_RNG] qual_writedata; - wire [4:0] qual_rd; - wire [NUMBER_REQUESTS-1:0][1:0] qual_wb; - wire [`NW_BITS-1:0] qual_warp_num; - wire [NUMBER_REQUESTS-1:0][2:0] qual_mem_read; - wire [NUMBER_REQUESTS-1:0][2:0] qual_mem_write; - wire [31:0] qual_pc; + wire [NUM_REQUESTS-1:0] qual_valids; + wire [NUM_REQUESTS-1:0][31:0] qual_addr; + wire [NUM_REQUESTS-1:0][`WORD_SIZE_RNG] qual_writedata; + wire [4:0] qual_rd; + wire [NUM_REQUESTS-1:0][1:0] qual_wb; + wire [`NW_BITS-1:0] qual_warp_num; + wire [NUM_REQUESTS-1:0][2:0] qual_mem_read; + wire [NUM_REQUESTS-1:0][2:0] qual_mem_write; + wire [31:0] qual_pc; - reg [NUMBER_REQUESTS-1:0] updated_valids; + reg [NUM_REQUESTS-1:0] updated_valids; wire o_empty; @@ -120,7 +120,7 @@ module VX_cache_req_queue wire push_qual = reqq_push && !reqq_full; wire pop_qual = !out_empty && use_empty; - VX_generic_queue_ll #(.DATAW( (NUMBER_REQUESTS * (1+32+`WORD_SIZE)) + 5 + (NUMBER_REQUESTS*2) + (`NW_BITS-1+1) + (NUMBER_REQUESTS * (3 + 3)) + 32 ), .SIZE(REQQ_SIZE)) reqq_queue( + VX_generic_queue_ll #(.DATAW( (NUM_REQUESTS * (1+32+`WORD_SIZE)) + 5 + (NUM_REQUESTS*2) + (`NW_BITS-1+1) + (NUM_REQUESTS * (3 + 3)) + 32 ), .SIZE(REQQ_SIZE)) reqq_queue( .clk (clk), .reset (reset), .push (push_qual), @@ -132,7 +132,7 @@ module VX_cache_req_queue ); - wire[NUMBER_REQUESTS-1:0] real_out_per_valids = out_per_valids & {NUMBER_REQUESTS{~out_empty}}; + wire[NUM_REQUESTS-1:0] real_out_per_valids = out_per_valids & {NUM_REQUESTS{~out_empty}}; assign qual_valids = use_per_valids; assign qual_addr = use_per_addr; @@ -144,9 +144,9 @@ module VX_cache_req_queue assign qual_mem_write = use_per_mem_write; assign qual_pc = use_per_pc; - wire[`vx_clog2(NUMBER_REQUESTS)-1:0] qual_request_index; + wire[`LOG2UP(NUM_REQUESTS)-1:0] qual_request_index; wire qual_has_request; - VX_generic_priority_encoder #(.N(NUMBER_REQUESTS)) VX_sel_bank( + VX_generic_priority_encoder #(.N(NUM_REQUESTS)) VX_sel_bank( .valids(qual_valids), .index (qual_request_index), .found (qual_has_request) @@ -155,7 +155,7 @@ module VX_cache_req_queue assign reqq_empty = !qual_has_request; assign reqq_req_st0 = qual_has_request; assign reqq_req_tid_st0 = qual_request_index; - assign reqq_req_addr_st0 = qual_addr [qual_request_index]; + assign reqq_req_addr_st0 = qual_addr[qual_request_index]; assign reqq_req_writedata_st0 = qual_writedata[qual_request_index]; assign reqq_req_rd_st0 = qual_rd; assign reqq_req_wb_st0 = qual_wb[qual_request_index]; diff --git a/hw/rtl/generic_cache/VX_cache_wb_sel_merge.v b/hw/rtl/generic_cache/VX_cache_wb_sel_merge.v index 89f4e9b4..148365e1 100644 --- a/hw/rtl/generic_cache/VX_cache_wb_sel_merge.v +++ b/hw/rtl/generic_cache/VX_cache_wb_sel_merge.v @@ -7,11 +7,11 @@ module VX_cache_wb_sel_merge // Size of line inside a bank in bytes parameter BANK_LINE_SIZE_BYTES = 16, // Number of banks {1, 2, 4, 8,...} - parameter NUMBER_BANKS = 8, + parameter NUM_BANKS = 8, // Size of a word in bytes parameter WORD_SIZE_BYTES = 4, // Number of Word requests per cycle {1, 2, 4, 8, ...} - parameter NUMBER_REQUESTS = 2, + parameter NUM_REQUESTS = 2, // Number of cycles to complete stage 1 (read from memory) parameter STAGE_1_CYCLES = 2, // Function ID, {Dcache=0, Icache=1, Sharedmemory=2} @@ -49,52 +49,52 @@ module VX_cache_wb_sel_merge ( // Per Bank WB - input wire [NUMBER_BANKS-1:0] per_bank_wb_valid, - input wire [NUMBER_BANKS-1:0][`vx_clog2(NUMBER_REQUESTS)-1:0] per_bank_wb_tid, - input wire [NUMBER_BANKS-1:0][4:0] per_bank_wb_rd, - input wire [NUMBER_BANKS-1:0][1:0] per_bank_wb_wb, - input wire [NUMBER_BANKS-1:0][`NW_BITS-1:0] per_bank_wb_warp_num, - input wire [NUMBER_BANKS-1:0][`WORD_SIZE_RNG] per_bank_wb_data, - input wire [NUMBER_BANKS-1:0][31:0] per_bank_wb_pc, - input wire [NUMBER_BANKS-1:0][31:0] per_bank_wb_address, - output wire [NUMBER_BANKS-1:0] per_bank_wb_pop, + input wire [NUM_BANKS-1:0] per_bank_wb_valid, + input wire [NUM_BANKS-1:0][`LOG2UP(NUM_REQUESTS)-1:0] per_bank_wb_tid, + input wire [NUM_BANKS-1:0][4:0] per_bank_wb_rd, + input wire [NUM_BANKS-1:0][1:0] per_bank_wb_wb, + input wire [NUM_BANKS-1:0][`NW_BITS-1:0] per_bank_wb_warp_num, + input wire [NUM_BANKS-1:0][`WORD_SIZE_RNG] per_bank_wb_data, + input wire [NUM_BANKS-1:0][31:0] per_bank_wb_pc, + input wire [NUM_BANKS-1:0][31:0] per_bank_wb_address, + output wire [NUM_BANKS-1:0] per_bank_wb_pop, // Core Writeback - input wire core_no_wb_slot, - output reg [NUMBER_REQUESTS-1:0] core_wb_valid, - output reg [NUMBER_REQUESTS-1:0][`WORD_SIZE_RNG] core_wb_readdata, - output reg [NUMBER_REQUESTS-1:0][31:0] core_wb_pc, - output wire [4:0] core_wb_req_rd, - output wire [1:0] core_wb_req_wb, - output wire [`NW_BITS-1:0] core_wb_warp_num, - output reg [NUMBER_REQUESTS-1:0][31:0] core_wb_address + input wire core_no_wb_slot, + output reg [NUM_REQUESTS-1:0] core_wb_valid, + output reg [NUM_REQUESTS-1:0][`WORD_SIZE_RNG] core_wb_readdata, + output reg [NUM_REQUESTS-1:0][31:0] core_wb_pc, + output wire [4:0] core_wb_req_rd, + output wire [1:0] core_wb_req_wb, + output wire [`NW_BITS-1:0] core_wb_warp_num, + output reg [NUM_REQUESTS-1:0][31:0] core_wb_address ); - reg [NUMBER_BANKS-1:0] per_bank_wb_pop_unqual; - assign per_bank_wb_pop = per_bank_wb_pop_unqual & {NUMBER_BANKS{~core_no_wb_slot}}; + reg [NUM_BANKS-1:0] per_bank_wb_pop_unqual; + assign per_bank_wb_pop = per_bank_wb_pop_unqual & {NUM_BANKS{~core_no_wb_slot}}; - // wire[NUMBER_BANKS-1:0] bank_wants_wb; + // wire[NUM_BANKS-1:0] bank_wants_wb; // genvar curr_bank; // generate - // for (curr_bank = 0; curr_bank < NUMBER_BANKS; curr_bank=curr_bank+1) begin + // for (curr_bank = 0; curr_bank < NUM_BANKS; curr_bank=curr_bank+1) begin // assign bank_wants_wb[curr_bank] = (|per_bank_wb_valid[curr_bank]); // end // endgenerate - wire [(`vx_clog2(NUMBER_BANKS))-1:0] main_bank_index; + wire [`LOG2UP(NUM_BANKS)-1:0] main_bank_index; wire found_bank; - VX_generic_priority_encoder #(.N(NUMBER_BANKS)) VX_sel_bank( + VX_generic_priority_encoder #(.N(NUM_BANKS)) VX_sel_bank( .valids(per_bank_wb_valid), .index (main_bank_index), .found (found_bank) ); - assign core_wb_req_rd = per_bank_wb_rd [main_bank_index]; - assign core_wb_req_wb = per_bank_wb_wb [main_bank_index]; + assign core_wb_req_rd = per_bank_wb_rd[main_bank_index]; + assign core_wb_req_wb = per_bank_wb_wb[main_bank_index]; assign core_wb_warp_num = per_bank_wb_warp_num[main_bank_index]; integer this_bank; @@ -104,10 +104,14 @@ module VX_cache_wb_sel_merge core_wb_readdata = 0; core_wb_pc = 0; core_wb_address = 0; - for (this_bank = 0; this_bank < NUMBER_BANKS; this_bank = this_bank + 1) begin + for (this_bank = 0; this_bank < NUM_BANKS; this_bank = this_bank + 1) begin if ((FUNC_ID == `L2FUNC_ID) || (FUNC_ID == `L3FUNC_ID)) begin - if (found_bank && !core_wb_valid[per_bank_wb_tid[this_bank]] && per_bank_wb_valid[this_bank] && ((this_bank == main_bank_index) || (per_bank_wb_tid[this_bank] != per_bank_wb_tid[main_bank_index]))) begin + if (found_bank + && !core_wb_valid[per_bank_wb_tid[this_bank]] + && per_bank_wb_valid[this_bank] + && ((main_bank_index == `LOG2UP(NUM_BANKS)'(this_bank)) + || (per_bank_wb_tid[this_bank] != per_bank_wb_tid[main_bank_index]))) begin core_wb_valid[per_bank_wb_tid[this_bank]] = 1; core_wb_readdata[per_bank_wb_tid[this_bank]] = per_bank_wb_data[this_bank]; core_wb_pc[per_bank_wb_tid[this_bank]] = per_bank_wb_pc[this_bank]; @@ -119,8 +123,13 @@ module VX_cache_wb_sel_merge end else begin - - if (((this_bank == main_bank_index) || (per_bank_wb_tid[this_bank] != per_bank_wb_tid[main_bank_index])) && found_bank && !core_wb_valid[per_bank_wb_tid[this_bank]] && (per_bank_wb_valid[this_bank]) && (per_bank_wb_rd[this_bank] == per_bank_wb_rd[main_bank_index]) && (per_bank_wb_warp_num[this_bank] == per_bank_wb_warp_num[main_bank_index])) begin + if (((main_bank_index == `LOG2UP(NUM_BANKS)'(this_bank)) + || (per_bank_wb_tid[this_bank] != per_bank_wb_tid[main_bank_index])) + && found_bank + && !core_wb_valid[per_bank_wb_tid[this_bank]] + && (per_bank_wb_valid[this_bank]) + && (per_bank_wb_rd[this_bank] == per_bank_wb_rd[main_bank_index]) + && (per_bank_wb_warp_num[this_bank] == per_bank_wb_warp_num[main_bank_index])) begin core_wb_valid[per_bank_wb_tid[this_bank]] = 1; core_wb_readdata[per_bank_wb_tid[this_bank]] = per_bank_wb_data[this_bank]; core_wb_pc[per_bank_wb_tid[this_bank]] = per_bank_wb_pc[this_bank]; diff --git a/hw/rtl/generic_cache/VX_dcache_llv_resp_bank_sel.v b/hw/rtl/generic_cache/VX_dcache_llv_resp_bank_sel.v index 7eae1819..37f79d35 100644 --- a/hw/rtl/generic_cache/VX_dcache_llv_resp_bank_sel.v +++ b/hw/rtl/generic_cache/VX_dcache_llv_resp_bank_sel.v @@ -7,11 +7,11 @@ module VX_dcache_llv_resp_bank_sel // Size of line inside a bank in bytes parameter BANK_LINE_SIZE_BYTES = 16, // Number of banks {1, 2, 4, 8,...} - parameter NUMBER_BANKS = 8, + parameter NUM_BANKS = 8, // Size of a word in bytes parameter WORD_SIZE_BYTES = 4, // Number of Word requests per cycle {1, 2, 4, 8, ...} - parameter NUMBER_REQUESTS = 2, + parameter NUM_REQUESTS = 2, // Number of cycles to complete stage 1 (read from memory) parameter STAGE_1_CYCLES = 2, @@ -45,24 +45,24 @@ module VX_dcache_llv_resp_bank_sel ) ( - output reg [NUMBER_BANKS-1:0] per_bank_llvq_pop, - input wire[NUMBER_BANKS-1:0] per_bank_llvq_valid, - input wire[NUMBER_BANKS-1:0][31:0] per_bank_llvq_res_addr, - input wire[NUMBER_BANKS-1:0][`BANK_LINE_WORDS-1:0][31:0] per_bank_llvq_res_data, - input wire[NUMBER_BANKS-1:0][`vx_clog2(NUMBER_REQUESTS)-1:0] per_bank_llvq_res_tid, + output reg [NUM_BANKS-1:0] per_bank_llvq_pop, + input wire[NUM_BANKS-1:0] per_bank_llvq_valid, + input wire[NUM_BANKS-1:0][31:0] per_bank_llvq_res_addr, + input wire[NUM_BANKS-1:0][`BANK_LINE_WORDS-1:0][31:0] per_bank_llvq_res_data, + input wire[NUM_BANKS-1:0][`LOG2UP(NUM_REQUESTS)-1:0] per_bank_llvq_res_tid, - input wire llvq_pop, - output reg[NUMBER_REQUESTS-1:0] llvq_valid, - output reg[NUMBER_REQUESTS-1:0][31:0] llvq_res_addr, - output reg[NUMBER_REQUESTS-1:0][`BANK_LINE_WORDS-1:0][31:0] llvq_res_data + input wire llvq_pop, + output reg[NUM_REQUESTS-1:0] llvq_valid, + output reg[NUM_REQUESTS-1:0][31:0] llvq_res_addr, + output reg[NUM_REQUESTS-1:0][`BANK_LINE_WORDS-1:0][31:0] llvq_res_data ); - wire [(`vx_clog2(NUMBER_BANKS))-1:0] main_bank_index; + wire [(`LOG2UP(NUM_BANKS))-1:0] main_bank_index; wire found_bank; - VX_generic_priority_encoder #(.N(NUMBER_BANKS)) VX_sel_bank( + VX_generic_priority_encoder #(.N(NUM_BANKS)) VX_sel_bank( .valids(per_bank_llvq_valid), .index (main_bank_index), .found (found_bank) diff --git a/hw/rtl/generic_cache/VX_fill_invalidator.v b/hw/rtl/generic_cache/VX_fill_invalidator.v index 9448d0b1..3b4a2a5c 100644 --- a/hw/rtl/generic_cache/VX_fill_invalidator.v +++ b/hw/rtl/generic_cache/VX_fill_invalidator.v @@ -7,11 +7,11 @@ module VX_fill_invalidator // Size of line inside a bank in bytes parameter BANK_LINE_SIZE_BYTES = 16, // Number of banks {1, 2, 4, 8,...} - parameter NUMBER_BANKS = 8, + parameter NUM_BANKS = 8, // Size of a word in bytes parameter WORD_SIZE_BYTES = 4, // Number of Word requests per cycle {1, 2, 4, 8, ...} - parameter NUMBER_REQUESTS = 2, + parameter NUM_REQUESTS = 2, // Number of cycles to complete stage 1 (read from memory) parameter STAGE_1_CYCLES = 2, @@ -81,7 +81,7 @@ module VX_fill_invalidator assign matched = (|(matched_fill)); - wire [(`vx_clog2(FILL_INVALIDAOR_SIZE))-1:0] enqueue_index; + wire [(`LOG2UP(FILL_INVALIDAOR_SIZE))-1:0] enqueue_index; wire enqueue_found; VX_generic_priority_encoder #(.N(FILL_INVALIDAOR_SIZE)) VX_sel_bank( .valids(~fills_active), @@ -111,7 +111,7 @@ module VX_fill_invalidator // reg success_found; - // reg[(`vx_clog2(FILL_INVALIDAOR_SIZE))-1:0] success_index; + // reg[(`LOG2UP(FILL_INVALIDAOR_SIZE))-1:0] success_index; // integer curr_fill; // always @(*) begin @@ -136,7 +136,7 @@ module VX_fill_invalidator - // wire [(`vx_clog2(FILL_INVALIDAOR_SIZE))-1:0] enqueue_index; + // wire [(`LOG2UP(FILL_INVALIDAOR_SIZE))-1:0] enqueue_index; // wire enqueue_found; // VX_generic_priority_encoder #(.N(FILL_INVALIDAOR_SIZE)) VX_sel_bank( diff --git a/hw/rtl/generic_cache/VX_prefetcher.v b/hw/rtl/generic_cache/VX_prefetcher.v index 9a5e0fb0..043606e6 100644 --- a/hw/rtl/generic_cache/VX_prefetcher.v +++ b/hw/rtl/generic_cache/VX_prefetcher.v @@ -23,8 +23,8 @@ module VX_prefetcher ); - reg[`vx_clog2(PRFQ_STRIDE):0] use_valid; - reg[31:0] use_addr; + reg[`LOG2UP(PRFQ_STRIDE):0] use_valid; + reg[31:0] use_addr; wire current_valid; diff --git a/hw/rtl/generic_cache/VX_snp_fwd_arb.v b/hw/rtl/generic_cache/VX_snp_fwd_arb.v index e540f3b4..e22ea69d 100644 --- a/hw/rtl/generic_cache/VX_snp_fwd_arb.v +++ b/hw/rtl/generic_cache/VX_snp_fwd_arb.v @@ -2,12 +2,12 @@ module VX_snp_fwd_arb #( - parameter NUMBER_BANKS = 8 + parameter NUM_BANKS = 8 ) ( - input wire[NUMBER_BANKS-1:0] per_bank_snp_fwd, - input wire[NUMBER_BANKS-1:0][31:0] per_bank_snp_fwd_addr, - output reg[NUMBER_BANKS-1:0] per_bank_snp_fwd_pop, + input wire[NUM_BANKS-1:0] per_bank_snp_fwd, + input wire[NUM_BANKS-1:0][31:0] per_bank_snp_fwd_addr, + output reg[NUM_BANKS-1:0] per_bank_snp_fwd_pop, output wire snp_fwd, output wire[31:0] snp_fwd_addr, @@ -15,13 +15,12 @@ module VX_snp_fwd_arb ); + wire[NUM_BANKS-1:0] qual_per_bank_snp_fwd = per_bank_snp_fwd & {NUM_BANKS{!snp_fwd_delay}}; - wire[NUMBER_BANKS-1:0] qual_per_bank_snp_fwd = per_bank_snp_fwd & {NUMBER_BANKS{!snp_fwd_delay}}; - - wire[`vx_clog2(NUMBER_BANKS)-1:0] fsq_bank; + wire[`LOG2UP(NUM_BANKS)-1:0] fsq_bank; wire fsq_valid; - VX_generic_priority_encoder #(.N(NUMBER_BANKS)) VX_sel_ffsq( + VX_generic_priority_encoder #(.N(NUM_BANKS)) VX_sel_ffsq( .valids(qual_per_bank_snp_fwd), .index (fsq_bank), .found (fsq_valid) diff --git a/hw/rtl/generic_cache/VX_tag_data_access.v b/hw/rtl/generic_cache/VX_tag_data_access.v index b8330bdf..af768fb0 100644 --- a/hw/rtl/generic_cache/VX_tag_data_access.v +++ b/hw/rtl/generic_cache/VX_tag_data_access.v @@ -7,11 +7,11 @@ module VX_tag_data_access // Size of line inside a bank in bytes parameter BANK_LINE_SIZE_BYTES = 16, // Number of banks {1, 2, 4, 8,...} - parameter NUMBER_BANKS = 8, + parameter NUM_BANKS = 8, // Size of a word in bytes parameter WORD_SIZE_BYTES = 4, // Number of Word requests per cycle {1, 2, 4, 8, ...} - parameter NUMBER_REQUESTS = 2, + parameter NUM_REQUESTS = 2, // Number of cycles to complete stage 1 (read from memory) parameter STAGE_1_CYCLES = 2, // Function ID, {Dcache=0, Icache=1, Sharedmemory=2} @@ -64,7 +64,7 @@ module VX_tag_data_access input wire[2:0] mem_write_st1e, input wire[2:0] mem_read_st1e, - output wire[`WORD_SIZE_RNG] readword_st1e, + output wire[`WORD_SIZE_RNG] readword_st1e, output wire[`DBANK_LINE_WORDS-1:0][31:0] readdata_st1e, output wire[`TAG_SELECT_SIZE_RNG] readtag_st1e, output wire miss_st1e, @@ -104,9 +104,9 @@ module VX_tag_data_access VX_tag_data_structure #( .CACHE_SIZE_BYTES (CACHE_SIZE_BYTES), .BANK_LINE_SIZE_BYTES (BANK_LINE_SIZE_BYTES), - .NUMBER_BANKS (NUMBER_BANKS), + .NUM_BANKS (NUM_BANKS), .WORD_SIZE_BYTES (WORD_SIZE_BYTES), - .NUMBER_REQUESTS (NUMBER_REQUESTS), + .NUM_REQUESTS (NUM_REQUESTS), .STAGE_1_CYCLES (STAGE_1_CYCLES), .FUNC_ID (FUNC_ID), .REQQ_SIZE (REQQ_SIZE), diff --git a/hw/rtl/generic_cache/VX_tag_data_structure.v b/hw/rtl/generic_cache/VX_tag_data_structure.v index d4ded057..be81edd7 100644 --- a/hw/rtl/generic_cache/VX_tag_data_structure.v +++ b/hw/rtl/generic_cache/VX_tag_data_structure.v @@ -6,12 +6,12 @@ module VX_tag_data_structure parameter CACHE_SIZE_BYTES = 1024, // Size of line inside a bank in bytes parameter BANK_LINE_SIZE_BYTES = 16, - // Number of banks {1, 2, 4, 8,...} - parameter NUMBER_BANKS = 8, + // Number of banks {1, 2, 4, 8,...} + parameter NUM_BANKS = 8, // Size of a word in bytes parameter WORD_SIZE_BYTES = 4, // Number of Word requests per cycle {1, 2, 4, 8, ...} - parameter NUMBER_REQUESTS = 2, + parameter NUM_REQUESTS = 2, // Number of cycles to complete stage 1 (read from memory) parameter STAGE_1_CYCLES = 2, // Function ID, {Dcache=0, Icache=1, Sharedmemory=2} @@ -66,7 +66,7 @@ module VX_tag_data_structure ); - reg[`DBANK_LINE_WORDS-1:0][3:0][7:0] data [`BANK_LINE_COUNT-1:0]; + reg[`DBANK_LINE_WORDS-1:0][3:0][7:0] data [`BANK_LINE_COUNT-1:0]; reg[`TAG_SELECT_SIZE_RNG] tag [`BANK_LINE_COUNT-1:0]; reg valid[`BANK_LINE_COUNT-1:0]; reg dirty[`BANK_LINE_COUNT-1:0]; diff --git a/hw/rtl/interfaces/VX_dram_req_rsp_inter.v b/hw/rtl/interfaces/VX_dram_req_rsp_inter.v index 9ba5882f..ed94e5d7 100644 --- a/hw/rtl/interfaces/VX_dram_req_rsp_inter.v +++ b/hw/rtl/interfaces/VX_dram_req_rsp_inter.v @@ -6,18 +6,18 @@ `define VX_DRAM_REQ_RSP_INTER interface VX_dram_req_rsp_inter #( - parameter NUMBER_BANKS = 8, + parameter NUM_BANKS = 8, parameter NUM_WORDS_PER_BLOCK = 4) (); // Req wire [31:0] o_m_evict_addr; wire [31:0] o_m_read_addr; wire o_m_valid; - wire[NUMBER_BANKS - 1:0][NUM_WORDS_PER_BLOCK-1:0][31:0] o_m_writedata; + wire[NUM_BANKS - 1:0][NUM_WORDS_PER_BLOCK-1:0][31:0] o_m_writedata; wire o_m_read_or_write; // Rsp - wire[NUMBER_BANKS - 1:0][NUM_WORDS_PER_BLOCK-1:0][31:0] i_m_readdata; + wire[NUM_BANKS - 1:0][NUM_WORDS_PER_BLOCK-1:0][31:0] i_m_readdata; wire i_m_ready; diff --git a/hw/rtl/interfaces/VX_gpu_dcache_req_inter.v b/hw/rtl/interfaces/VX_gpu_dcache_req_inter.v index 2063d1b8..424f5412 100644 --- a/hw/rtl/interfaces/VX_gpu_dcache_req_inter.v +++ b/hw/rtl/interfaces/VX_gpu_dcache_req_inter.v @@ -8,23 +8,23 @@ interface VX_gpu_dcache_req_inter #( - parameter NUMBER_REQUESTS = 32 + parameter NUM_REQUESTS = 32 ) (); // Core Request - wire [NUMBER_REQUESTS-1:0] core_req_valid; - wire [NUMBER_REQUESTS-1:0][31:0] core_req_addr; - wire [NUMBER_REQUESTS-1:0][31:0] core_req_writedata; - wire [NUMBER_REQUESTS-1:0][2:0] core_req_mem_read; - wire [NUMBER_REQUESTS-1:0][2:0] core_req_mem_write; - wire [4:0] core_req_rd; - wire [NUMBER_REQUESTS-1:0][1:0] core_req_wb; - wire [`NW_BITS-1:0] core_req_warp_num; - wire [31:0] core_req_pc; + wire [NUM_REQUESTS-1:0] core_req_valid; + wire [NUM_REQUESTS-1:0][31:0] core_req_addr; + wire [NUM_REQUESTS-1:0][31:0] core_req_writedata; + wire [NUM_REQUESTS-1:0][2:0] core_req_mem_read; + wire [NUM_REQUESTS-1:0][2:0] core_req_mem_write; + wire [4:0] core_req_rd; + wire [NUM_REQUESTS-1:0][1:0] core_req_wb; + wire [`NW_BITS-1:0] core_req_warp_num; + wire [31:0] core_req_pc; // Can't WB - wire core_no_wb_slot; + wire core_no_wb_slot; endinterface diff --git a/hw/rtl/interfaces/VX_gpu_dcache_res_inter.v b/hw/rtl/interfaces/VX_gpu_dcache_res_inter.v index d6d01cb1..a39e1798 100644 --- a/hw/rtl/interfaces/VX_gpu_dcache_res_inter.v +++ b/hw/rtl/interfaces/VX_gpu_dcache_res_inter.v @@ -8,20 +8,20 @@ interface VX_gpu_dcache_res_inter #( - parameter NUMBER_REQUESTS = 32 + parameter NUM_REQUESTS = 32 ) (); // Cache WB - wire [NUMBER_REQUESTS-1:0] core_wb_valid; - wire [4:0] core_wb_req_rd; - wire [1:0] core_wb_req_wb; - wire [`NW_BITS-1:0] core_wb_warp_num; - wire [NUMBER_REQUESTS-1:0][31:0] core_wb_readdata; - wire [NUMBER_REQUESTS-1:0][31:0] core_wb_pc; + wire [NUM_REQUESTS-1:0] core_wb_valid; + wire [4:0] core_wb_req_rd; + wire [1:0] core_wb_req_wb; + wire [`NW_BITS-1:0] core_wb_warp_num; + wire [NUM_REQUESTS-1:0][31:0] core_wb_readdata; + wire [NUM_REQUESTS-1:0][31:0] core_wb_pc; // Cache Full - wire delay_req; + wire delay_req; endinterface diff --git a/hw/scripts/gen_config.py b/hw/scripts/gen_config.py index b622802b..426c83a8 100755 --- a/hw/scripts/gen_config.py +++ b/hw/scripts/gen_config.py @@ -116,11 +116,11 @@ if args.outc != 'none': #define THREADS_PER_WARP NUM_THREADS #define WARPS_PER_CORE NUM_WARPS -#define NUMBER_WI (NUM_WARPS * NUM_THREADS * NUMBER_CORES_PER_CLUSTER * NUMBER_CLUSTERS) +#define NUM_WI (NUM_WARPS * NUM_THREADS * NUM_CORES_PER_CLUSTER * NUM_CLUSTERS) // legacy -#define TOTAL_THREADS NUMBER_WI -#define TOTAL_WARPS (NUM_WARPS * NUMBER_CORES_PER_CLUSTER * NUMBER_CLUSTERS) +#define TOTAL_THREADS NUM_WI +#define TOTAL_WARPS (NUM_WARPS * NUM_CORES_PER_CLUSTER * NUM_CLUSTERS) // COLORS #define GREEN "\\033[32m" diff --git a/hw/scripts/gen_synth_configs.py b/hw/scripts/gen_synth_configs.py index 8bb7ccc9..0b42d88a 100755 --- a/hw/scripts/gen_synth_configs.py +++ b/hw/scripts/gen_synth_configs.py @@ -10,8 +10,8 @@ template = """ export V_NT={threads} export V_NW={warps} -export V_NUMBER_CORES_PER_CLUSTER={cores} -export V_NUMBER_CLUSTERS={clusters} +export V_NUM_CORES_PER_CLUSTER={cores} +export V_NUM_CLUSTERS={clusters} export V_DCACHE_SIZE_BYTES={dcachek} export V_ICACHE_SIZE_BYTES={icachek} diff --git a/hw/simulate/simulator.cpp b/hw/simulate/simulator.cpp index 732b2d71..4046c1ce 100644 --- a/hw/simulate/simulator.cpp +++ b/hw/simulate/simulator.cpp @@ -351,13 +351,13 @@ void Simulator::send_snoops(uint32_t mem_addr, uint32_t size) { } void Simulator::flush_caches(uint32_t mem_addr, uint32_t size) { - printf("[sim] total cycles: %lld\n", this->total_cycles_); + printf("[sim] total cycles: %ld\n", this->total_cycles_); // send snoops for L1 flush this->send_snoops(mem_addr, size); this->wait(PIPELINE_FLUSH_LATENCY); -// #if NUMBER_CORES != 1 +// #if NUM_CORES != 1 // send snoops for L2 flush // this->send_snoops(mem_addr, size); // this->wait(PIPELINE_FLUSH_LATENCY); diff --git a/hw/simulate/simulator.h b/hw/simulate/simulator.h index 97766deb..80c5a930 100644 --- a/hw/simulate/simulator.h +++ b/hw/simulate/simulator.h @@ -13,7 +13,7 @@ #include #endif -#include "VX_define.h" +#include "VX_config.h" #include "ram.h" #include @@ -56,7 +56,7 @@ private: void send_snoops(uint32_t mem_addr, uint32_t size); void wait(uint32_t cycles); - uint64_t total_cycles_; + int64_t total_cycles_; bool dram_stalled_; bool I_dram_stalled_; std::vector dram_req_vec_; diff --git a/hw/syn/yosys/diagram.ys b/hw/syn/yosys/diagram.ys new file mode 100644 index 00000000..ffa3808c --- /dev/null +++ b/hw/syn/yosys/diagram.ys @@ -0,0 +1,5 @@ +# load design +read_verilog -sv -I../../rtl -I../../rtl/interfaces -I../../rtl/cache -I../../rtl/generic_cache -I../../rtl/shared_memory -I../../rtl/pipe_regs -I../../rtl/compat ../../rtl/Vortex.v + +# dump diagram +show diff --git a/hw/syn/yosys/synthesis.ys b/hw/syn/yosys/synthesis.ys new file mode 100644 index 00000000..cf285a67 --- /dev/null +++ b/hw/syn/yosys/synthesis.ys @@ -0,0 +1,27 @@ +# load design +read_verilog -sv -I../../rtl -I../../rtl/interfaces -I../../rtl/cache -I../../rtl/generic_cache -I../../rtl/shared_memory -I../../rtl/pipe_regs -I../../rtl/compat ../../rtl/Vortex.v + +# high-level synthesis +proc; opt; fsm;; memory -nomap; opt + +# substitute block rams +techmap -map map_rams.v + +# map remaining memories +memory_map + +# low-level synthesis +techmap; opt; flatten;; abc -lut6 +techmap -map map_xl_cells.v + +# add clock buffers +select -set xl_clocks t:FDRE %x:+FDRE[C] t:FDRE %d +iopadmap -inpad BUFGP O:I @xl_clocks + +# add io buffers +select -set xl_nonclocks w:* t:BUFGP %x:+BUFGP[I] %d +iopadmap -outpad OBUF I:O -inpad IBUF O:I @xl_nonclocks + +# write synthesis results +write_edif synth.edif + diff --git a/simX/include/core.h b/simX/include/core.h index 77e4bf41..19087a18 100644 --- a/simX/include/core.h +++ b/simX/include/core.h @@ -19,9 +19,9 @@ #include "Vcache_simX.h" #include "verilated.h" -// #ifdef VCD_OUTPUT +#ifdef VCD_OUTPUT #include -// #endif +#endif #include "trace.h"