scope refactoring: adding modules definitions to VCD trace

driver/opae/Makefile

@@ -24,13 +24,6 @@ CXXFLAGS += -fPIC
 # Dump perf stats
 CXXFLAGS += -DDUMP_PERF_STATS
 
-# Enable scope analyzer
-# Enable scope analyzer
-ifdef SCOPE
-	CXXFLAGS += -DSCOPE
-	SET_SCOPE = SCOPE=1
-endif
-
 LDFLAGS += -shared
 
 FPGA_LIBS += -luuid -lopae-c
@@ -53,7 +46,14 @@ PROJECT_VLSIM = $(VLSIM_DIR)/libvortex.so
 
 AFU_JSON_INFO = vortex_afu.h
 
-SRCS = vortex.cpp vx_scope.cpp ../common/vx_utils.cpp
+SRCS = vortex.cpp ../common/vx_utils.cpp
+
+# Enable scope analyzer
+ifdef SCOPE
+	CXXFLAGS += -DSCOPE	
+	SRCS += vx_scope.cpp
+	SET_SCOPE = SCOPE=1
+endif
 
 all: vlsim
 
@@ -64,7 +64,7 @@ json: ../../hw/opae/vortex_afu.json
 fpga: $(SRCS)
 	$(CXX) $(CXXFLAGS) $^ $(LDFLAGS) $(FPGA_LIBS) -o $(PROJECT)
 
-ase: $(SRCS) $(ASE_DIR)
+asesim: $(SRCS) $(ASE_DIR)
 	$(CXX) $(CXXFLAGS) -DUSE_ASE $(SRCS) $(LDFLAGS) $(ASE_LIBS) -o $(PROJECT_ASE)
 
 vlsim: $(SRCS) opae-vlsim

driver/opae/vlsim/Makefile

@@ -20,10 +20,10 @@ DBG_FLAGS += -DDBG_CORE_REQ_INFO
 
 #CONFIGS += -DNUM_CLUSTERS=2 -DNUM_CORES=4 -DL2_ENABLE=1
 #CONFIGS += -DNUM_CLUSTERS=1 -DNUM_CORES=4 -DL2_ENABLE=1
-#CONFIGS += -DNUM_CLUSTERS=1 -DNUM_CORES=2 -DL2_ENABLE=0
-CONFIGS += -DNUM_CLUSTERS=1 -DNUM_CORES=1
+CONFIGS += -DNUM_CLUSTERS=1 -DNUM_CORES=2 -DL2_ENABLE=0
+#CONFIGS += -DNUM_CLUSTERS=1 -DNUM_CORES=1
 
-DEBUG=1
+#DEBUG=1
 SCOPE=1
 
 CFLAGS += -fPIC

driver/opae/vlsim/vortex_afu_shim.sv

@@ -87,7 +87,7 @@ t_if_ccip_Tx af2cp_sTxPort;
 
 vortex_afu #(
   .NUM_LOCAL_MEM_BANKS(NUM_LOCAL_MEM_BANKS)
-) vortex_afu (
+) afu (
     .clk(clk),
     .reset(reset),
     .cp2af_sRxPort(cp2af_sRxPort),

driver/opae/vortex.cpp

@@ -509,12 +509,6 @@ extern int vx_start(vx_device_h hdevice) {
     // start execution    
     CHECK_RES(fpgaWriteMMIO64(device->fpga, 0, MMIO_CMD_TYPE, CMD_RUN));
 
-/*#ifdef SCOPE
-    sleep(15);
-    vx_scope_stop(device->fpga, 0);
-    exit(0);
-#endif*/
-
     return 0;
 }
 
@@ -547,7 +541,7 @@ extern int vx_csr_get(vx_device_h hdevice, int core_id, int addr, unsigned* valu
 
     // Ensure ready for new command
     if (vx_ready_wait(hdevice, -1) != 0)
-        return -1; 
+        return -1;
 
     // write CSR value    
     CHECK_RES(fpgaWriteMMIO64(device->fpga, 0, MMIO_CSR_CORE, core_id));

driver/opae/vx_scope.cpp

@@ -4,6 +4,9 @@
 #include <chrono>
 #include <vector>
 #include <assert.h>
+#include <chrono>
+#include <thread>
+#include <mutex>
 
 #ifdef USE_VLSIM
 #include "vlsim/fpga.h"
@@ -39,14 +42,30 @@
 #define CMD_SET_STOP    5
 #define CMD_GET_OFFSET  6
 
-static constexpr int num_signals = sizeof(scope_signals) / sizeof(scope_signal_t);
+static constexpr int num_modules = sizeof(scope_modules) / sizeof(scope_module_t);
+
+static constexpr int num_signals = sizeof(scope_taps) / sizeof(scope_tap_t);
 
 constexpr int calcFrameWidth(int index = 0) {
-    return (index < num_signals) ? (scope_signals[index].width + calcFrameWidth(index + 1)) : 0;
+    return (index < num_signals) ? (scope_taps[index].width + calcFrameWidth(index + 1)) : 0;
 }
 
 static constexpr int fwidth = calcFrameWidth();
 
+#ifdef HANG_TIMEOUT
+static std::thread g_timeout_thread;
+static std::mutex g_timeout_mutex;
+
+static void timeout_callback(fpga_handle fpga) {
+    std::this_thread::sleep_for(std::chrono::seconds{60});
+    if (!g_timeout_mutex.try_lock())
+        return;
+    vx_scope_stop(fpga, HANG_TIMEOUT);
+    fpgaClose(fpga);
+    exit(0);
+}
+#endif
+
 uint64_t print_clock(std::ofstream& ofs, uint64_t delta, uint64_t timestamp) {
     while (delta != 0) {
         ofs << '#' << timestamp++ << std::endl;
@@ -58,6 +77,27 @@ uint64_t print_clock(std::ofstream& ofs, uint64_t delta, uint64_t timestamp) {
     return timestamp;
 }
 
+void dump_taps(std::ofstream& ofs, int module) {
+    int i = 1;
+     for (auto& tap : scope_taps) {
+        if (tap.module != module)
+            continue;
+        ofs << "$var reg " << tap.width << " " << i << " " << tap.name << " $end" << std::endl;        
+        i += 1;
+    }
+}
+
+void dump_module(std::ofstream& ofs, int parent) {
+    for (auto& module : scope_modules) {
+        if (module.parent != parent)
+            continue;
+        ofs << "$scope module " << module.name << " $end" << std::endl;
+        dump_module(ofs, module.index);
+        dump_taps(ofs, module.index);
+        ofs << "$upscope $end" << std::endl;
+    }
+}
+
 int vx_scope_start(fpga_handle hfpga, uint64_t delay) {    
     if (nullptr == hfpga)
         return -1;  
@@ -69,10 +109,20 @@ int vx_scope_start(fpga_handle hfpga, uint64_t delay) {
         std::cout << "scope start delay: " << delay << std::endl;
     }
 
+#ifdef HANG_TIMEOUT
+    g_timeout_thread = std::thread(timeout_callback, hfpga);
+    g_timeout_thread.detach();
+#endif
+
     return 0;
 }
 
 int vx_scope_stop(fpga_handle hfpga, uint64_t delay) {    
+#ifdef HANG_TIMEOUT
+    if (!g_timeout_mutex.try_lock())
+        return 0;
+#endif
+
     if (nullptr == hfpga)
         return -1;
     
@@ -89,11 +139,8 @@ int vx_scope_stop(fpga_handle hfpga, uint64_t delay) {
     ofs << "$timescale 1 ns $end" << std::endl;
     ofs << "$scope module TOP $end" << std::endl;
     ofs << "$var reg 1 0 clk $end" << std::endl;
-
-    for (int i = 0; i < num_signals; ++i) {
-        ofs << "$var reg " << scope_signals[i].width << " " << (i+1) << " " << scope_signals[i].name << " $end" << std::endl;
-    }
-
+    dump_module(ofs, -1);
+    dump_taps(ofs, -1);
     ofs << "$upscope $end" << std::endl;
     ofs << "enddefinitions $end" << std::endl;
     
@@ -158,7 +205,7 @@ int vx_scope_stop(fpga_handle hfpga, uint64_t delay) {
         CHECK_RES(fpgaReadMMIO64(hfpga, 0, MMIO_SCOPE_READ, &word));
         
         do {          
-            int signal_width = scope_signals[signal_id-1].width;
+            int signal_width = scope_taps[signal_id-1].width;
             int word_offset = frame_offset % 64;
 
             signal_data[signal_width - signal_offset - 1] = ((word >> word_offset) & 0x1) ? '1' : '0';
@@ -183,7 +230,9 @@ int vx_scope_stop(fpga_handle hfpga, uint64_t delay) {
                     CHECK_RES(fpgaReadMMIO64(hfpga, 0, MMIO_SCOPE_READ, &delta));
                     timestamp = print_clock(ofs, delta + 1, timestamp);            
                     signal_id = num_signals;
-                    //std::cout << "*** " << frame_no << " frames, timestamp=" << timestamp << std::endl;
+                    if (0 == (frame_no % 100)) {
+                        std::cout << "*** " << frame_no << " frames, timestamp=" << timestamp << std::endl;
+                    }
                 }                     
             }
             

driver/opae/vx_scope.h

@@ -1,5 +1,7 @@
 #pragma once
 
+#define HANG_TIMEOUT 60
+
 int vx_scope_start(fpga_handle hfpga, uint64_t delay = -1);
 
 int vx_scope_stop(fpga_handle hfpga, uint64_t delay = -1);