rtl gpr multicore fix
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8
hw/rtl/cache/VX_cache_config.vh
vendored
8
hw/rtl/cache/VX_cache_config.vh
vendored
@@ -12,10 +12,14 @@
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`define BYTE_EN_BITS 3
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// data tid tag read write base addr
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`define MRVQ_METADATA_WIDTH (`WORD_WIDTH + `LOG2UP(NUM_REQUESTS) + CORE_TAG_WIDTH + `BYTE_EN_BITS + `BYTE_EN_BITS + `BASE_ADDR_BITS)
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`define MRVQ_METADATA_WIDTH (`WORD_WIDTH + `REQS_BITS + CORE_TAG_WIDTH + `BYTE_EN_BITS + `BYTE_EN_BITS + `BASE_ADDR_BITS)
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// tag read write reqs
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`define REQ_INST_META_WIDTH (CORE_TAG_WIDTH + `BYTE_EN_BITS + `BYTE_EN_BITS + `LOG2UP(NUM_REQUESTS))
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`define REQ_INST_META_WIDTH (CORE_TAG_WIDTH + `BYTE_EN_BITS + `BYTE_EN_BITS + `REQS_BITS)
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`define REQS_BITS `LOG2UP(NUM_REQUESTS)
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`define BANK_BITS `LOG2UP(NUM_BANKS)
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`define WORD_WIDTH (8 * WORD_SIZE)
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`define BYTE_WIDTH (`WORD_WIDTH / 4)
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