riscv-tests work on simx
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@@ -49,7 +49,7 @@ static const char* op_string(const Instr &instr) {
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HalfWord func3 = instr.getFunc3();
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HalfWord func7 = instr.getFunc7();
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HalfWord rs2 = instr.getRSrc(1);
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HalfWord imm = instr.getImm();
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Word imm = instr.getImm();
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switch (instr.getOpcode()) {
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case Opcode::NOP: return "NOP";
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case Opcode::LUI_INST: return "LUI";
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@@ -394,7 +394,7 @@ std::shared_ptr<Instr> Decoder::decode(HalfWord code, HalfWord PC) {
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instr->setSrcReg(rs2);
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}
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instr->setFunc3(func3);
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HalfWord imeed = (func7 << reg_s_) | rd;
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Word imeed = (func7 << reg_s_) | rd;
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instr->setImm(signExt(imeed, 12, s_imm_mask_));
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} break;
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@@ -406,7 +406,7 @@ std::shared_ptr<Instr> Decoder::decode(HalfWord code, HalfWord PC) {
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HalfWord bits_4_1 = rd >> 1;
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HalfWord bit_10_5 = func7 & 0x3f;
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HalfWord bit_12 = func7 >> 6;
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HalfWord imeed = (bits_4_1 << 1) | (bit_10_5 << 5) | (bit_11 << 11) | (bit_12 << 12);
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Word imeed = (bits_4_1 << 1) | (bit_10_5 << 5) | (bit_11 << 11) | (bit_12 << 12);
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instr->setImm(signExt(imeed, 13, b_imm_mask_));
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} break;
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@@ -422,7 +422,7 @@ std::shared_ptr<Instr> Decoder::decode(HalfWord code, HalfWord PC) {
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HalfWord bit_11 = (unordered >> 8) & 0x1;
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HalfWord bits_10_1 = (unordered >> 9) & 0x3ff;
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HalfWord bit_20 = (unordered >> 19) & 0x1;
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HalfWord imeed = 0 | (bits_10_1 << 1) | (bit_11 << 11) | (bits_19_12 << 12) | (bit_20 << 20);
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Word imeed = 0 | (bits_10_1 << 1) | (bit_11 << 11) | (bits_19_12 << 12) | (bit_20 << 20);
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if (bit_20) {
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imeed |= ~j_imm_mask_;
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}
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