From 382585d33d0de89f47a52034c0a1a2bf581f48fc Mon Sep 17 00:00:00 2001 From: Blaise Tine Date: Sat, 17 Jul 2021 07:22:16 -0700 Subject: [PATCH] minor update --- hw/rtl/VX_decode.v | 2 +- hw/rtl/VX_icache_stage.v | 4 ++-- hw/rtl/interfaces/VX_ifetch_rsp_if.v | 2 +- 3 files changed, 4 insertions(+), 4 deletions(-) diff --git a/hw/rtl/VX_decode.v b/hw/rtl/VX_decode.v index dd6569d6..54257679 100644 --- a/hw/rtl/VX_decode.v +++ b/hw/rtl/VX_decode.v @@ -40,7 +40,7 @@ module VX_decode #( reg is_join, is_wstall; reg [`NUM_REGS-1:0] used_regs; - wire [31:0] instr = ifetch_rsp_if.instr; + wire [31:0] instr = ifetch_rsp_if.data; wire [6:0] opcode = instr[6:0]; wire [2:0] func3 = instr[14:12]; wire [6:0] func7 = instr[31:25]; diff --git a/hw/rtl/VX_icache_stage.v b/hw/rtl/VX_icache_stage.v index 75688a68..74965c56 100644 --- a/hw/rtl/VX_icache_stage.v +++ b/hw/rtl/VX_icache_stage.v @@ -62,7 +62,7 @@ module VX_icache_stage #( assign ifetch_rsp_if.tmask = rsp_tmask; assign ifetch_rsp_if.wid = rsp_tag; assign ifetch_rsp_if.PC = rsp_PC; - assign ifetch_rsp_if.instr = icache_rsp_if.data; + assign ifetch_rsp_if.data = icache_rsp_if.data; // Can accept new response? assign icache_rsp_if.ready = ifetch_rsp_if.ready; @@ -81,7 +81,7 @@ module VX_icache_stage #( $display("%t: I$%0d req: wid=%0d, PC=%0h", $time, CORE_ID, ifetch_req_if.wid, ifetch_req_if.PC); end if (icache_rsp_if.valid && icache_rsp_if.ready) begin - $display("%t: I$%0d rsp: wid=%0d, PC=%0h, instr=%0h", $time, CORE_ID, ifetch_rsp_if.wid, ifetch_rsp_if.PC, ifetch_rsp_if.instr); + $display("%t: I$%0d rsp: wid=%0d, PC=%0h, data=%0h", $time, CORE_ID, ifetch_rsp_if.wid, ifetch_rsp_if.PC, ifetch_rsp_if.data); end end `endif diff --git a/hw/rtl/interfaces/VX_ifetch_rsp_if.v b/hw/rtl/interfaces/VX_ifetch_rsp_if.v index 4991f462..78706577 100644 --- a/hw/rtl/interfaces/VX_ifetch_rsp_if.v +++ b/hw/rtl/interfaces/VX_ifetch_rsp_if.v @@ -9,7 +9,7 @@ interface VX_ifetch_rsp_if (); wire [`NUM_THREADS-1:0] tmask; wire [`NW_BITS-1:0] wid; wire [31:0] PC; - wire [31:0] instr; + wire [31:0] data; wire ready; endinterface