From 3e68c8bcf5344dcae218d65195307b0562b95dc5 Mon Sep 17 00:00:00 2001 From: wgulian3 Date: Tue, 18 Feb 2020 13:38:17 -0500 Subject: [PATCH] verilator does not support delayed assignment in a loop --- rtl/VX_csr_data.v | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/rtl/VX_csr_data.v b/rtl/VX_csr_data.v index 30382d2b..2a3c5641 100644 --- a/rtl/VX_csr_data.v +++ b/rtl/VX_csr_data.v @@ -57,7 +57,12 @@ module VX_csr_data ( always @(posedge clk or posedge reset) begin if (reset) begin for (curr_e = 0; curr_e < 1024; curr_e=curr_e+1) begin +`ifdef VERILATOR + // - Verilator does not support delayed assignment in loops. + csr[curr_e] = 0; +`else csr[curr_e] <= 0; +`endif end cycle <= 0; instret <= 0; @@ -74,9 +79,9 @@ module VX_csr_data ( assign out_read_csr_data = read_cycle ? cycle[31:0] : - read_cycleh ? cycle[63:32] : + read_cycleh ? cycle[63:32] : read_instret ? instret[31:0] : - read_instreth ? instret[63:32] : + read_instreth ? instret[63:32] : {{20{1'b0}}, csr[in_read_csr_address]}; -endmodule +endmodule : VX_csr_data