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CSRs I/O refactoring

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This commit is contained in:
Blaise Tine
2021-06-11 03:08:07 -07:00
parent a46d6cb606
commit 3cc1190cd7
33 changed files with 881 additions and 1385 deletions
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2
runtime/Makefile
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@@ -10,7 +10,7 @@ CFLAGS += -I./include -I../hw
PROJECT = libvortexrt
SRCS = ./src/vx_start.S ./src/vx_print.S ./src/vx_print.c ./src/vx_spawn.c
SRCS = ./src/vx_start.S ./src/vx_print.S ./src/vx_print.c ./src/vx_spawn.c ./src/vx_perf.c
OBJS := $(addsuffix .o, $(notdir $(SRCS)))

59
runtime/include/vx_intrinsics.h
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@@ -7,6 +7,51 @@
extern "C" {
#endif
#ifdef __ASSEMBLY__
#define __ASM_STR(x) x
#else
#define __ASM_STR(x) #x
#endif
#define vx_csr_swap(csr, val) ({ \
unsigned __v = (unsigned )(val); \
__asm__ __volatile__ ("csrrw %0, " __ASM_STR(csr) ", %1" : "=r" (__v) : "rK" (__v) : "memory"); \
__v; \
})
#define vx_csr_read(csr) ({ \
register unsigned __v; \
__asm__ __volatile__ ("csrr %0, " __ASM_STR(csr) : "=r" (__v) :: "memory"); \
__v; \
})
#define vx_csr_write(csr, val) ({ \
unsigned __v = (unsigned )(val); \
__asm__ __volatile__ ("csrw " __ASM_STR(csr) ", %0" :: "rK" (__v) : "memory"); \
})
#define vx_csr_read_set(csr, val) ({ \
unsigned __v = (unsigned )(val); \
__asm__ __volatile__ ("csrrs %0, " __ASM_STR(csr) ", %1" : "=r" (__v) : "rK" (__v) : "memory"); \
__v; \
})
#define vx_csr_set(csr, val) ({ \
unsigned __v = (unsigned )(val); \
__asm__ __volatile__ ("csrs " __ASM_STR(csr) ", %0" :: "rK" (__v) : "memory"); \
})
#define vx_csr_read_clear(csr, val) ({ \
unsigned __v = (unsigned )(val); \
__asm__ __volatile__ ("csrrc %0, " __ASM_STR(csr) ", %1" : "=r" (__v) : "rK" (__v) : "memory"); \
__v; \
})
#define vx_csr_clear(csr, val) ({ \
unsigned __v = (unsigned )(val); \
__asm__ __volatile__ ("csrc " __ASM_STR(csr) ", %0" :: "rK" (__v) : "memory"); \
})
// Set thread mask
inline void vx_tmc(unsigned num_threads) {
asm volatile (".insn s 0x6b, 0, x0, 0(%0)" :: "r"(num_threads));
@@ -95,20 +140,6 @@ inline int vx_num_cores() {
return result;
}
// Return the number of cycles
inline int vx_num_cycles() {
int result;
asm volatile ("csrr %0, %1" : "=r"(result) : "i"(CSR_CYCLE));
return result;
}
// Return the number of instructions
inline int vx_num_instrs() {
int result;
asm volatile ("csrr %0, %1" : "=r"(result) : "i"(CSR_INSTRET));
return result;
}
#define __if(b) vx_split(b); \
if (b)

27
runtime/src/vx_perf.c Normal file
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@@ -0,0 +1,27 @@
#include <VX_config.h>
#include <vx_intrinsics.h>
#include <stdint.h>
#define DUMP_CSR_4(d, s) \
csr_mem[d + 0] = vx_csr_read(s + 0); \
csr_mem[d + 1] = vx_csr_read(s + 1); \
csr_mem[d + 2] = vx_csr_read(s + 2); \
csr_mem[d + 3] = vx_csr_read(s + 3);
#define DUMP_CSR_32(d, s) \
DUMP_CSR_4(d + 0, s + 0) \
DUMP_CSR_4(d + 4, s + 4) \
DUMP_CSR_4(d + 8, s + 8) \
DUMP_CSR_4(d + 12, s + 12) \
DUMP_CSR_4(d + 16, s + 16) \
DUMP_CSR_4(d + 20, s + 20) \
DUMP_CSR_4(d + 24, s + 24) \
DUMP_CSR_4(d + 28, s + 28)
void vx_perf_dump() {
int core_id = vx_core_id();
uint32_t* const csr_mem = (uint32_t*)(IO_ADDR_CSR + 64 * sizeof(uint32_t) * core_id);
DUMP_CSR_32(0, CSR_MPM_BASE)
DUMP_CSR_32(32, CSR_MPM_BASE_H)
}

3
runtime/src/vx_start.S
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@@ -42,6 +42,9 @@ _start:
.type _exit, @function
.global _exit
_exit:
# dump performance CSRs
call vx_perf_dump
# disable all threads in current warp
li a0, 0
.insn s 0x6b, 0, x0, 0(a0) # tmc a0