tensor: Properly guard tc_rf_if for non-hopper
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@@ -63,7 +63,9 @@ module VX_core import VX_gpu_pkg::*; #(
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VX_decode_if decode_if();
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VX_decode_if decode_if();
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VX_sched_csr_if sched_csr_if();
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VX_sched_csr_if sched_csr_if();
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VX_decode_sched_if decode_sched_if();
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VX_decode_sched_if decode_sched_if();
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`ifdef EXT_T_HOPPER
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VX_tc_rf_if tensor_regfile_if();
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VX_tc_rf_if tensor_regfile_if();
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`endif
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VX_commit_sched_if commit_sched_if();
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VX_commit_sched_if commit_sched_if();
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VX_commit_csr_if commit_csr_if();
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VX_commit_csr_if commit_csr_if();
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VX_branch_ctl_if branch_ctl_if[`NUM_ALU_BLOCKS]();
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VX_branch_ctl_if branch_ctl_if[`NUM_ALU_BLOCKS]();
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@@ -90,8 +90,12 @@ module VX_issue import VX_gpu_pkg::*; #(
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.reset (operands_reset),
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.reset (operands_reset),
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.writeback_if (writeback_if),
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.writeback_if (writeback_if),
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.scoreboard_if (scoreboard_if),
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.scoreboard_if (scoreboard_if),
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`ifdef EXT_T_HOPPER
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.operands_if (operands_if),
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.operands_if (operands_if),
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.tensor_regfile_if (tensor_regfile_if)
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.tensor_regfile_if (tensor_regfile_if)
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`else
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.operands_if (operands_if)
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`endif
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);
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);
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VX_dispatch #(
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VX_dispatch #(
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@@ -24,7 +24,9 @@ module VX_operands_dup import VX_gpu_pkg::*; #(
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VX_writeback_if.slave writeback_if [`ISSUE_WIDTH],
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VX_writeback_if.slave writeback_if [`ISSUE_WIDTH],
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VX_ibuffer_if.slave scoreboard_if [`ISSUE_WIDTH],
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VX_ibuffer_if.slave scoreboard_if [`ISSUE_WIDTH],
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`ifdef EXT_T_HOPPER
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VX_tc_rf_if.slave tensor_regfile_if,
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VX_tc_rf_if.slave tensor_regfile_if,
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`endif
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VX_operands_if.master operands_if [`ISSUE_WIDTH]
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VX_operands_if.master operands_if [`ISSUE_WIDTH]
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);
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);
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`UNUSED_PARAM (CORE_ID)
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`UNUSED_PARAM (CORE_ID)
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@@ -50,11 +52,13 @@ module VX_operands_dup import VX_gpu_pkg::*; #(
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// because NUM_BLOCKS == 1
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// because NUM_BLOCKS == 1
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wire [`NUM_THREADS-1:0][`XLEN-1:0] tc_rf_data [`ISSUE_WIDTH];
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wire [`NUM_THREADS-1:0][`XLEN-1:0] tc_rf_data [`ISSUE_WIDTH];
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`ifdef EXT_T_HOPPER
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`STATIC_ASSERT((ISSUE_RATIO == 1),
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`STATIC_ASSERT((ISSUE_RATIO == 1),
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("static assertion failed: tensor core only supports ISSUE_RATIO == 1"))
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("static assertion failed: tensor core only supports ISSUE_RATIO == 1"))
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assign tc_rf_valid = '{`ISSUE_WIDTH{tensor_regfile_if.req_valid}};
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assign tc_rf_valid = '{`ISSUE_WIDTH{tensor_regfile_if.req_valid}};
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assign tc_rf_addr = '{`ISSUE_WIDTH{tensor_regfile_if.req_data.rs}};
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assign tc_rf_addr = '{`ISSUE_WIDTH{tensor_regfile_if.req_data.rs}};
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assign tensor_regfile_if.rsp_data.data = tc_rf_data[0];
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assign tensor_regfile_if.rsp_data.data = tc_rf_data[0];
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`endif
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for (genvar i = 0; i < `ISSUE_WIDTH; ++i) begin
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for (genvar i = 0; i < `ISSUE_WIDTH; ++i) begin
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@@ -113,7 +117,11 @@ module VX_operands_dup import VX_gpu_pkg::*; #(
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.size (size1[i])
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.size (size1[i])
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);
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);
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assign operands_if[i].valid = ~empty1[i];
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assign operands_if[i].valid = ~empty1[i];
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`ifdef EXT_T_HOPPER
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assign scoreboard_if[i].ready = (size1[i] < 3'd2) && ~tc_rf_valid[i];
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assign scoreboard_if[i].ready = (size1[i] < 3'd2) && ~tc_rf_valid[i];
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`else
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assign scoreboard_if[i].ready = (size1[i] < 3'd2);
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`endif
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// assert (full1[i] == full2[i]);
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// assert (full1[i] == full2[i]);
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// assert (empty1[i] == empty2[i]);
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// assert (empty1[i] == empty2[i]);
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@@ -153,7 +161,9 @@ module VX_operands_dup import VX_gpu_pkg::*; #(
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`UNUSED_PIN (alm_full),
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`UNUSED_PIN (alm_full),
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`UNUSED_PIN (size)
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`UNUSED_PIN (size)
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);
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);
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`ifdef EXT_T_HOPPER
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assign tc_rf_data[i][j] = rs3_data[j];
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assign tc_rf_data[i][j] = rs3_data[j];
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`endif
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end
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end
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// GPR banks
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// GPR banks
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@@ -179,7 +189,11 @@ module VX_operands_dup import VX_gpu_pkg::*; #(
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assign gpr_wr_addr = {writeback_if[i].data.wis, writeback_if[i].data.rd};
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assign gpr_wr_addr = {writeback_if[i].data.wis, writeback_if[i].data.rd};
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assign gpr_rd_addr_rs1 = {scoreboard_if[i].data.wis, scoreboard_if[i].data.rs1};
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assign gpr_rd_addr_rs1 = {scoreboard_if[i].data.wis, scoreboard_if[i].data.rs1};
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assign gpr_rd_addr_rs2 = {scoreboard_if[i].data.wis, scoreboard_if[i].data.rs2};
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assign gpr_rd_addr_rs2 = {scoreboard_if[i].data.wis, scoreboard_if[i].data.rs2};
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`ifdef EXT_T_HOPPER
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assign gpr_rd_addr_rs3 = tc_rf_valid[i] ? tc_rf_addr[i] : {scoreboard_if[i].data.wis, scoreboard_if[i].data.rs3};
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assign gpr_rd_addr_rs3 = tc_rf_valid[i] ? tc_rf_addr[i] : {scoreboard_if[i].data.wis, scoreboard_if[i].data.rs3};
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`else
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assign gpr_rd_addr_rs3 = {scoreboard_if[i].data.wis, scoreboard_if[i].data.rs3};
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`endif
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// always @(posedge clk) begin
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// always @(posedge clk) begin
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// if (reset) begin
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// if (reset) begin
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// gpr_rd_addr_rs1 <= '0;
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// gpr_rd_addr_rs1 <= '0;
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@@ -198,7 +212,11 @@ module VX_operands_dup import VX_gpu_pkg::*; #(
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assign gpr_wr_addr = writeback_if[i].data.rd;
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assign gpr_wr_addr = writeback_if[i].data.rd;
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assign gpr_rd_addr_rs1 = scoreboard_if[i].data.rs1;
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assign gpr_rd_addr_rs1 = scoreboard_if[i].data.rs1;
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assign gpr_rd_addr_rs2 = scoreboard_if[i].data.rs2;
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assign gpr_rd_addr_rs2 = scoreboard_if[i].data.rs2;
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`ifdef EXT_T_HOPPER
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assign gpr_rd_addr_rs3 = tc_rf_valid[i] ? tc_rf_addr[i] : scoreboard_if[i].data.rs3;
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assign gpr_rd_addr_rs3 = tc_rf_valid[i] ? tc_rf_addr[i] : scoreboard_if[i].data.rs3;
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`else
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assign gpr_rd_addr_rs3 = {scoreboard_if[i].data.wis, scoreboard_if[i].data.rs3};
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`endif
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// always @(posedge clk) begin
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// always @(posedge clk) begin
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// if (reset) begin
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// if (reset) begin
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// gpr_rd_addr_rs1 <= '0;
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// gpr_rd_addr_rs1 <= '0;
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@@ -242,7 +260,11 @@ module VX_operands_dup import VX_gpu_pkg::*; #(
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.NO_RWCHECK (1)
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.NO_RWCHECK (1)
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) gpr_ram_rs1 (
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) gpr_ram_rs1 (
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.clk (clk),
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.clk (clk),
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`ifdef EXT_T_HOPPER
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.read (~tc_rf_valid[i]),
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.read (~tc_rf_valid[i]),
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`else
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.read (1'b1),
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`endif
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`UNUSED_PIN (wren),
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`UNUSED_PIN (wren),
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`ifdef GPR_RESET
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`ifdef GPR_RESET
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.write (wr_enabled && writeback_if[i].valid && writeback_if[i].data.tmask[j]),
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.write (wr_enabled && writeback_if[i].valid && writeback_if[i].data.tmask[j]),
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@@ -266,7 +288,11 @@ module VX_operands_dup import VX_gpu_pkg::*; #(
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.NO_RWCHECK (1)
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.NO_RWCHECK (1)
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) gpr_ram_rs2(
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) gpr_ram_rs2(
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.clk (clk),
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.clk (clk),
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`ifdef EXT_T_HOPPER
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.read (~tc_rf_valid[i]),
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.read (~tc_rf_valid[i]),
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`else
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.read (1'b1),
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`endif
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`UNUSED_PIN (wren),
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`UNUSED_PIN (wren),
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`ifdef GPR_RESET
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`ifdef GPR_RESET
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.write (wr_enabled && writeback_if[i].valid && writeback_if[i].data.tmask[j]),
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.write (wr_enabled && writeback_if[i].valid && writeback_if[i].data.tmask[j]),
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