parametrize memory interface in core wrapper and update config.vh
This commit is contained in:
Richard Yan
@@ -79,15 +79,15 @@
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`endif
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`endif
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`ifndef NUM_CORES
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`ifndef NUM_CORES
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`define NUM_CORES 1
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`define NUM_CORES 2
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`endif
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`endif
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`ifndef NUM_WARPS
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`ifndef NUM_WARPS
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`define NUM_WARPS 4
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`define NUM_WARPS 8
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`endif
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`endif
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`ifndef NUM_THREADS
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`ifndef NUM_THREADS
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`define NUM_THREADS 4
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`define NUM_THREADS 8
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`endif
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`endif
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`ifndef NUM_BARRIERS
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`ifndef NUM_BARRIERS
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@@ -175,7 +175,7 @@
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`endif
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`endif
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`ifndef SMEM_LOG_SIZE
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`ifndef SMEM_LOG_SIZE
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`define SMEM_LOG_SIZE 14
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`define SMEM_LOG_SIZE 15
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`endif
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`endif
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`ifndef IO_BASE_ADDR
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`ifndef IO_BASE_ADDR
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@@ -238,7 +238,7 @@
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// Issue width
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// Issue width
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`ifndef ISSUE_WIDTH
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`ifndef ISSUE_WIDTH
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`define ISSUE_WIDTH `MIN(`NUM_WARPS, 4)
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`define ISSUE_WIDTH `MIN(`NUM_WARPS, 8)
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`endif
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`endif
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// Number of ALU units
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// Number of ALU units
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@@ -259,12 +259,12 @@
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// Number of LSU units
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// Number of LSU units
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`ifndef NUM_LSU_LANES
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`ifndef NUM_LSU_LANES
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`define NUM_LSU_LANES `MIN(`NUM_THREADS, 4)
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`define NUM_LSU_LANES `NUM_THREADS
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`endif
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`endif
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// Number of SFU units
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// Number of SFU units
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`ifndef NUM_SFU_LANES
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`ifndef NUM_SFU_LANES
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`define NUM_SFU_LANES `MIN(`NUM_THREADS, 4)
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`define NUM_SFU_LANES `NUM_THREADS
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`endif
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`endif
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// Size of Instruction Buffer
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// Size of Instruction Buffer
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@@ -459,7 +459,7 @@
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// Number of Banks
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// Number of Banks
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`ifndef DCACHE_NUM_BANKS
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`ifndef DCACHE_NUM_BANKS
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`define DCACHE_NUM_BANKS `MIN(`NUM_LSU_LANES, 4)
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`define DCACHE_NUM_BANKS `NUM_LSU_LANES
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`endif
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`endif
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// Core Response Queue Size
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// Core Response Queue Size
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@@ -222,195 +222,63 @@ module Vortex import VX_gpu_pkg::*; #(
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// dmem -------------------------------------------------------------------
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// dmem -------------------------------------------------------------------
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// Vortex core does not accept write acks; filter them out here
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// Vortex core does not accept write acks; filter them out here
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assign dcache_bus_if[0].rsp_valid =
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generate
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(dmem_d_valid[0] && (dmem_d_bits_opcode[0 * 3 +: 3] !== 3'd0 /*AccessAck*/));
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for (genvar i = 0; i < DCACHE_NUM_REQS; i++) begin
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assign dcache_bus_if[1].rsp_valid =
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assign dcache_bus_if[i].rsp_valid =
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(dmem_d_valid[1] && (dmem_d_bits_opcode[1 * 3 +: 3] !== 3'd0 /*AccessAck*/));
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(dmem_d_valid[i] && (dmem_d_bits_opcode[i * 3 +: 3] !== 3'd0 /*AccessAck*/));
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assign dcache_bus_if[2].rsp_valid =
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// Data and tag assignment for dcache
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(dmem_d_valid[2] && (dmem_d_bits_opcode[2 * 3 +: 3] !== 3'd0 /*AccessAck*/));
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assign dcache_bus_if[i].rsp_data.data = dmem_d_bits_data[i * 32 +: 32];
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assign dcache_bus_if[3].rsp_valid =
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assign dcache_bus_if[i].rsp_data.tag = dmem_d_bits_source[i * DCACHE_NOSM_TAG_WIDTH +: DCACHE_NOSM_TAG_WIDTH];
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(dmem_d_valid[3] && (dmem_d_bits_opcode[3 * 3 +: 3] !== 3'd0 /*AccessAck*/));
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assign dcache_bus_if[0].rsp_data.data = dmem_d_bits_data[0 * 32 +: 32];
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// Handling write ACKs, setting ready bit for dcache
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assign dcache_bus_if[1].rsp_data.data = dmem_d_bits_data[1 * 32 +: 32];
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assign dmem_d_ready[i] = dcache_bus_if[i].rsp_ready ||
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assign dcache_bus_if[2].rsp_data.data = dmem_d_bits_data[2 * 32 +: 32];
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(dmem_d_valid[i] && (dmem_d_bits_opcode[i * 3 +: 3] == 3'd0 /*AccessAck*/));
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assign dcache_bus_if[3].rsp_data.data = dmem_d_bits_data[3 * 32 +: 32];
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assign dcache_bus_if[0].rsp_data.tag = dmem_d_bits_source[0 * DCACHE_NOSM_TAG_WIDTH +: DCACHE_NOSM_TAG_WIDTH];
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// Request validity and address/data/source assignment for dcache
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assign dcache_bus_if[1].rsp_data.tag = dmem_d_bits_source[1 * DCACHE_NOSM_TAG_WIDTH +: DCACHE_NOSM_TAG_WIDTH];
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assign dmem_a_valid[i] = dcache_bus_if[i].req_valid;
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assign dcache_bus_if[2].rsp_data.tag = dmem_d_bits_source[2 * DCACHE_NOSM_TAG_WIDTH +: DCACHE_NOSM_TAG_WIDTH];
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assign dmem_a_bits_address[i * 32 +: 32] = {dcache_bus_if[i].req_data.addr, 2'b0};
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assign dcache_bus_if[3].rsp_data.tag = dmem_d_bits_source[3 * DCACHE_NOSM_TAG_WIDTH +: DCACHE_NOSM_TAG_WIDTH];
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assign dmem_a_bits_data[i * 32 +: 32] = dcache_bus_if[i].req_data.data;
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assign dmem_a_bits_source[i * DCACHE_NOSM_TAG_WIDTH +: DCACHE_NOSM_TAG_WIDTH] = dcache_bus_if[i].req_data.tag;
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// When there's a write ACK coming back, ready bit should always be 1 to
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// Opcode, size, and mask assignment for dcache
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// accept them because core does not accept them on their own
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assign dmem_a_bits_opcode[i * 3 +: 3] =
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assign dmem_d_ready[0] = dcache_bus_if[0].rsp_ready ||
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dcache_bus_if[i].req_data.rw ?
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(dmem_d_valid[0] && (dmem_d_bits_opcode[0 * 3 +: 3] == 3'd0 /*AccessAck*/));
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(&dcache_bus_if[i].req_data.byteen ? 3'd0 /*PutFull*/ : 3'd1 /*PutPartial*/)
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assign dmem_d_ready[1] = dcache_bus_if[1].rsp_ready ||
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: 3'd4 /*Get*/;
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(dmem_d_valid[1] && (dmem_d_bits_opcode[1 * 3 +: 3] == 3'd0 /*AccessAck*/));
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assign dmem_a_bits_size[i * 4 +: 4] = 4'd2; // Fixed size
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assign dmem_d_ready[2] = dcache_bus_if[2].rsp_ready ||
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assign dmem_a_bits_mask[i * 4 +: 4] = dcache_bus_if[i].req_data.byteen;
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(dmem_d_valid[2] && (dmem_d_bits_opcode[2 * 3 +: 3] == 3'd0 /*AccessAck*/));
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assign dmem_d_ready[3] = dcache_bus_if[3].rsp_ready ||
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(dmem_d_valid[3] && (dmem_d_bits_opcode[3 * 3 +: 3] == 3'd0 /*AccessAck*/));
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assign dmem_a_valid[0] = dcache_bus_if[0].req_valid;
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// Setting request ready signal for dcache
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assign dmem_a_valid[1] = dcache_bus_if[1].req_valid;
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assign dcache_bus_if[i].req_ready = dmem_a_ready[i];
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assign dmem_a_valid[2] = dcache_bus_if[2].req_valid;
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assign dmem_a_valid[3] = dcache_bus_if[3].req_valid;
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assign dmem_a_bits_address[0 * 32 +: 32] = {dcache_bus_if[0].req_data.addr, 2'b0};
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// Data and tag assignment for smem
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assign dmem_a_bits_address[1 * 32 +: 32] = {dcache_bus_if[1].req_data.addr, 2'b0};
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assign smem_bus_if[i].rsp_valid =
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assign dmem_a_bits_address[2 * 32 +: 32] = {dcache_bus_if[2].req_data.addr, 2'b0};
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(smem_d_valid[i] && (smem_d_bits_opcode[i * 3 +: 3] !== 3'd0 /*AccessAck*/));
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assign dmem_a_bits_address[3 * 32 +: 32] = {dcache_bus_if[3].req_data.addr, 2'b0};
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assign smem_bus_if[i].rsp_data.data = smem_d_bits_data[i * 32 +: 32];
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assign smem_bus_if[i].rsp_data.tag = smem_d_bits_source[i * DCACHE_NOSM_TAG_WIDTH +: DCACHE_NOSM_TAG_WIDTH];
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assign dmem_a_bits_data[0 * 32 +: 32] = dcache_bus_if[0].req_data.data;
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// Handling write ACKs, setting ready bit for smem
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assign dmem_a_bits_data[1 * 32 +: 32] = dcache_bus_if[1].req_data.data;
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assign smem_d_ready[i] = smem_bus_if[i].rsp_ready ||
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assign dmem_a_bits_data[2 * 32 +: 32] = dcache_bus_if[2].req_data.data;
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(smem_d_valid[i] && (smem_d_bits_opcode[i * 3 +: 3] == 3'd0 /*AccessAck*/));
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assign dmem_a_bits_data[3 * 32 +: 32] = dcache_bus_if[3].req_data.data;
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assign dmem_a_bits_source[0 * DCACHE_NOSM_TAG_WIDTH +: DCACHE_NOSM_TAG_WIDTH] = dcache_bus_if[0].req_data.tag;
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// Request validity and address/data/source assignment for smem
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assign dmem_a_bits_source[1 * DCACHE_NOSM_TAG_WIDTH +: DCACHE_NOSM_TAG_WIDTH] = dcache_bus_if[1].req_data.tag;
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assign smem_a_valid[i] = smem_bus_if[i].req_valid;
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assign dmem_a_bits_source[2 * DCACHE_NOSM_TAG_WIDTH +: DCACHE_NOSM_TAG_WIDTH] = dcache_bus_if[2].req_data.tag;
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assign smem_a_bits_address[i * 32 +: 32] = {smem_bus_if[i].req_data.addr, 2'b0};
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assign dmem_a_bits_source[3 * DCACHE_NOSM_TAG_WIDTH +: DCACHE_NOSM_TAG_WIDTH] = dcache_bus_if[3].req_data.tag;
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assign smem_a_bits_data[i * 32 +: 32] = smem_bus_if[i].req_data.data;
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assign smem_a_bits_source[i * DCACHE_NOSM_TAG_WIDTH +: DCACHE_NOSM_TAG_WIDTH] = smem_bus_if[i].req_data.tag;
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// we assume all lanes always have the same tag; otherwise the sourceId
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// Opcode, size, and mask assignment for smem
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// logic in the Chisel tile breaks
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assign smem_a_bits_opcode[i * 3 +: 3] =
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// NOTE: not working at the moment but this doesn't seem to be a problem
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smem_bus_if[i].req_data.rw ?
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// always @(*) begin
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(&smem_bus_if[i].req_data.byteen ? 3'd0 /*PutFull*/ : 3'd1 /*PutPartial*/)
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// for (i = 0; i < 4; i++) begin
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: 3'd4 /*Get*/;
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// assert(dcache_req_if.tag[0] == dcache_req_if.tag[i])
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assign smem_a_bits_size[i * 4 +: 4] = 4'd2; // Fixed size
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// end
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assign smem_a_bits_mask[i * 4 +: 4] = smem_bus_if[i].req_data.byteen;
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// end
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// Translate Vortex rw/byteen to TileLink opcode
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// Setting request ready signal for smem
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assign dmem_a_bits_opcode[0 * 3 +: 3] =
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assign smem_bus_if[i].req_ready = smem_a_ready[i];
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dcache_bus_if[0].req_data.rw ?
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end
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(&dcache_bus_if[0].req_data.byteen ? 3'd0 /*PutFull*/ : 3'd1 /*PutPartial*/)
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endgenerate
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: 3'd4 /*Get*/;
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assign dmem_a_bits_opcode[1 * 3 +: 3] =
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dcache_bus_if[1].req_data.rw ?
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(&dcache_bus_if[1].req_data.byteen ? 3'd0 /*PutFull*/ : 3'd1 /*PutPartial*/)
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: 3'd4 /*Get*/;
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assign dmem_a_bits_opcode[2 * 3 +: 3] =
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dcache_bus_if[2].req_data.rw ?
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(&dcache_bus_if[2].req_data.byteen ? 3'd0 /*PutFull*/ : 3'd1 /*PutPartial*/)
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: 3'd4 /*Get*/;
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assign dmem_a_bits_opcode[3 * 3 +: 3] =
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dcache_bus_if[3].req_data.rw ?
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(&dcache_bus_if[3].req_data.byteen ? 3'd0 /*PutFull*/ : 3'd1 /*PutPartial*/)
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: 3'd4 /*Get*/;
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// Vortex cache requests are single-fixed-size
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// NOTE: MAKE SURE TO CHANGE CONSTANT WIDTH FOR SIZE!
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assign dmem_a_bits_size[0 * 4 +: 4] = 4'd2;
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assign dmem_a_bits_size[1 * 4 +: 4] = 4'd2;
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assign dmem_a_bits_size[2 * 4 +: 4] = 4'd2;
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assign dmem_a_bits_size[3 * 4 +: 4] = 4'd2;
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/* $countones(dcache_req_if.byteen[0]) === 'd4 ? 2'd2 :
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($countones(dcache_req_if.byteen[0]) === 'd2 ? 2'd1 : 2'd0); */
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// byteen can be directly used as TL mask
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assign dmem_a_bits_mask[0 * 4 +: 4] = dcache_bus_if[0].req_data.byteen;
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assign dmem_a_bits_mask[1 * 4 +: 4] = dcache_bus_if[1].req_data.byteen;
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assign dmem_a_bits_mask[2 * 4 +: 4] = dcache_bus_if[2].req_data.byteen;
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assign dmem_a_bits_mask[3 * 4 +: 4] = dcache_bus_if[3].req_data.byteen;
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assign dcache_bus_if[0].req_ready = dmem_a_ready[0];
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assign dcache_bus_if[1].req_ready = dmem_a_ready[1];
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assign dcache_bus_if[2].req_ready = dmem_a_ready[2];
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assign dcache_bus_if[3].req_ready = dmem_a_ready[3];
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// smem -------------------------------------------------------------------
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// FIXME: giant @copypaste from dmem
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// Vortex core does not accept write acks; filter them out here
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assign smem_bus_if[0].rsp_valid =
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(smem_d_valid[0] && (smem_d_bits_opcode[0 * 3 +: 3] !== 3'd0 /*AccessAck*/));
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assign smem_bus_if[1].rsp_valid =
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(smem_d_valid[1] && (smem_d_bits_opcode[1 * 3 +: 3] !== 3'd0 /*AccessAck*/));
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assign smem_bus_if[2].rsp_valid =
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(smem_d_valid[2] && (smem_d_bits_opcode[2 * 3 +: 3] !== 3'd0 /*AccessAck*/));
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assign smem_bus_if[3].rsp_valid =
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(smem_d_valid[3] && (smem_d_bits_opcode[3 * 3 +: 3] !== 3'd0 /*AccessAck*/));
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assign smem_bus_if[0].rsp_data.data = smem_d_bits_data[0 * 32 +: 32];
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assign smem_bus_if[1].rsp_data.data = smem_d_bits_data[1 * 32 +: 32];
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assign smem_bus_if[2].rsp_data.data = smem_d_bits_data[2 * 32 +: 32];
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assign smem_bus_if[3].rsp_data.data = smem_d_bits_data[3 * 32 +: 32];
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assign smem_bus_if[0].rsp_data.tag = smem_d_bits_source[0 * DCACHE_NOSM_TAG_WIDTH +: DCACHE_NOSM_TAG_WIDTH];
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assign smem_bus_if[1].rsp_data.tag = smem_d_bits_source[1 * DCACHE_NOSM_TAG_WIDTH +: DCACHE_NOSM_TAG_WIDTH];
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assign smem_bus_if[2].rsp_data.tag = smem_d_bits_source[2 * DCACHE_NOSM_TAG_WIDTH +: DCACHE_NOSM_TAG_WIDTH];
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assign smem_bus_if[3].rsp_data.tag = smem_d_bits_source[3 * DCACHE_NOSM_TAG_WIDTH +: DCACHE_NOSM_TAG_WIDTH];
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// When there's a write ACK coming back, ready bit should always be 1 to
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// accept them because core does not accept them on their own
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assign smem_d_ready[0] = smem_bus_if[0].rsp_ready ||
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(smem_d_valid[0] && (smem_d_bits_opcode[0 * 3 +: 3] == 3'd0 /*AccessAck*/));
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assign smem_d_ready[1] = smem_bus_if[1].rsp_ready ||
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(smem_d_valid[1] && (smem_d_bits_opcode[1 * 3 +: 3] == 3'd0 /*AccessAck*/));
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assign smem_d_ready[2] = smem_bus_if[2].rsp_ready ||
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(smem_d_valid[2] && (smem_d_bits_opcode[2 * 3 +: 3] == 3'd0 /*AccessAck*/));
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assign smem_d_ready[3] = smem_bus_if[3].rsp_ready ||
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(smem_d_valid[3] && (smem_d_bits_opcode[3 * 3 +: 3] == 3'd0 /*AccessAck*/));
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assign smem_a_valid[0] = smem_bus_if[0].req_valid;
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assign smem_a_valid[1] = smem_bus_if[1].req_valid;
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assign smem_a_valid[2] = smem_bus_if[2].req_valid;
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assign smem_a_valid[3] = smem_bus_if[3].req_valid;
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assign smem_a_bits_address[0 * 32 +: 32] = {smem_bus_if[0].req_data.addr, 2'b0};
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assign smem_a_bits_address[1 * 32 +: 32] = {smem_bus_if[1].req_data.addr, 2'b0};
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assign smem_a_bits_address[2 * 32 +: 32] = {smem_bus_if[2].req_data.addr, 2'b0};
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assign smem_a_bits_address[3 * 32 +: 32] = {smem_bus_if[3].req_data.addr, 2'b0};
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assign smem_a_bits_data[0 * 32 +: 32] = smem_bus_if[0].req_data.data;
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assign smem_a_bits_data[1 * 32 +: 32] = smem_bus_if[1].req_data.data;
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assign smem_a_bits_data[2 * 32 +: 32] = smem_bus_if[2].req_data.data;
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assign smem_a_bits_data[3 * 32 +: 32] = smem_bus_if[3].req_data.data;
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assign smem_a_bits_source[0 * DCACHE_NOSM_TAG_WIDTH +: DCACHE_NOSM_TAG_WIDTH] = smem_bus_if[0].req_data.tag;
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assign smem_a_bits_source[1 * DCACHE_NOSM_TAG_WIDTH +: DCACHE_NOSM_TAG_WIDTH] = smem_bus_if[1].req_data.tag;
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assign smem_a_bits_source[2 * DCACHE_NOSM_TAG_WIDTH +: DCACHE_NOSM_TAG_WIDTH] = smem_bus_if[2].req_data.tag;
|
|
||||||
assign smem_a_bits_source[3 * DCACHE_NOSM_TAG_WIDTH +: DCACHE_NOSM_TAG_WIDTH] = smem_bus_if[3].req_data.tag;
|
|
||||||
|
|
||||||
// Translate Vortex rw/byteen to TileLink opcode
|
|
||||||
assign smem_a_bits_opcode[0 * 3 +: 3] =
|
|
||||||
smem_bus_if[0].req_data.rw ?
|
|
||||||
(&smem_bus_if[0].req_data.byteen ? 3'd0 /*PutFull*/ : 3'd1 /*PutPartial*/)
|
|
||||||
: 3'd4 /*Get*/;
|
|
||||||
assign smem_a_bits_opcode[1 * 3 +: 3] =
|
|
||||||
smem_bus_if[1].req_data.rw ?
|
|
||||||
(&smem_bus_if[1].req_data.byteen ? 3'd0 /*PutFull*/ : 3'd1 /*PutPartial*/)
|
|
||||||
: 3'd4 /*Get*/;
|
|
||||||
assign smem_a_bits_opcode[2 * 3 +: 3] =
|
|
||||||
smem_bus_if[2].req_data.rw ?
|
|
||||||
(&smem_bus_if[2].req_data.byteen ? 3'd0 /*PutFull*/ : 3'd1 /*PutPartial*/)
|
|
||||||
: 3'd4 /*Get*/;
|
|
||||||
assign smem_a_bits_opcode[3 * 3 +: 3] =
|
|
||||||
smem_bus_if[3].req_data.rw ?
|
|
||||||
(&smem_bus_if[3].req_data.byteen ? 3'd0 /*PutFull*/ : 3'd1 /*PutPartial*/)
|
|
||||||
: 3'd4 /*Get*/;
|
|
||||||
|
|
||||||
// Vortex cache requests are single-fixed-size
|
|
||||||
// NOTE: MAKE SURE TO CHANGE CONSTANT WIDTH FOR SIZE!
|
|
||||||
assign smem_a_bits_size[0 * 4 +: 4] = 4'd2;
|
|
||||||
assign smem_a_bits_size[1 * 4 +: 4] = 4'd2;
|
|
||||||
assign smem_a_bits_size[2 * 4 +: 4] = 4'd2;
|
|
||||||
assign smem_a_bits_size[3 * 4 +: 4] = 4'd2;
|
|
||||||
/* $countones(dcache_req_if.byteen[0]) === 'd4 ? 2'd2 :
|
|
||||||
($countones(dcache_req_if.byteen[0]) === 'd2 ? 2'd1 : 2'd0); */
|
|
||||||
|
|
||||||
// byteen can be directly used as TL mask
|
|
||||||
assign smem_a_bits_mask[0 * 4 +: 4] = smem_bus_if[0].req_data.byteen;
|
|
||||||
assign smem_a_bits_mask[1 * 4 +: 4] = smem_bus_if[1].req_data.byteen;
|
|
||||||
assign smem_a_bits_mask[2 * 4 +: 4] = smem_bus_if[2].req_data.byteen;
|
|
||||||
assign smem_a_bits_mask[3 * 4 +: 4] = smem_bus_if[3].req_data.byteen;
|
|
||||||
|
|
||||||
assign smem_bus_if[0].req_ready = smem_a_ready[0];
|
|
||||||
assign smem_bus_if[1].req_ready = smem_a_ready[1];
|
|
||||||
assign smem_bus_if[2].req_ready = smem_a_ready[2];
|
|
||||||
assign smem_bus_if[3].req_ready = smem_a_ready[3];
|
|
||||||
|
|
||||||
// gbar -------------------------------------------------------------------
|
// gbar -------------------------------------------------------------------
|
||||||
`ifdef GBAR_ENABLE
|
`ifdef GBAR_ENABLE
|
||||||
|
|||||||
Reference in New Issue
Block a user