From 4376bd33a2ad2c4f59a3c8f1702a87f88361f505 Mon Sep 17 00:00:00 2001
From: Hansung Kim <hansung_kim@berkeley.edu>
Date: Mon, 28 Oct 2024 19:41:37 -0700
Subject: [PATCH] tensor: Decode rs1/rs2 of HGMMA for smem addresses

---
 hw/rtl/core/VX_decode.sv | 7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/hw/rtl/core/VX_decode.sv b/hw/rtl/core/VX_decode.sv
index 8d52d450..36063cd9 100644
--- a/hw/rtl/core/VX_decode.sv
+++ b/hw/rtl/core/VX_decode.sv
@@ -551,15 +551,16 @@ module VX_decode  #(
                 end else begin
                     op_type = `INST_TENSOR_HGMMA;
                 end
-                // rd/rs1/rs2/rs3 unused to prevent hazard stalls at the
-                // scoreboard
+                // rs1 and rs2 encodes the sharedmem addresses for A and
+                // B matrix tiles
+                `USED_IREG (rs1);
+                `USED_IREG (rs2);
             `else
                 ex_type = `EX_TENSOR;
                 op_type = `INST_TENSOR_HMMA;
                 // tensor core macroop is encoded as r-type
                 // hazard stall logic in the scoreboard will handle
                 // read-after-write dependency on rd -> rs3
-                use_rd = 1;
                 `USED_IREG (rd);
                 `USED_IREG (rs1);
                 `USED_IREG (rs2);