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RTL code refactoring

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This commit is contained in:
Blaise Tine
2020-04-21 01:52:12 -04:00
parent 20ae78f434
commit 43a8bf4326
2 changed files with 72 additions and 60 deletions
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25
hw/rtl/VX_warp_sched.v
View File

@@ -60,7 +60,6 @@ module VX_warp_sched (
input wire[`NW_BITS-1:0] icache_stage_wid,
input wire[`NUM_THREADS-1:0] icache_stage_valids
);
wire update_use_wspawn;
wire update_visible_active;
@@ -226,13 +225,18 @@ module VX_warp_sched (
end
end
VX_countones #(.N(`NUM_WARPS)) barrier_count(
VX_countones #(
.N(`NUM_WARPS)
) barrier_count (
.valids(curr_barrier_mask),
.count (curr_barrier_count)
);
wire [$clog2(`NUM_WARPS):0] count_visible_active;
VX_countones #(.N(`NUM_WARPS)) num_visible(
VX_countones #(
.N(`NUM_WARPS)
) num_visible (
.valids(visible_active),
.count (count_visible_active)
);
@@ -254,17 +258,13 @@ module VX_warp_sched (
// end
// end
assign update_visible_active = (count_visible_active < 1) && !(stall || wstall_this_cycle || hazard || is_join);
wire[(1+32+`NUM_THREADS-1):0] q1 = {1'b1, 32'b0 , thread_masks[split_warp_num]};
wire[(1+32+`NUM_THREADS-1):0] q2 = {1'b0, split_save_pc , split_later_mask};
assign {join_fall, join_pc, join_tm} = d[join_warp_num];
genvar curr_warp;
generate
for (curr_warp = 0; curr_warp < `NUM_WARPS; curr_warp = curr_warp + 1) begin : stacks
@@ -273,7 +273,11 @@ module VX_warp_sched (
wire push = (is_split && !dont_split) && correct_warp_s;
wire pop = is_join && correct_warp_j;
VX_generic_stack #(.WIDTH(1+32+`NUM_THREADS), .DEPTH($clog2(`NUM_THREADS)+1)) ipdom_stack(
VX_generic_stack #(
.WIDTH(1+32+`NUM_THREADS),
.DEPTH($clog2(`NUM_THREADS)+1)
) ipdom_stack(
.clk (clk),
.reset(reset),
.push (push),
@@ -308,11 +312,12 @@ module VX_warp_sched (
assign new_pc = warp_pc + 4;
assign use_active = (count_visible_active < 1) ? (warp_active & (~warp_stalled) & (~total_barrier_stall) & (~warp_lock)) : visible_active;
// Choosing a warp to schedule
VX_priority_encoder choose_schedule(
VX_priority_encoder #(
.N(`NUM_WARPS)
) choose_schedule (
.valids(use_active),
.index (warp_to_schedule),
.found (schedule)

23
hw/rtl/libs/VX_priority_encoder.v
View File

@@ -1,21 +1,28 @@
`include "VX_define.vh"
module VX_priority_encoder (
input wire[`NUM_WARPS-1:0] valids,
output reg[`NW_BITS-1:0] index,
output reg found
module VX_priority_encoder #(
parameter N
) (
input wire [N-1:0] valids,
output wire [`LOG2UP(N)-1:0] index,
output wire found
);
reg [`LOG2UP(N)-1:0] index_r;
reg found_r;
integer i;
always @(*) begin
index = 0;
found = 0;
index_r = 0;
found_r = 0;
for (i = `NUM_WARPS-1; i >= 0; i = i - 1) begin
if (valids[i]) begin
index = i[`NW_BITS-1:0];
found = 1;
index_r = i[`NW_BITS-1:0];
found_r = 1;
end
end
end
assign index = index_r;
assign found = found_r;
endmodule