wu-arch/vortex
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

minor update

Browse Source
This commit is contained in:
Blaise Tine
2021-10-11 18:32:17 -04:00
parent 549629440d
commit 4a4498cd53
4 changed files with 10 additions and 8 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
sim/rtlsim/Makefile
View File

@@ -34,7 +34,7 @@ SRCS += main.cpp simulator.cpp
ifdef AXI_BUS
TOP = Vortex_axi
CFLAGS += -DAXI_BUS
CXXFLAGS += -DAXI_BUS
else
TOP = Vortex
endif
@@ -44,9 +44,11 @@ VL_FLAGS += -O2 --language 1800-2009 --assert -Wall -Wpedantic
VL_FLAGS += -Wno-DECLFILENAME -Wno-REDEFMACRO
VL_FLAGS += --x-initial unique --x-assign unique
VL_FLAGS += verilator.vlt
VL_FLAGS += $(CONFIGS)
VL_FLAGS += $(RTL_INCLUDE)
VL_FLAGS += $(CONFIGS)
CXXFLAGS += $(CONFIGS)
# Debugigng
ifdef DEBUG
VL_FLAGS += -DVCD_OUTPUT --trace --trace-structs $(DBG_FLAGS)

3
sim/rtlsim/simulator.cpp
View File

@@ -219,6 +219,7 @@ void Simulator::reset_axi_bus() {
vl_obj_->device->m_axi_awready = 0;
vl_obj_->device->m_axi_arready = 0;
vl_obj_->device->m_axi_rvalid = 0;
vl_obj_->device->m_axi_bvalid = 0;
}
void Simulator::eval_axi_bus(bool clk) {
@@ -369,7 +370,7 @@ void Simulator::eval_axi_bus(bool clk) {
mem_req_t mem_req;
mem_req.tag = vl_obj_->device->m_axi_arid;
mem_req.addr = vl_obj_->device->m_axi_araddr;
ram_->read(vl_obj_->device->m_axi_araddr, MEM_BLOCK_SIZE, mem_req.block.data());
ram_->read(mem_req.block.data(), vl_obj_->device->m_axi_araddr, MEM_BLOCK_SIZE);
mem_req.cycles_left = MEM_LATENCY;
mem_req.write = 0;
for (auto& rsp : mem_rsp_vec_[req_bank]) {