diff --git a/rtl/VX_decode.v b/rtl/VX_decode.v
index a87c6eb8..9d76a115 100644
--- a/rtl/VX_decode.v
+++ b/rtl/VX_decode.v
@@ -137,49 +137,24 @@ module VX_decode(
 		// 	$display("Decode: curr_pc: %h", in_curr_PC);
 		// end
 
-		// genvar index;
+		genvar index;
 
-		// generate  
-		// for (index=0; index < `NT; index=index+1)  
-		//   begin: gen_code_label  
-		// 	VX_register_file vx_register_file(
-		// 		.clk(clk),
-		// 		.in_valid(in_wb_valid[index]),
-		// 		.in_write_register(write_register),
-		// 		.in_rd(in_rd),
-		// 		.in_data(in_write_data[index]),
-		// 		.in_src1(out_rs1),
-		// 		.in_src2(out_rs2),
-		// 		.out_src1_data(rd1_register[index]),
-		// 		.out_src2_data(rd2_register[index])
-		// 	);
-		//   end  
-		// endgenerate  
-
-			VX_register_file vx_register_file_0(
+		generate  
+		for (index=0; index < `NT; index=index+1)  
+		  begin: gen_code_label  
+			VX_register_file vx_register_file(
 				.clk(clk),
-				.in_valid(in_wb_valid[0]),
+				.in_valid(in_wb_valid[index]),
 				.in_write_register(write_register),
 				.in_rd(in_rd),
-				.in_data(in_write_data[0]),
+				.in_data(in_write_data[index]),
 				.in_src1(out_rs1),
 				.in_src2(out_rs2),
-				.out_src1_data(rd1_register[0]),
-				.out_src2_data(rd2_register[0])
-			);
-
-
-			VX_register_file vx_register_file_1(
-				.clk(clk),
-				.in_valid(in_wb_valid[1]),
-				.in_write_register(write_register),
-				.in_rd(in_rd),
-				.in_data(in_write_data[1]),
-				.in_src1(out_rs1),
-				.in_src2(out_rs2),
-				.out_src1_data(rd1_register[1]),
-				.out_src2_data(rd2_register[1])
+				.out_src1_data(rd1_register[index]),
+				.out_src2_data(rd2_register[index])
 			);
+		  end  
+		endgenerate  
 
 		assign curr_opcode    = in_instruction[6:0];
 
diff --git a/rtl/VX_execute.v b/rtl/VX_execute.v
index 3fb0119a..5b2163f4 100644
--- a/rtl/VX_execute.v
+++ b/rtl/VX_execute.v
@@ -47,78 +47,25 @@ module VX_execute (
 
 
 
-	// VX_alu vx_alu(
-	// 		.in_reg_data   (in_reg_data),
-	// 		.in_rs2_src    (in_rs2_src),
-	// 		.in_itype_immed(in_itype_immed),
-	// 		.in_upper_immed(in_upper_immed),
-	// 		.in_alu_op     (in_alu_op),
-	// 		.in_csr_data   (in_csr_data),
-	// 		.in_curr_PC    (in_curr_PC),
-	// 		.out_alu_result(out_alu_result)
-	// 	);
+		genvar index_out_reg;
+		generate
+			for (index_out_reg = 0; index_out_reg < `NT; index_out_reg = index_out_reg + 1)
+				begin
+					VX_alu vx_alu(
+						// .in_reg_data   (in_reg_data[1:0]),
+						.in_1          (in_a_reg_data[index_out_reg]),
+						.in_2          (in_b_reg_data[index_out_reg]),
+						.in_rs2_src    (in_rs2_src),
+						.in_itype_immed(in_itype_immed),
+						.in_upper_immed(in_upper_immed),
+						.in_alu_op     (in_alu_op),
+						.in_csr_data   (in_csr_data),
+						.in_curr_PC    (in_curr_PC),
+						.out_alu_result(out_alu_result[index_out_reg])
+					);
+				end
+		endgenerate
 
-		// genvar index;
-		// reg[5:0] index_2;
-		// generate  
-		// for (index=0; index < `NT; index=index+1)  
-		//   begin: gen_code_label  
-		//   	assign index_2 = index * 2;
-		// 	VX_alu vx_alu(
-		// 		.in_reg_data   (in_reg_data[(index_2+1):(index_2)]),
-		// 		.in_rs2_src    (in_rs2_src),
-		// 		.in_itype_immed(in_itype_immed),
-		// 		.in_upper_immed(in_upper_immed),
-		// 		.in_alu_op     (in_alu_op),
-		// 		.in_csr_data   (in_csr_data),
-		// 		.in_curr_PC    (in_curr_PC),
-		// 		.out_alu_result(out_alu_result[index])
-		// 	);
-		//   end  
-		// endgenerate  
-
-		// genvar index_out_reg;
-		// generate
-		// 	for (index_out_reg = 0; index_out_reg < `NT; index_out_reg = index_out_reg + 1)
-		// 		begin
-		// 			VX_alu vx_alu_0(
-		// 				// .in_reg_data   (in_reg_data[1:0]),
-		// 				.in_1          (in_a_reg_data[index_out_reg]),
-		// 				.in_2          (in_b_reg_data[index_out_reg]),
-		// 				.in_rs2_src    (in_rs2_src),
-		// 				.in_itype_immed(in_itype_immed),
-		// 				.in_upper_immed(in_upper_immed),
-		// 				.in_alu_op     (in_alu_op),
-		// 				.in_csr_data   (in_csr_data),
-		// 				.in_curr_PC    (in_curr_PC),
-		// 				.out_alu_result(out_alu_result[index_out_reg])
-		// 			);
-		// 		end
-		// endgenerate
-
-		VX_alu vx_alu_0(
-			.in_1          (in_a_reg_data[0]),
-			.in_2          (in_b_reg_data[0]),
-			.in_rs2_src    (in_rs2_src),
-			.in_itype_immed(in_itype_immed),
-			.in_upper_immed(in_upper_immed),
-			.in_alu_op     (in_alu_op),
-			.in_csr_data   (in_csr_data),
-			.in_curr_PC    (in_curr_PC),
-			.out_alu_result(out_alu_result[0])
-		);
-
-		VX_alu vx_alu_1(
-			.in_1          (in_a_reg_data[1]),
-			.in_2          (in_b_reg_data[1]),
-			.in_rs2_src    (in_rs2_src),
-			.in_itype_immed(in_itype_immed),
-			.in_upper_immed(in_upper_immed),
-			.in_alu_op     (in_alu_op),
-			.in_csr_data   (in_csr_data),
-			.in_curr_PC    (in_curr_PC),
-			.out_alu_result(out_alu_result[1])
-		);
 
 		assign out_jal_dest = $signed(in_a_reg_data[0]) + $signed(in_jal_offset);
 		assign out_jal      = in_jal;
diff --git a/rtl/VX_fetch.v b/rtl/VX_fetch.v
index 835ea6fe..f102d56d 100644
--- a/rtl/VX_fetch.v
+++ b/rtl/VX_fetch.v
@@ -52,7 +52,6 @@ module VX_fetch (
 			for (ini_cur_th = 1; ini_cur_th < `NT; ini_cur_th=ini_cur_th+1)
 				valid[ini_cur_th]   = 0; // Thread 1 active
 			valid[0]   = 1;
-			// valid[1]   = 0;
 			stall_reg  = 0;
 			delay_reg  = 0;
 			old        = 0;
diff --git a/rtl/obj_dir/VVortex b/rtl/obj_dir/VVortex
index 517a7088..0a8ca7ff 100755
Binary files a/rtl/obj_dir/VVortex and b/rtl/obj_dir/VVortex differ
diff --git a/rtl/obj_dir/VVortex.cpp b/rtl/obj_dir/VVortex.cpp
index e1518546..58f32e18 100644
--- a/rtl/obj_dir/VVortex.cpp
+++ b/rtl/obj_dir/VVortex.cpp
@@ -106,25 +106,25 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__1(VVortex__Syms* __restrict vlSymsp)
     // Body
     __Vdlyvset__Vortex__DOT__vx_f_d_reg__DOT__valid__v0 = 0U;
     __Vdlyvset__Vortex__DOT__vx_f_d_reg__DOT__valid__v5 = 0U;
-    // ALWAYS at VX_fetch.v:147
+    // ALWAYS at VX_fetch.v:146
     vlTOPp->Vortex__DOT__vx_fetch__DOT__old = ((IData)(vlTOPp->reset)
 					        ? 0U
 					        : vlTOPp->Vortex__DOT__vx_fetch__DOT__temp_PC);
-    // ALWAYS at VX_fetch.v:147
+    // ALWAYS at VX_fetch.v:146
     vlTOPp->Vortex__DOT__vx_fetch__DOT__BR_reg = ((IData)(vlTOPp->reset)
 						   ? 0U
 						   : 
 						  ((IData)(4U) 
 						   + vlTOPp->Vortex__DOT__memory_branch_dest));
-    // ALWAYS at VX_fetch.v:147
+    // ALWAYS at VX_fetch.v:146
     vlTOPp->Vortex__DOT__vx_fetch__DOT__delay_reg = 0U;
-    // ALWAYS at VX_fetch.v:147
+    // ALWAYS at VX_fetch.v:146
     vlTOPp->Vortex__DOT__vx_fetch__DOT__real_PC = ((IData)(vlTOPp->reset)
 						    ? 0U
 						    : 
 						   ((IData)(4U) 
 						    + vlTOPp->Vortex__DOT__vx_fetch__DOT__PC_to_use));
-    // ALWAYS at VX_fetch.v:147
+    // ALWAYS at VX_fetch.v:146
     vlTOPp->Vortex__DOT__vx_fetch__DOT__stall_reg = 
 	((~ (IData)(vlTOPp->reset)) & (IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__stall));
     // ALWAYS at VX_f_d_reg.v:29
@@ -150,7 +150,7 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__1(VVortex__Syms* __restrict vlSymsp)
 		[0U];
 	}
     }
-    // ALWAYS at VX_fetch.v:147
+    // ALWAYS at VX_fetch.v:146
     vlTOPp->Vortex__DOT__vx_fetch__DOT__state = ((IData)(vlTOPp->reset)
 						  ? 0U
 						  : 
@@ -163,7 +163,7 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__1(VVortex__Syms* __restrict vlSymsp)
 						   ((IData)(vlTOPp->Vortex__DOT__memory_branch_dir)
 						     ? 2U
 						     : 0U))));
-    // ALWAYS at VX_fetch.v:147
+    // ALWAYS at VX_fetch.v:146
     vlTOPp->Vortex__DOT__vx_fetch__DOT__JAL_reg = ((IData)(vlTOPp->reset)
 						    ? 0U
 						    : 
@@ -204,9 +204,9 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__1(VVortex__Syms* __restrict vlSymsp)
     vlTOPp->Vortex__DOT____Vcellout__vx_f_d_reg__out_valid[0U] 
 	= vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__valid
 	[0U];
-    // ALWAYS at VX_fetch.v:147
+    // ALWAYS at VX_fetch.v:146
     vlTOPp->Vortex__DOT__vx_fetch__DOT__prev_debug = 0U;
-    // ALWAYS at VX_fetch.v:82
+    // ALWAYS at VX_fetch.v:81
     vlTOPp->Vortex__DOT__vx_fetch__DOT__PC_to_use = 
 	((IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__delay_reg)
 	  ? vlTOPp->Vortex__DOT__vx_fetch__DOT__old
@@ -279,10 +279,16 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__2(VVortex__Syms* __restrict vlSymsp)
     VVortex* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
     // Variables
     // Begin mtask footprint  all: 
-    VL_SIG8(__Vdlyvdim0__Vortex__DOT__vx_decode__DOT__vx_register_file_0__DOT__registers__v0,4,0);
-    VL_SIG8(__Vdlyvset__Vortex__DOT__vx_decode__DOT__vx_register_file_0__DOT__registers__v0,0,0);
-    VL_SIG8(__Vdlyvdim0__Vortex__DOT__vx_decode__DOT__vx_register_file_1__DOT__registers__v0,4,0);
-    VL_SIG8(__Vdlyvset__Vortex__DOT__vx_decode__DOT__vx_register_file_1__DOT__registers__v0,0,0);
+    VL_SIG8(__Vdlyvdim0__Vortex__DOT__vx_decode__DOT__gen_code_label__BRA__0__KET____DOT__vx_register_file__DOT__registers__v0,4,0);
+    VL_SIG8(__Vdlyvset__Vortex__DOT__vx_decode__DOT__gen_code_label__BRA__0__KET____DOT__vx_register_file__DOT__registers__v0,0,0);
+    VL_SIG8(__Vdlyvdim0__Vortex__DOT__vx_decode__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file__DOT__registers__v0,4,0);
+    VL_SIG8(__Vdlyvset__Vortex__DOT__vx_decode__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file__DOT__registers__v0,0,0);
+    VL_SIG8(__Vdlyvdim0__Vortex__DOT__vx_decode__DOT__gen_code_label__BRA__2__KET____DOT__vx_register_file__DOT__registers__v0,4,0);
+    VL_SIG8(__Vdlyvset__Vortex__DOT__vx_decode__DOT__gen_code_label__BRA__2__KET____DOT__vx_register_file__DOT__registers__v0,0,0);
+    VL_SIG8(__Vdlyvdim0__Vortex__DOT__vx_decode__DOT__gen_code_label__BRA__3__KET____DOT__vx_register_file__DOT__registers__v0,4,0);
+    VL_SIG8(__Vdlyvset__Vortex__DOT__vx_decode__DOT__gen_code_label__BRA__3__KET____DOT__vx_register_file__DOT__registers__v0,0,0);
+    VL_SIG8(__Vdlyvdim0__Vortex__DOT__vx_decode__DOT__gen_code_label__BRA__4__KET____DOT__vx_register_file__DOT__registers__v0,4,0);
+    VL_SIG8(__Vdlyvset__Vortex__DOT__vx_decode__DOT__gen_code_label__BRA__4__KET____DOT__vx_register_file__DOT__registers__v0,0,0);
     VL_SIG8(__Vdlyvval__Vortex__DOT__vx_d_e_reg__DOT__valid__v0,0,0);
     VL_SIG8(__Vdlyvval__Vortex__DOT__vx_d_e_reg__DOT__valid__v1,0,0);
     VL_SIG8(__Vdlyvval__Vortex__DOT__vx_d_e_reg__DOT__valid__v2,0,0);
@@ -301,8 +307,11 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__2(VVortex__Syms* __restrict vlSymsp)
     VL_SIG8(__Vdlyvset__Vortex__DOT__vx_csr_handler__DOT__csr__v0,0,0);
     VL_SIG16(__Vdlyvdim0__Vortex__DOT__vx_csr_handler__DOT__csr__v0,11,0);
     VL_SIG16(__Vdlyvval__Vortex__DOT__vx_csr_handler__DOT__csr__v0,11,0);
-    VL_SIG(__Vdlyvval__Vortex__DOT__vx_decode__DOT__vx_register_file_0__DOT__registers__v0,31,0);
-    VL_SIG(__Vdlyvval__Vortex__DOT__vx_decode__DOT__vx_register_file_1__DOT__registers__v0,31,0);
+    VL_SIG(__Vdlyvval__Vortex__DOT__vx_decode__DOT__gen_code_label__BRA__0__KET____DOT__vx_register_file__DOT__registers__v0,31,0);
+    VL_SIG(__Vdlyvval__Vortex__DOT__vx_decode__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file__DOT__registers__v0,31,0);
+    VL_SIG(__Vdlyvval__Vortex__DOT__vx_decode__DOT__gen_code_label__BRA__2__KET____DOT__vx_register_file__DOT__registers__v0,31,0);
+    VL_SIG(__Vdlyvval__Vortex__DOT__vx_decode__DOT__gen_code_label__BRA__3__KET____DOT__vx_register_file__DOT__registers__v0,31,0);
+    VL_SIG(__Vdlyvval__Vortex__DOT__vx_decode__DOT__gen_code_label__BRA__4__KET____DOT__vx_register_file__DOT__registers__v0,31,0);
     VL_SIG(__Vdlyvval__Vortex__DOT__vx_d_e_reg__DOT__a_reg_data__v0,31,0);
     VL_SIG(__Vdlyvval__Vortex__DOT__vx_d_e_reg__DOT__a_reg_data__v1,31,0);
     VL_SIG(__Vdlyvval__Vortex__DOT__vx_d_e_reg__DOT__a_reg_data__v2,31,0);
@@ -334,8 +343,11 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__2(VVortex__Syms* __restrict vlSymsp)
     VL_SIG(__Vdlyvval__Vortex__DOT__vx_m_w_reg__DOT__mem_result__v3,31,0);
     VL_SIG(__Vdlyvval__Vortex__DOT__vx_m_w_reg__DOT__mem_result__v4,31,0);
     // Body
-    __Vdlyvset__Vortex__DOT__vx_decode__DOT__vx_register_file_1__DOT__registers__v0 = 0U;
-    __Vdlyvset__Vortex__DOT__vx_decode__DOT__vx_register_file_0__DOT__registers__v0 = 0U;
+    __Vdlyvset__Vortex__DOT__vx_decode__DOT__gen_code_label__BRA__4__KET____DOT__vx_register_file__DOT__registers__v0 = 0U;
+    __Vdlyvset__Vortex__DOT__vx_decode__DOT__gen_code_label__BRA__3__KET____DOT__vx_register_file__DOT__registers__v0 = 0U;
+    __Vdlyvset__Vortex__DOT__vx_decode__DOT__gen_code_label__BRA__2__KET____DOT__vx_register_file__DOT__registers__v0 = 0U;
+    __Vdlyvset__Vortex__DOT__vx_decode__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file__DOT__registers__v0 = 0U;
+    __Vdlyvset__Vortex__DOT__vx_decode__DOT__gen_code_label__BRA__0__KET____DOT__vx_register_file__DOT__registers__v0 = 0U;
     __Vdlyvset__Vortex__DOT__vx_csr_handler__DOT__csr__v0 = 0U;
     // ALWAYS at VX_m_w_reg.v:60
     __Vdlyvval__Vortex__DOT__vx_m_w_reg__DOT__valid__v0 
@@ -398,9 +410,6 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__2(VVortex__Syms* __restrict vlSymsp)
 						(vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction 
 						 >> 0xcU)
 						 : 0U))));
-    // ALWAYS at VX_csr_handler.v:34
-    vlTOPp->Vortex__DOT__vx_csr_handler__DOT__decode_csr_address 
-	= vlTOPp->Vortex__DOT__decode_csr_address;
     // ALWAYS at VX_m_w_reg.v:60
     __Vdlyvval__Vortex__DOT__vx_m_w_reg__DOT__mem_result__v0 
 	= vlTOPp->Vortex__DOT____Vcellinp__vx_m_w_reg__in_mem_result
@@ -434,6 +443,9 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__2(VVortex__Syms* __restrict vlSymsp)
 	= vlTOPp->Vortex__DOT____Vcellinp__vx_m_w_reg__in_alu_result
 	[0U];
     // ALWAYS at VX_csr_handler.v:34
+    vlTOPp->Vortex__DOT__vx_csr_handler__DOT__decode_csr_address 
+	= vlTOPp->Vortex__DOT__decode_csr_address;
+    // ALWAYS at VX_csr_handler.v:34
     vlTOPp->Vortex__DOT__vx_csr_handler__DOT__cycle 
 	= (VL_ULL(1) + vlTOPp->Vortex__DOT__vx_csr_handler__DOT__cycle);
     // ALWAYS at VX_csr_handler.v:34
@@ -448,6 +460,22 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__2(VVortex__Syms* __restrict vlSymsp)
 			       | (0x23U == (0x7fU & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)))
 			       ? 1U : 0U))));
     // ALWAYS at VX_e_m_reg.v:126
+    __Vdlyvval__Vortex__DOT__vx_e_m_reg__DOT__alu_result__v0 
+	= vlTOPp->Vortex__DOT____Vcellinp__vx_e_m_reg__in_alu_result
+	[4U];
+    __Vdlyvval__Vortex__DOT__vx_e_m_reg__DOT__alu_result__v1 
+	= vlTOPp->Vortex__DOT____Vcellinp__vx_e_m_reg__in_alu_result
+	[3U];
+    __Vdlyvval__Vortex__DOT__vx_e_m_reg__DOT__alu_result__v2 
+	= vlTOPp->Vortex__DOT____Vcellinp__vx_e_m_reg__in_alu_result
+	[2U];
+    __Vdlyvval__Vortex__DOT__vx_e_m_reg__DOT__alu_result__v3 
+	= vlTOPp->Vortex__DOT____Vcellinp__vx_e_m_reg__in_alu_result
+	[1U];
+    __Vdlyvval__Vortex__DOT__vx_e_m_reg__DOT__alu_result__v4 
+	= vlTOPp->Vortex__DOT____Vcellinp__vx_e_m_reg__in_alu_result
+	[0U];
+    // ALWAYS at VX_e_m_reg.v:126
     vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__branch_type 
 	= vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__branch_type;
     // ALWAYS at VX_d_e_reg.v:138
@@ -493,36 +521,62 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__2(VVortex__Syms* __restrict vlSymsp)
     vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__jal_dest 
 	= (vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data
 	   [0U] + vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__jal_offset);
-    // ALWAYS at VX_e_m_reg.v:126
-    __Vdlyvval__Vortex__DOT__vx_e_m_reg__DOT__alu_result__v0 
-	= vlTOPp->Vortex__DOT____Vcellinp__vx_e_m_reg__in_alu_result
-	[4U];
-    __Vdlyvval__Vortex__DOT__vx_e_m_reg__DOT__alu_result__v1 
-	= vlTOPp->Vortex__DOT____Vcellinp__vx_e_m_reg__in_alu_result
-	[3U];
-    __Vdlyvval__Vortex__DOT__vx_e_m_reg__DOT__alu_result__v2 
-	= vlTOPp->Vortex__DOT____Vcellinp__vx_e_m_reg__in_alu_result
-	[2U];
-    __Vdlyvval__Vortex__DOT__vx_e_m_reg__DOT__alu_result__v3 
-	= vlTOPp->Vortex__DOT____Vcellinp__vx_e_m_reg__in_alu_result
-	[1U];
-    __Vdlyvval__Vortex__DOT__vx_e_m_reg__DOT__alu_result__v4 
-	= vlTOPp->Vortex__DOT____Vcellinp__vx_e_m_reg__in_alu_result
-	[0U];
     // ALWAYS at VX_m_w_reg.v:60
     vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__PC_next = vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__PC_next;
     // ALWAYS at VX_register_file.v:36
+    if (VL_UNLIKELY((((0U != (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb)) 
+		      & (0U != (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__rd))) 
+		     & vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_wb_valid
+		     [4U]))) {
+	VL_WRITEF("RF: Writing %x to %2#\n",32,vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_write_data
+		  [4U],5,vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__rd);
+	__Vdlyvval__Vortex__DOT__vx_decode__DOT__gen_code_label__BRA__4__KET____DOT__vx_register_file__DOT__registers__v0 
+	    = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_write_data
+	    [4U];
+	__Vdlyvset__Vortex__DOT__vx_decode__DOT__gen_code_label__BRA__4__KET____DOT__vx_register_file__DOT__registers__v0 = 1U;
+	__Vdlyvdim0__Vortex__DOT__vx_decode__DOT__gen_code_label__BRA__4__KET____DOT__vx_register_file__DOT__registers__v0 
+	    = vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__rd;
+    }
+    // ALWAYS at VX_register_file.v:36
+    if (VL_UNLIKELY((((0U != (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb)) 
+		      & (0U != (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__rd))) 
+		     & vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_wb_valid
+		     [3U]))) {
+	VL_WRITEF("RF: Writing %x to %2#\n",32,vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_write_data
+		  [3U],5,vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__rd);
+	__Vdlyvval__Vortex__DOT__vx_decode__DOT__gen_code_label__BRA__3__KET____DOT__vx_register_file__DOT__registers__v0 
+	    = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_write_data
+	    [3U];
+	__Vdlyvset__Vortex__DOT__vx_decode__DOT__gen_code_label__BRA__3__KET____DOT__vx_register_file__DOT__registers__v0 = 1U;
+	__Vdlyvdim0__Vortex__DOT__vx_decode__DOT__gen_code_label__BRA__3__KET____DOT__vx_register_file__DOT__registers__v0 
+	    = vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__rd;
+    }
+    // ALWAYS at VX_register_file.v:36
+    if (VL_UNLIKELY((((0U != (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb)) 
+		      & (0U != (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__rd))) 
+		     & vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_wb_valid
+		     [2U]))) {
+	VL_WRITEF("RF: Writing %x to %2#\n",32,vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_write_data
+		  [2U],5,vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__rd);
+	__Vdlyvval__Vortex__DOT__vx_decode__DOT__gen_code_label__BRA__2__KET____DOT__vx_register_file__DOT__registers__v0 
+	    = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_write_data
+	    [2U];
+	__Vdlyvset__Vortex__DOT__vx_decode__DOT__gen_code_label__BRA__2__KET____DOT__vx_register_file__DOT__registers__v0 = 1U;
+	__Vdlyvdim0__Vortex__DOT__vx_decode__DOT__gen_code_label__BRA__2__KET____DOT__vx_register_file__DOT__registers__v0 
+	    = vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__rd;
+    }
+    // ALWAYS at VX_register_file.v:36
     if (VL_UNLIKELY((((0U != (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb)) 
 		      & (0U != (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__rd))) 
 		     & vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_wb_valid
 		     [1U]))) {
 	VL_WRITEF("RF: Writing %x to %2#\n",32,vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_write_data
 		  [1U],5,vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__rd);
-	__Vdlyvval__Vortex__DOT__vx_decode__DOT__vx_register_file_1__DOT__registers__v0 
+	__Vdlyvval__Vortex__DOT__vx_decode__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file__DOT__registers__v0 
 	    = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_write_data
 	    [1U];
-	__Vdlyvset__Vortex__DOT__vx_decode__DOT__vx_register_file_1__DOT__registers__v0 = 1U;
-	__Vdlyvdim0__Vortex__DOT__vx_decode__DOT__vx_register_file_1__DOT__registers__v0 
+	__Vdlyvset__Vortex__DOT__vx_decode__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file__DOT__registers__v0 = 1U;
+	__Vdlyvdim0__Vortex__DOT__vx_decode__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file__DOT__registers__v0 
 	    = vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__rd;
     }
     // ALWAYS at VX_register_file.v:36
@@ -532,11 +586,11 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__2(VVortex__Syms* __restrict vlSymsp)
 		     [0U]))) {
 	VL_WRITEF("RF: Writing %x to %2#\n",32,vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_write_data
 		  [0U],5,vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__rd);
-	__Vdlyvval__Vortex__DOT__vx_decode__DOT__vx_register_file_0__DOT__registers__v0 
+	__Vdlyvval__Vortex__DOT__vx_decode__DOT__gen_code_label__BRA__0__KET____DOT__vx_register_file__DOT__registers__v0 
 	    = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_write_data
 	    [0U];
-	__Vdlyvset__Vortex__DOT__vx_decode__DOT__vx_register_file_0__DOT__registers__v0 = 1U;
-	__Vdlyvdim0__Vortex__DOT__vx_decode__DOT__vx_register_file_0__DOT__registers__v0 
+	__Vdlyvset__Vortex__DOT__vx_decode__DOT__gen_code_label__BRA__0__KET____DOT__vx_register_file__DOT__registers__v0 = 1U;
+	__Vdlyvdim0__Vortex__DOT__vx_decode__DOT__gen_code_label__BRA__0__KET____DOT__vx_register_file__DOT__registers__v0 
 	    = vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__rd;
     }
     // ALWAYS at VX_d_e_reg.v:138
@@ -654,17 +708,6 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__2(VVortex__Syms* __restrict vlSymsp)
 	= __Vdlyvval__Vortex__DOT__vx_m_w_reg__DOT__alu_result__v3;
     vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__alu_result[0U] 
 	= __Vdlyvval__Vortex__DOT__vx_m_w_reg__DOT__alu_result__v4;
-    // ALWAYSPOST at VX_d_e_reg.v:160
-    vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__valid[4U] 
-	= __Vdlyvval__Vortex__DOT__vx_d_e_reg__DOT__valid__v0;
-    vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__valid[3U] 
-	= __Vdlyvval__Vortex__DOT__vx_d_e_reg__DOT__valid__v1;
-    vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__valid[2U] 
-	= __Vdlyvval__Vortex__DOT__vx_d_e_reg__DOT__valid__v2;
-    vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__valid[1U] 
-	= __Vdlyvval__Vortex__DOT__vx_d_e_reg__DOT__valid__v3;
-    vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__valid[0U] 
-	= __Vdlyvval__Vortex__DOT__vx_d_e_reg__DOT__valid__v4;
     // ALWAYSPOST at VX_e_m_reg.v:128
     vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__alu_result[4U] 
 	= __Vdlyvval__Vortex__DOT__vx_e_m_reg__DOT__alu_result__v0;
@@ -676,15 +719,41 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__2(VVortex__Syms* __restrict vlSymsp)
 	= __Vdlyvval__Vortex__DOT__vx_e_m_reg__DOT__alu_result__v3;
     vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__alu_result[0U] 
 	= __Vdlyvval__Vortex__DOT__vx_e_m_reg__DOT__alu_result__v4;
+    // ALWAYSPOST at VX_d_e_reg.v:160
+    vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__valid[4U] 
+	= __Vdlyvval__Vortex__DOT__vx_d_e_reg__DOT__valid__v0;
+    vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__valid[3U] 
+	= __Vdlyvval__Vortex__DOT__vx_d_e_reg__DOT__valid__v1;
+    vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__valid[2U] 
+	= __Vdlyvval__Vortex__DOT__vx_d_e_reg__DOT__valid__v2;
+    vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__valid[1U] 
+	= __Vdlyvval__Vortex__DOT__vx_d_e_reg__DOT__valid__v3;
+    vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__valid[0U] 
+	= __Vdlyvval__Vortex__DOT__vx_d_e_reg__DOT__valid__v4;
     // ALWAYSPOST at VX_register_file.v:39
-    if (__Vdlyvset__Vortex__DOT__vx_decode__DOT__vx_register_file_1__DOT__registers__v0) {
-	vlTOPp->Vortex__DOT__vx_decode__DOT__vx_register_file_1__DOT__registers[__Vdlyvdim0__Vortex__DOT__vx_decode__DOT__vx_register_file_1__DOT__registers__v0] 
-	    = __Vdlyvval__Vortex__DOT__vx_decode__DOT__vx_register_file_1__DOT__registers__v0;
+    if (__Vdlyvset__Vortex__DOT__vx_decode__DOT__gen_code_label__BRA__4__KET____DOT__vx_register_file__DOT__registers__v0) {
+	vlTOPp->Vortex__DOT__vx_decode__DOT__gen_code_label__BRA__4__KET____DOT__vx_register_file__DOT__registers[__Vdlyvdim0__Vortex__DOT__vx_decode__DOT__gen_code_label__BRA__4__KET____DOT__vx_register_file__DOT__registers__v0] 
+	    = __Vdlyvval__Vortex__DOT__vx_decode__DOT__gen_code_label__BRA__4__KET____DOT__vx_register_file__DOT__registers__v0;
     }
     // ALWAYSPOST at VX_register_file.v:39
-    if (__Vdlyvset__Vortex__DOT__vx_decode__DOT__vx_register_file_0__DOT__registers__v0) {
-	vlTOPp->Vortex__DOT__vx_decode__DOT__vx_register_file_0__DOT__registers[__Vdlyvdim0__Vortex__DOT__vx_decode__DOT__vx_register_file_0__DOT__registers__v0] 
-	    = __Vdlyvval__Vortex__DOT__vx_decode__DOT__vx_register_file_0__DOT__registers__v0;
+    if (__Vdlyvset__Vortex__DOT__vx_decode__DOT__gen_code_label__BRA__3__KET____DOT__vx_register_file__DOT__registers__v0) {
+	vlTOPp->Vortex__DOT__vx_decode__DOT__gen_code_label__BRA__3__KET____DOT__vx_register_file__DOT__registers[__Vdlyvdim0__Vortex__DOT__vx_decode__DOT__gen_code_label__BRA__3__KET____DOT__vx_register_file__DOT__registers__v0] 
+	    = __Vdlyvval__Vortex__DOT__vx_decode__DOT__gen_code_label__BRA__3__KET____DOT__vx_register_file__DOT__registers__v0;
+    }
+    // ALWAYSPOST at VX_register_file.v:39
+    if (__Vdlyvset__Vortex__DOT__vx_decode__DOT__gen_code_label__BRA__2__KET____DOT__vx_register_file__DOT__registers__v0) {
+	vlTOPp->Vortex__DOT__vx_decode__DOT__gen_code_label__BRA__2__KET____DOT__vx_register_file__DOT__registers[__Vdlyvdim0__Vortex__DOT__vx_decode__DOT__gen_code_label__BRA__2__KET____DOT__vx_register_file__DOT__registers__v0] 
+	    = __Vdlyvval__Vortex__DOT__vx_decode__DOT__gen_code_label__BRA__2__KET____DOT__vx_register_file__DOT__registers__v0;
+    }
+    // ALWAYSPOST at VX_register_file.v:39
+    if (__Vdlyvset__Vortex__DOT__vx_decode__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file__DOT__registers__v0) {
+	vlTOPp->Vortex__DOT__vx_decode__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file__DOT__registers[__Vdlyvdim0__Vortex__DOT__vx_decode__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file__DOT__registers__v0] 
+	    = __Vdlyvval__Vortex__DOT__vx_decode__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file__DOT__registers__v0;
+    }
+    // ALWAYSPOST at VX_register_file.v:39
+    if (__Vdlyvset__Vortex__DOT__vx_decode__DOT__gen_code_label__BRA__0__KET____DOT__vx_register_file__DOT__registers__v0) {
+	vlTOPp->Vortex__DOT__vx_decode__DOT__gen_code_label__BRA__0__KET____DOT__vx_register_file__DOT__registers[__Vdlyvdim0__Vortex__DOT__vx_decode__DOT__gen_code_label__BRA__0__KET____DOT__vx_register_file__DOT__registers__v0] 
+	    = __Vdlyvval__Vortex__DOT__vx_decode__DOT__gen_code_label__BRA__0__KET____DOT__vx_register_file__DOT__registers__v0;
     }
     // ALWAYSPOST at VX_d_e_reg.v:143
     vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__a_reg_data[4U] 
@@ -788,6 +857,21 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__2(VVortex__Syms* __restrict vlSymsp)
     vlTOPp->Vortex__DOT____Vcellout__vx_m_w_reg__out_alu_result[0U] 
 	= vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__alu_result
 	[0U];
+    vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_alu_result[4U] 
+	= vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__alu_result
+	[4U];
+    vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_alu_result[3U] 
+	= vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__alu_result
+	[3U];
+    vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_alu_result[2U] 
+	= vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__alu_result
+	[2U];
+    vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_alu_result[1U] 
+	= vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__alu_result
+	[1U];
+    vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_alu_result[0U] 
+	= vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__alu_result
+	[0U];
     // ALWAYS at VX_d_e_reg.v:138
     vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__branch_type 
 	= ((IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__stalling)
@@ -888,21 +972,6 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__2(VVortex__Syms* __restrict vlSymsp)
 					   >> 0x14U))))
 				 ? 0xb0000000U : 0xdeadbeefU)
 			     : 0xdeadbeefU))));
-    vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_alu_result[4U] 
-	= vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__alu_result
-	[4U];
-    vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_alu_result[3U] 
-	= vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__alu_result
-	[3U];
-    vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_alu_result[2U] 
-	= vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__alu_result
-	[2U];
-    vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_alu_result[1U] 
-	= vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__alu_result
-	[1U];
-    vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_alu_result[0U] 
-	= vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__alu_result
-	[0U];
     vlTOPp->Vortex__DOT__vx_writeback__DOT__out_pc_data[0U] 
 	= vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__PC_next;
     vlTOPp->Vortex__DOT__vx_writeback__DOT__out_pc_data[1U] 
@@ -1019,16 +1088,6 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__2(VVortex__Syms* __restrict vlSymsp)
 	[1U];
     vlTOPp->Vortex__DOT__m_w_alu_result[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_m_w_reg__out_alu_result
 	[0U];
-    vlTOPp->Vortex__DOT__d_e_valid[4U] = vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_valid
-	[4U];
-    vlTOPp->Vortex__DOT__d_e_valid[3U] = vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_valid
-	[3U];
-    vlTOPp->Vortex__DOT__d_e_valid[2U] = vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_valid
-	[2U];
-    vlTOPp->Vortex__DOT__d_e_valid[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_valid
-	[1U];
-    vlTOPp->Vortex__DOT__d_e_valid[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_valid
-	[0U];
     vlTOPp->Vortex__DOT__e_m_alu_result[4U] = vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_alu_result
 	[4U];
     vlTOPp->Vortex__DOT__e_m_alu_result[3U] = vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_alu_result
@@ -1039,6 +1098,16 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__2(VVortex__Syms* __restrict vlSymsp)
 	[1U];
     vlTOPp->Vortex__DOT__e_m_alu_result[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_alu_result
 	[0U];
+    vlTOPp->Vortex__DOT__d_e_valid[4U] = vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_valid
+	[4U];
+    vlTOPp->Vortex__DOT__d_e_valid[3U] = vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_valid
+	[3U];
+    vlTOPp->Vortex__DOT__d_e_valid[2U] = vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_valid
+	[2U];
+    vlTOPp->Vortex__DOT__d_e_valid[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_valid
+	[1U];
+    vlTOPp->Vortex__DOT__d_e_valid[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_valid
+	[0U];
     vlTOPp->Vortex__DOT__d_e_a_reg_data[4U] = vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_a_reg_data
 	[4U];
     vlTOPp->Vortex__DOT__d_e_a_reg_data[3U] = vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_a_reg_data
@@ -1161,6 +1230,16 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__2(VVortex__Syms* __restrict vlSymsp)
 	= vlTOPp->Vortex__DOT__m_w_alu_result[1U];
     vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_writeback_alu_result[0U] 
 	= vlTOPp->Vortex__DOT__m_w_alu_result[0U];
+    vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_alu_result[4U] 
+	= vlTOPp->Vortex__DOT__e_m_alu_result[4U];
+    vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_alu_result[3U] 
+	= vlTOPp->Vortex__DOT__e_m_alu_result[3U];
+    vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_alu_result[2U] 
+	= vlTOPp->Vortex__DOT__e_m_alu_result[2U];
+    vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_alu_result[1U] 
+	= vlTOPp->Vortex__DOT__e_m_alu_result[1U];
+    vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_alu_result[0U] 
+	= vlTOPp->Vortex__DOT__e_m_alu_result[0U];
     vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_valid[4U] 
 	= vlTOPp->Vortex__DOT__d_e_valid[4U];
     vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_valid[3U] 
@@ -1174,16 +1253,6 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__2(VVortex__Syms* __restrict vlSymsp)
     vlTOPp->Vortex__DOT__execute_branch_stall = ((0U 
 						  != (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__branch_type)) 
 						 | (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__jal));
-    vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_alu_result[4U] 
-	= vlTOPp->Vortex__DOT__e_m_alu_result[4U];
-    vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_alu_result[3U] 
-	= vlTOPp->Vortex__DOT__e_m_alu_result[3U];
-    vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_alu_result[2U] 
-	= vlTOPp->Vortex__DOT__e_m_alu_result[2U];
-    vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_alu_result[1U] 
-	= vlTOPp->Vortex__DOT__e_m_alu_result[1U];
-    vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_alu_result[0U] 
-	= vlTOPp->Vortex__DOT__e_m_alu_result[0U];
     vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_memory_PC_next[0U] 
 	= vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__PC_next;
     vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_memory_PC_next[1U] 
@@ -1327,21 +1396,6 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__2(VVortex__Syms* __restrict vlSymsp)
 		    ? vlTOPp->Vortex__DOT____Vcellinp__vx_writeback__in_alu_result
 		   [0U] : vlTOPp->Vortex__DOT____Vcellinp__vx_writeback__in_mem_result
 		   [0U]));
-    vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_valid[4U] 
-	= vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_valid
-	[4U];
-    vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_valid[3U] 
-	= vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_valid
-	[3U];
-    vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_valid[2U] 
-	= vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_valid
-	[2U];
-    vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_valid[1U] 
-	= vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_valid
-	[1U];
-    vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_valid[0U] 
-	= vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_valid
-	[0U];
     // ALWAYS at VX_memory.v:74
     vlTOPp->Vortex__DOT__memory_branch_dir = (1U & 
 					      ((4U 
@@ -1418,6 +1472,21 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__2(VVortex__Syms* __restrict vlSymsp)
     vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_alu_result[0U] 
 	= vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_alu_result
 	[0U];
+    vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_valid[4U] 
+	= vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_valid
+	[4U];
+    vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_valid[3U] 
+	= vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_valid
+	[3U];
+    vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_valid[2U] 
+	= vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_valid
+	[2U];
+    vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_valid[1U] 
+	= vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_valid
+	[1U];
+    vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_valid[0U] 
+	= vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_valid
+	[0U];
     vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_b_reg_data[4U] 
 	= vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_b_reg_data
 	[4U];
@@ -1433,16 +1502,31 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__2(VVortex__Syms* __restrict vlSymsp)
     vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_b_reg_data[0U] 
 	= vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_b_reg_data
 	[0U];
-    vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_0__DOT__ALU_in2 
+    vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__0__KET____DOT__vx_alu__DOT__ALU_in2 
 	= ((IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__rs2_src)
 	    ? vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__itype_immed
 	    : vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_b_reg_data
 	   [0U]);
-    vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_1__DOT__ALU_in2 
+    vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__1__KET____DOT__vx_alu__DOT__ALU_in2 
 	= ((IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__rs2_src)
 	    ? vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__itype_immed
 	    : vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_b_reg_data
 	   [1U]);
+    vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__2__KET____DOT__vx_alu__DOT__ALU_in2 
+	= ((IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__rs2_src)
+	    ? vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__itype_immed
+	    : vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_b_reg_data
+	   [2U]);
+    vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__3__KET____DOT__vx_alu__DOT__ALU_in2 
+	= ((IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__rs2_src)
+	    ? vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__itype_immed
+	    : vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_b_reg_data
+	   [3U]);
+    vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__4__KET____DOT__vx_alu__DOT__ALU_in2 
+	= ((IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__rs2_src)
+	    ? vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__itype_immed
+	    : vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_b_reg_data
+	   [4U]);
     vlTOPp->out_cache_driver_in_data[4U] = vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_data
 	[4U];
     vlTOPp->out_cache_driver_in_data[3U] = vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_data
@@ -1488,16 +1572,6 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__2(VVortex__Syms* __restrict vlSymsp)
     vlTOPp->Vortex__DOT__writeback_write_data[0U] = 
 	vlTOPp->Vortex__DOT____Vcellout__vx_writeback__out_write_data
 	[0U];
-    vlTOPp->Vortex__DOT__execute_valid[4U] = vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_valid
-	[4U];
-    vlTOPp->Vortex__DOT__execute_valid[3U] = vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_valid
-	[3U];
-    vlTOPp->Vortex__DOT__execute_valid[2U] = vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_valid
-	[2U];
-    vlTOPp->Vortex__DOT__execute_valid[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_valid
-	[1U];
-    vlTOPp->Vortex__DOT__execute_valid[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_valid
-	[0U];
     vlTOPp->out_cache_driver_in_address[4U] = vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_address
 	[4U];
     vlTOPp->out_cache_driver_in_address[3U] = vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_address
@@ -1518,6 +1592,16 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__2(VVortex__Syms* __restrict vlSymsp)
 	[1U];
     vlTOPp->Vortex__DOT__memory_alu_result[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_alu_result
 	[0U];
+    vlTOPp->Vortex__DOT__execute_valid[4U] = vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_valid
+	[4U];
+    vlTOPp->Vortex__DOT__execute_valid[3U] = vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_valid
+	[3U];
+    vlTOPp->Vortex__DOT__execute_valid[2U] = vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_valid
+	[2U];
+    vlTOPp->Vortex__DOT__execute_valid[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_valid
+	[1U];
+    vlTOPp->Vortex__DOT__execute_valid[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_valid
+	[0U];
     vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_execute_PC_next[0U] 
 	= vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__PC_next_out;
     vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_execute_PC_next[1U] 
@@ -1590,16 +1674,31 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__2(VVortex__Syms* __restrict vlSymsp)
 	[1U];
     vlTOPp->Vortex__DOT__execute_b_reg_data[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_b_reg_data
 	[0U];
-    vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_0__DOT__mult_signed_result 
+    vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__0__KET____DOT__vx_alu__DOT__mult_signed_result 
 	= VL_MULS_QQQ(64,64,64, VL_EXTENDS_QI(64,32, 
 					      vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data
 					      [0U]), 
-		      VL_EXTENDS_QI(64,32, vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_0__DOT__ALU_in2));
-    vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_1__DOT__mult_signed_result 
+		      VL_EXTENDS_QI(64,32, vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__0__KET____DOT__vx_alu__DOT__ALU_in2));
+    vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__1__KET____DOT__vx_alu__DOT__mult_signed_result 
 	= VL_MULS_QQQ(64,64,64, VL_EXTENDS_QI(64,32, 
 					      vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data
 					      [1U]), 
-		      VL_EXTENDS_QI(64,32, vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_1__DOT__ALU_in2));
+		      VL_EXTENDS_QI(64,32, vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__1__KET____DOT__vx_alu__DOT__ALU_in2));
+    vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__2__KET____DOT__vx_alu__DOT__mult_signed_result 
+	= VL_MULS_QQQ(64,64,64, VL_EXTENDS_QI(64,32, 
+					      vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data
+					      [2U]), 
+		      VL_EXTENDS_QI(64,32, vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__2__KET____DOT__vx_alu__DOT__ALU_in2));
+    vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__3__KET____DOT__vx_alu__DOT__mult_signed_result 
+	= VL_MULS_QQQ(64,64,64, VL_EXTENDS_QI(64,32, 
+					      vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data
+					      [3U]), 
+		      VL_EXTENDS_QI(64,32, vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__3__KET____DOT__vx_alu__DOT__ALU_in2));
+    vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__4__KET____DOT__vx_alu__DOT__mult_signed_result 
+	= VL_MULS_QQQ(64,64,64, VL_EXTENDS_QI(64,32, 
+					      vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data
+					      [4U]), 
+		      VL_EXTENDS_QI(64,32, vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__4__KET____DOT__vx_alu__DOT__ALU_in2));
     vlTOPp->Vortex__DOT____Vcellinp__vx_m_w_reg__in_valid[4U] 
 	= vlTOPp->Vortex__DOT__memory_valid[4U];
     vlTOPp->Vortex__DOT____Vcellinp__vx_m_w_reg__in_valid[3U] 
@@ -1625,16 +1724,6 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__2(VVortex__Syms* __restrict vlSymsp)
     vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_write_data[0U] 
 	= vlTOPp->Vortex__DOT__writeback_write_data
 	[0U];
-    vlTOPp->Vortex__DOT____Vcellinp__vx_e_m_reg__in_valid[4U] 
-	= vlTOPp->Vortex__DOT__execute_valid[4U];
-    vlTOPp->Vortex__DOT____Vcellinp__vx_e_m_reg__in_valid[3U] 
-	= vlTOPp->Vortex__DOT__execute_valid[3U];
-    vlTOPp->Vortex__DOT____Vcellinp__vx_e_m_reg__in_valid[2U] 
-	= vlTOPp->Vortex__DOT__execute_valid[2U];
-    vlTOPp->Vortex__DOT____Vcellinp__vx_e_m_reg__in_valid[1U] 
-	= vlTOPp->Vortex__DOT__execute_valid[1U];
-    vlTOPp->Vortex__DOT____Vcellinp__vx_e_m_reg__in_valid[0U] 
-	= vlTOPp->Vortex__DOT__execute_valid[0U];
     vlTOPp->Vortex__DOT____Vcellinp__vx_m_w_reg__in_alu_result[4U] 
 	= vlTOPp->Vortex__DOT__memory_alu_result[4U];
     vlTOPp->Vortex__DOT____Vcellinp__vx_m_w_reg__in_alu_result[3U] 
@@ -1655,6 +1744,16 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__2(VVortex__Syms* __restrict vlSymsp)
 	= vlTOPp->Vortex__DOT__memory_alu_result[1U];
     vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_memory_alu_result[0U] 
 	= vlTOPp->Vortex__DOT__memory_alu_result[0U];
+    vlTOPp->Vortex__DOT____Vcellinp__vx_e_m_reg__in_valid[4U] 
+	= vlTOPp->Vortex__DOT__execute_valid[4U];
+    vlTOPp->Vortex__DOT____Vcellinp__vx_e_m_reg__in_valid[3U] 
+	= vlTOPp->Vortex__DOT__execute_valid[3U];
+    vlTOPp->Vortex__DOT____Vcellinp__vx_e_m_reg__in_valid[2U] 
+	= vlTOPp->Vortex__DOT__execute_valid[2U];
+    vlTOPp->Vortex__DOT____Vcellinp__vx_e_m_reg__in_valid[1U] 
+	= vlTOPp->Vortex__DOT__execute_valid[1U];
+    vlTOPp->Vortex__DOT____Vcellinp__vx_e_m_reg__in_valid[0U] 
+	= vlTOPp->Vortex__DOT__execute_valid[0U];
     vlTOPp->Vortex__DOT____Vcellinp__vx_e_m_reg__in_b_reg_data[4U] 
 	= vlTOPp->Vortex__DOT__execute_b_reg_data[4U];
     vlTOPp->Vortex__DOT____Vcellinp__vx_e_m_reg__in_b_reg_data[3U] 
@@ -1668,39 +1767,39 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__2(VVortex__Syms* __restrict vlSymsp)
     // ALWAYS at VX_alu.v:48
     if ((0x10U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))) {
 	if ((8U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))) {
-	    vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellout__vx_alu_0__out_alu_result = 0U;
+	    vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellout__genblk1__BRA__0__KET____DOT__vx_alu__out_alu_result = 0U;
 	} else {
 	    if ((4U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))) {
-		vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellout__vx_alu_0__out_alu_result 
+		vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellout__genblk1__BRA__0__KET____DOT__vx_alu__out_alu_result 
 		    = ((2U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
 		        ? ((1U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
-			    ? ((0U == vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_0__DOT__ALU_in2)
+			    ? ((0U == vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__0__KET____DOT__vx_alu__DOT__ALU_in2)
 			        ? vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data
 			       [0U] : VL_MODDIV_III(32, 
 						    vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data
-						    [0U], vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_0__DOT__ALU_in2))
-			    : ((0U == vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_0__DOT__ALU_in2)
+						    [0U], vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__0__KET____DOT__vx_alu__DOT__ALU_in2))
+			    : ((0U == vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__0__KET____DOT__vx_alu__DOT__ALU_in2)
 			        ? vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data
 			       [0U] : VL_MODDIVS_III(32, 
 						     vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data
-						     [0U], vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_0__DOT__ALU_in2)))
+						     [0U], vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__0__KET____DOT__vx_alu__DOT__ALU_in2)))
 		        : ((1U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
-			    ? ((0U == vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_0__DOT__ALU_in2)
+			    ? ((0U == vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__0__KET____DOT__vx_alu__DOT__ALU_in2)
 			        ? 0xffffffffU : VL_DIV_III(32, 
 							   vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data
-							   [0U], vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_0__DOT__ALU_in2))
-			    : ((0U == vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_0__DOT__ALU_in2)
+							   [0U], vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__0__KET____DOT__vx_alu__DOT__ALU_in2))
+			    : ((0U == vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__0__KET____DOT__vx_alu__DOT__ALU_in2)
 			        ? 0xffffffffU : VL_DIVS_III(32, 
 							    vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data
-							    [0U], vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_0__DOT__ALU_in2))));
+							    [0U], vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__0__KET____DOT__vx_alu__DOT__ALU_in2))));
 	    } else {
 		if ((2U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))) {
-		    vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellout__vx_alu_0__out_alu_result 
+		    vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellout__genblk1__BRA__0__KET____DOT__vx_alu__out_alu_result 
 			= ((1U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
 			    ? (IData)((((QData)((IData)(
 							vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data
 							[0U])) 
-					* (QData)((IData)(vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_0__DOT__ALU_in2))) 
+					* (QData)((IData)(vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__0__KET____DOT__vx_alu__DOT__ALU_in2))) 
 				       >> 0x20U)) : (IData)(
 							    (((((QData)((IData)(
 										VL_NEGATE_I((IData)(
@@ -1712,27 +1811,27 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__2(VVortex__Syms* __restrict vlSymsp)
 							       | (QData)((IData)(
 										vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data
 										[0U]))) 
-							      * (QData)((IData)(vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_0__DOT__ALU_in2))) 
+							      * (QData)((IData)(vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__0__KET____DOT__vx_alu__DOT__ALU_in2))) 
 							     >> 0x20U)));
 		} else {
 		    if (VL_LIKELY((1U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)))) {
-			vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellout__vx_alu_0__out_alu_result 
-			    = (IData)((vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_0__DOT__mult_signed_result 
+			vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellout__genblk1__BRA__0__KET____DOT__vx_alu__out_alu_result 
+			    = (IData)((vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__0__KET____DOT__vx_alu__DOT__mult_signed_result 
 				       >> 0x20U));
 		    } else {
-			vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellout__vx_alu_0__out_alu_result 
-			    = (IData)(vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_0__DOT__mult_signed_result);
+			vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellout__genblk1__BRA__0__KET____DOT__vx_alu__out_alu_result 
+			    = (IData)(vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__0__KET____DOT__vx_alu__DOT__mult_signed_result);
 			VL_WRITEF("(%x) %x * %x = %x\n",
 				  32,vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__curr_PC,
 				  32,vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data
-				  [0U],32,vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_0__DOT__ALU_in2,
-				  32,vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellout__vx_alu_0__out_alu_result);
+				  [0U],32,vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__0__KET____DOT__vx_alu__DOT__ALU_in2,
+				  32,vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellout__genblk1__BRA__0__KET____DOT__vx_alu__out_alu_result);
 		    }
 		}
 	    }
 	}
     } else {
-	vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellout__vx_alu_0__out_alu_result 
+	vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellout__genblk1__BRA__0__KET____DOT__vx_alu__out_alu_result 
 	    = ((8U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
 	        ? ((4U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
 		    ? ((2U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
@@ -1752,20 +1851,20 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__2(VVortex__Syms* __restrict vlSymsp)
 						   : 
 						  ((vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data
 						    [0U] 
-						    >= vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_0__DOT__ALU_in2)
+						    >= vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__0__KET____DOT__vx_alu__DOT__ALU_in2)
 						    ? 0U
 						    : 0xffffffffU))
 						  : 
 						 ((1U 
 						   & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
 						   ? 
-						  (vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_0__DOT__ALU_in2 
+						  (vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__0__KET____DOT__vx_alu__DOT__ALU_in2 
 						   & vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data
 						   [0U])
 						   : 
 						  (vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data
 						   [0U] 
-						   | vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_0__DOT__ALU_in2))))
+						   | vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__0__KET____DOT__vx_alu__DOT__ALU_in2))))
 	        : ((4U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
 		    ? ((2U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
 		        ? ((1U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
@@ -1773,14 +1872,14 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__2(VVortex__Syms* __restrict vlSymsp)
 					     vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data
 					     [0U], 
 					     (0x1fU 
-					      & vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_0__DOT__ALU_in2))
+					      & vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__0__KET____DOT__vx_alu__DOT__ALU_in2))
 			    : (vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data
-			       [0U] >> (0x1fU & vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_0__DOT__ALU_in2)))
+			       [0U] >> (0x1fU & vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__0__KET____DOT__vx_alu__DOT__ALU_in2)))
 		        : ((1U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
 			    ? (vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data
-			       [0U] ^ vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_0__DOT__ALU_in2)
+			       [0U] ^ vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__0__KET____DOT__vx_alu__DOT__ALU_in2)
 			    : ((vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data
-				[0U] < vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_0__DOT__ALU_in2)
+				[0U] < vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__0__KET____DOT__vx_alu__DOT__ALU_in2)
 			        ? 1U : 0U))) : ((2U 
 						 & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
 						 ? 
@@ -1789,7 +1888,7 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__2(VVortex__Syms* __restrict vlSymsp)
 						  ? 
 						 (VL_LTS_III(1,32,32, 
 							     vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data
-							     [0U], vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_0__DOT__ALU_in2)
+							     [0U], vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__0__KET____DOT__vx_alu__DOT__ALU_in2)
 						   ? 1U
 						   : 0U)
 						  : 
@@ -1797,55 +1896,55 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__2(VVortex__Syms* __restrict vlSymsp)
 						  [0U] 
 						  << 
 						  (0x1fU 
-						   & vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_0__DOT__ALU_in2)))
+						   & vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__0__KET____DOT__vx_alu__DOT__ALU_in2)))
 						 : 
 						((1U 
 						  & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
 						  ? 
 						 (vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data
 						  [0U] 
-						  - vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_0__DOT__ALU_in2)
+						  - vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__0__KET____DOT__vx_alu__DOT__ALU_in2)
 						  : 
 						 (vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data
 						  [0U] 
-						  + vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_0__DOT__ALU_in2)))));
+						  + vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__0__KET____DOT__vx_alu__DOT__ALU_in2)))));
     }
     // ALWAYS at VX_alu.v:48
     if ((0x10U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))) {
 	if ((8U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))) {
-	    vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellout__vx_alu_1__out_alu_result = 0U;
+	    vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellout__genblk1__BRA__1__KET____DOT__vx_alu__out_alu_result = 0U;
 	} else {
 	    if ((4U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))) {
-		vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellout__vx_alu_1__out_alu_result 
+		vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellout__genblk1__BRA__1__KET____DOT__vx_alu__out_alu_result 
 		    = ((2U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
 		        ? ((1U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
-			    ? ((0U == vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_1__DOT__ALU_in2)
+			    ? ((0U == vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__1__KET____DOT__vx_alu__DOT__ALU_in2)
 			        ? vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data
 			       [1U] : VL_MODDIV_III(32, 
 						    vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data
-						    [1U], vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_1__DOT__ALU_in2))
-			    : ((0U == vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_1__DOT__ALU_in2)
+						    [1U], vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__1__KET____DOT__vx_alu__DOT__ALU_in2))
+			    : ((0U == vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__1__KET____DOT__vx_alu__DOT__ALU_in2)
 			        ? vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data
 			       [1U] : VL_MODDIVS_III(32, 
 						     vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data
-						     [1U], vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_1__DOT__ALU_in2)))
+						     [1U], vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__1__KET____DOT__vx_alu__DOT__ALU_in2)))
 		        : ((1U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
-			    ? ((0U == vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_1__DOT__ALU_in2)
+			    ? ((0U == vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__1__KET____DOT__vx_alu__DOT__ALU_in2)
 			        ? 0xffffffffU : VL_DIV_III(32, 
 							   vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data
-							   [1U], vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_1__DOT__ALU_in2))
-			    : ((0U == vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_1__DOT__ALU_in2)
+							   [1U], vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__1__KET____DOT__vx_alu__DOT__ALU_in2))
+			    : ((0U == vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__1__KET____DOT__vx_alu__DOT__ALU_in2)
 			        ? 0xffffffffU : VL_DIVS_III(32, 
 							    vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data
-							    [1U], vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_1__DOT__ALU_in2))));
+							    [1U], vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__1__KET____DOT__vx_alu__DOT__ALU_in2))));
 	    } else {
 		if ((2U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))) {
-		    vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellout__vx_alu_1__out_alu_result 
+		    vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellout__genblk1__BRA__1__KET____DOT__vx_alu__out_alu_result 
 			= ((1U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
 			    ? (IData)((((QData)((IData)(
 							vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data
 							[1U])) 
-					* (QData)((IData)(vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_1__DOT__ALU_in2))) 
+					* (QData)((IData)(vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__1__KET____DOT__vx_alu__DOT__ALU_in2))) 
 				       >> 0x20U)) : (IData)(
 							    (((((QData)((IData)(
 										VL_NEGATE_I((IData)(
@@ -1857,27 +1956,27 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__2(VVortex__Syms* __restrict vlSymsp)
 							       | (QData)((IData)(
 										vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data
 										[1U]))) 
-							      * (QData)((IData)(vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_1__DOT__ALU_in2))) 
+							      * (QData)((IData)(vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__1__KET____DOT__vx_alu__DOT__ALU_in2))) 
 							     >> 0x20U)));
 		} else {
 		    if (VL_LIKELY((1U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)))) {
-			vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellout__vx_alu_1__out_alu_result 
-			    = (IData)((vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_1__DOT__mult_signed_result 
+			vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellout__genblk1__BRA__1__KET____DOT__vx_alu__out_alu_result 
+			    = (IData)((vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__1__KET____DOT__vx_alu__DOT__mult_signed_result 
 				       >> 0x20U));
 		    } else {
-			vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellout__vx_alu_1__out_alu_result 
-			    = (IData)(vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_1__DOT__mult_signed_result);
+			vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellout__genblk1__BRA__1__KET____DOT__vx_alu__out_alu_result 
+			    = (IData)(vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__1__KET____DOT__vx_alu__DOT__mult_signed_result);
 			VL_WRITEF("(%x) %x * %x = %x\n",
 				  32,vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__curr_PC,
 				  32,vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data
-				  [1U],32,vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_1__DOT__ALU_in2,
-				  32,vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellout__vx_alu_1__out_alu_result);
+				  [1U],32,vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__1__KET____DOT__vx_alu__DOT__ALU_in2,
+				  32,vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellout__genblk1__BRA__1__KET____DOT__vx_alu__out_alu_result);
 		    }
 		}
 	    }
 	}
     } else {
-	vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellout__vx_alu_1__out_alu_result 
+	vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellout__genblk1__BRA__1__KET____DOT__vx_alu__out_alu_result 
 	    = ((8U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
 	        ? ((4U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
 		    ? ((2U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
@@ -1897,20 +1996,20 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__2(VVortex__Syms* __restrict vlSymsp)
 						   : 
 						  ((vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data
 						    [1U] 
-						    >= vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_1__DOT__ALU_in2)
+						    >= vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__1__KET____DOT__vx_alu__DOT__ALU_in2)
 						    ? 0U
 						    : 0xffffffffU))
 						  : 
 						 ((1U 
 						   & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
 						   ? 
-						  (vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_1__DOT__ALU_in2 
+						  (vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__1__KET____DOT__vx_alu__DOT__ALU_in2 
 						   & vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data
 						   [1U])
 						   : 
 						  (vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data
 						   [1U] 
-						   | vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_1__DOT__ALU_in2))))
+						   | vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__1__KET____DOT__vx_alu__DOT__ALU_in2))))
 	        : ((4U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
 		    ? ((2U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
 		        ? ((1U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
@@ -1918,14 +2017,14 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__2(VVortex__Syms* __restrict vlSymsp)
 					     vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data
 					     [1U], 
 					     (0x1fU 
-					      & vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_1__DOT__ALU_in2))
+					      & vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__1__KET____DOT__vx_alu__DOT__ALU_in2))
 			    : (vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data
-			       [1U] >> (0x1fU & vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_1__DOT__ALU_in2)))
+			       [1U] >> (0x1fU & vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__1__KET____DOT__vx_alu__DOT__ALU_in2)))
 		        : ((1U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
 			    ? (vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data
-			       [1U] ^ vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_1__DOT__ALU_in2)
+			       [1U] ^ vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__1__KET____DOT__vx_alu__DOT__ALU_in2)
 			    : ((vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data
-				[1U] < vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_1__DOT__ALU_in2)
+				[1U] < vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__1__KET____DOT__vx_alu__DOT__ALU_in2)
 			        ? 1U : 0U))) : ((2U 
 						 & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
 						 ? 
@@ -1934,7 +2033,7 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__2(VVortex__Syms* __restrict vlSymsp)
 						  ? 
 						 (VL_LTS_III(1,32,32, 
 							     vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data
-							     [1U], vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_1__DOT__ALU_in2)
+							     [1U], vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__1__KET____DOT__vx_alu__DOT__ALU_in2)
 						   ? 1U
 						   : 0U)
 						  : 
@@ -1942,23 +2041,464 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__2(VVortex__Syms* __restrict vlSymsp)
 						  [1U] 
 						  << 
 						  (0x1fU 
-						   & vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_1__DOT__ALU_in2)))
+						   & vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__1__KET____DOT__vx_alu__DOT__ALU_in2)))
 						 : 
 						((1U 
 						  & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
 						  ? 
 						 (vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data
 						  [1U] 
-						  - vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_1__DOT__ALU_in2)
+						  - vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__1__KET____DOT__vx_alu__DOT__ALU_in2)
 						  : 
 						 (vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data
 						  [1U] 
-						  + vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_1__DOT__ALU_in2)))));
+						  + vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__1__KET____DOT__vx_alu__DOT__ALU_in2)))));
+    }
+    // ALWAYS at VX_alu.v:48
+    if ((0x10U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))) {
+	if ((8U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))) {
+	    vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellout__genblk1__BRA__2__KET____DOT__vx_alu__out_alu_result = 0U;
+	} else {
+	    if ((4U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))) {
+		vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellout__genblk1__BRA__2__KET____DOT__vx_alu__out_alu_result 
+		    = ((2U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
+		        ? ((1U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
+			    ? ((0U == vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__2__KET____DOT__vx_alu__DOT__ALU_in2)
+			        ? vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data
+			       [2U] : VL_MODDIV_III(32, 
+						    vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data
+						    [2U], vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__2__KET____DOT__vx_alu__DOT__ALU_in2))
+			    : ((0U == vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__2__KET____DOT__vx_alu__DOT__ALU_in2)
+			        ? vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data
+			       [2U] : VL_MODDIVS_III(32, 
+						     vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data
+						     [2U], vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__2__KET____DOT__vx_alu__DOT__ALU_in2)))
+		        : ((1U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
+			    ? ((0U == vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__2__KET____DOT__vx_alu__DOT__ALU_in2)
+			        ? 0xffffffffU : VL_DIV_III(32, 
+							   vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data
+							   [2U], vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__2__KET____DOT__vx_alu__DOT__ALU_in2))
+			    : ((0U == vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__2__KET____DOT__vx_alu__DOT__ALU_in2)
+			        ? 0xffffffffU : VL_DIVS_III(32, 
+							    vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data
+							    [2U], vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__2__KET____DOT__vx_alu__DOT__ALU_in2))));
+	    } else {
+		if ((2U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))) {
+		    vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellout__genblk1__BRA__2__KET____DOT__vx_alu__out_alu_result 
+			= ((1U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
+			    ? (IData)((((QData)((IData)(
+							vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data
+							[2U])) 
+					* (QData)((IData)(vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__2__KET____DOT__vx_alu__DOT__ALU_in2))) 
+				       >> 0x20U)) : (IData)(
+							    (((((QData)((IData)(
+										VL_NEGATE_I((IData)(
+										(1U 
+										& (vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data
+										[2U] 
+										>> 0x1fU)))))) 
+								<< 0x20U) 
+							       | (QData)((IData)(
+										vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data
+										[2U]))) 
+							      * (QData)((IData)(vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__2__KET____DOT__vx_alu__DOT__ALU_in2))) 
+							     >> 0x20U)));
+		} else {
+		    if (VL_LIKELY((1U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)))) {
+			vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellout__genblk1__BRA__2__KET____DOT__vx_alu__out_alu_result 
+			    = (IData)((vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__2__KET____DOT__vx_alu__DOT__mult_signed_result 
+				       >> 0x20U));
+		    } else {
+			vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellout__genblk1__BRA__2__KET____DOT__vx_alu__out_alu_result 
+			    = (IData)(vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__2__KET____DOT__vx_alu__DOT__mult_signed_result);
+			VL_WRITEF("(%x) %x * %x = %x\n",
+				  32,vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__curr_PC,
+				  32,vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data
+				  [2U],32,vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__2__KET____DOT__vx_alu__DOT__ALU_in2,
+				  32,vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellout__genblk1__BRA__2__KET____DOT__vx_alu__out_alu_result);
+		    }
+		}
+	    }
+	}
+    } else {
+	vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellout__genblk1__BRA__2__KET____DOT__vx_alu__out_alu_result 
+	    = ((8U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
+	        ? ((4U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
+		    ? ((2U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
+		        ? vlTOPp->Vortex__DOT__csr_decode_csr_data
+		        : ((1U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
+			    ? vlTOPp->Vortex__DOT__csr_decode_csr_data
+			    : (vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__curr_PC 
+			       + (vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__upper_immed 
+				  << 0xcU)))) : ((2U 
+						  & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
+						  ? 
+						 ((1U 
+						   & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
+						   ? 
+						  (vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__upper_immed 
+						   << 0xcU)
+						   : 
+						  ((vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data
+						    [2U] 
+						    >= vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__2__KET____DOT__vx_alu__DOT__ALU_in2)
+						    ? 0U
+						    : 0xffffffffU))
+						  : 
+						 ((1U 
+						   & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
+						   ? 
+						  (vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__2__KET____DOT__vx_alu__DOT__ALU_in2 
+						   & vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data
+						   [2U])
+						   : 
+						  (vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data
+						   [2U] 
+						   | vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__2__KET____DOT__vx_alu__DOT__ALU_in2))))
+	        : ((4U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
+		    ? ((2U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
+		        ? ((1U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
+			    ? VL_SHIFTRS_III(32,32,5, 
+					     vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data
+					     [2U], 
+					     (0x1fU 
+					      & vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__2__KET____DOT__vx_alu__DOT__ALU_in2))
+			    : (vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data
+			       [2U] >> (0x1fU & vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__2__KET____DOT__vx_alu__DOT__ALU_in2)))
+		        : ((1U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
+			    ? (vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data
+			       [2U] ^ vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__2__KET____DOT__vx_alu__DOT__ALU_in2)
+			    : ((vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data
+				[2U] < vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__2__KET____DOT__vx_alu__DOT__ALU_in2)
+			        ? 1U : 0U))) : ((2U 
+						 & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
+						 ? 
+						((1U 
+						  & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
+						  ? 
+						 (VL_LTS_III(1,32,32, 
+							     vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data
+							     [2U], vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__2__KET____DOT__vx_alu__DOT__ALU_in2)
+						   ? 1U
+						   : 0U)
+						  : 
+						 (vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data
+						  [2U] 
+						  << 
+						  (0x1fU 
+						   & vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__2__KET____DOT__vx_alu__DOT__ALU_in2)))
+						 : 
+						((1U 
+						  & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
+						  ? 
+						 (vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data
+						  [2U] 
+						  - vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__2__KET____DOT__vx_alu__DOT__ALU_in2)
+						  : 
+						 (vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data
+						  [2U] 
+						  + vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__2__KET____DOT__vx_alu__DOT__ALU_in2)))));
+    }
+    // ALWAYS at VX_alu.v:48
+    if ((0x10U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))) {
+	if ((8U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))) {
+	    vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellout__genblk1__BRA__3__KET____DOT__vx_alu__out_alu_result = 0U;
+	} else {
+	    if ((4U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))) {
+		vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellout__genblk1__BRA__3__KET____DOT__vx_alu__out_alu_result 
+		    = ((2U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
+		        ? ((1U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
+			    ? ((0U == vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__3__KET____DOT__vx_alu__DOT__ALU_in2)
+			        ? vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data
+			       [3U] : VL_MODDIV_III(32, 
+						    vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data
+						    [3U], vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__3__KET____DOT__vx_alu__DOT__ALU_in2))
+			    : ((0U == vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__3__KET____DOT__vx_alu__DOT__ALU_in2)
+			        ? vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data
+			       [3U] : VL_MODDIVS_III(32, 
+						     vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data
+						     [3U], vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__3__KET____DOT__vx_alu__DOT__ALU_in2)))
+		        : ((1U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
+			    ? ((0U == vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__3__KET____DOT__vx_alu__DOT__ALU_in2)
+			        ? 0xffffffffU : VL_DIV_III(32, 
+							   vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data
+							   [3U], vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__3__KET____DOT__vx_alu__DOT__ALU_in2))
+			    : ((0U == vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__3__KET____DOT__vx_alu__DOT__ALU_in2)
+			        ? 0xffffffffU : VL_DIVS_III(32, 
+							    vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data
+							    [3U], vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__3__KET____DOT__vx_alu__DOT__ALU_in2))));
+	    } else {
+		if ((2U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))) {
+		    vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellout__genblk1__BRA__3__KET____DOT__vx_alu__out_alu_result 
+			= ((1U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
+			    ? (IData)((((QData)((IData)(
+							vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data
+							[3U])) 
+					* (QData)((IData)(vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__3__KET____DOT__vx_alu__DOT__ALU_in2))) 
+				       >> 0x20U)) : (IData)(
+							    (((((QData)((IData)(
+										VL_NEGATE_I((IData)(
+										(1U 
+										& (vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data
+										[3U] 
+										>> 0x1fU)))))) 
+								<< 0x20U) 
+							       | (QData)((IData)(
+										vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data
+										[3U]))) 
+							      * (QData)((IData)(vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__3__KET____DOT__vx_alu__DOT__ALU_in2))) 
+							     >> 0x20U)));
+		} else {
+		    if (VL_LIKELY((1U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)))) {
+			vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellout__genblk1__BRA__3__KET____DOT__vx_alu__out_alu_result 
+			    = (IData)((vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__3__KET____DOT__vx_alu__DOT__mult_signed_result 
+				       >> 0x20U));
+		    } else {
+			vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellout__genblk1__BRA__3__KET____DOT__vx_alu__out_alu_result 
+			    = (IData)(vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__3__KET____DOT__vx_alu__DOT__mult_signed_result);
+			VL_WRITEF("(%x) %x * %x = %x\n",
+				  32,vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__curr_PC,
+				  32,vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data
+				  [3U],32,vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__3__KET____DOT__vx_alu__DOT__ALU_in2,
+				  32,vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellout__genblk1__BRA__3__KET____DOT__vx_alu__out_alu_result);
+		    }
+		}
+	    }
+	}
+    } else {
+	vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellout__genblk1__BRA__3__KET____DOT__vx_alu__out_alu_result 
+	    = ((8U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
+	        ? ((4U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
+		    ? ((2U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
+		        ? vlTOPp->Vortex__DOT__csr_decode_csr_data
+		        : ((1U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
+			    ? vlTOPp->Vortex__DOT__csr_decode_csr_data
+			    : (vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__curr_PC 
+			       + (vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__upper_immed 
+				  << 0xcU)))) : ((2U 
+						  & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
+						  ? 
+						 ((1U 
+						   & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
+						   ? 
+						  (vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__upper_immed 
+						   << 0xcU)
+						   : 
+						  ((vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data
+						    [3U] 
+						    >= vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__3__KET____DOT__vx_alu__DOT__ALU_in2)
+						    ? 0U
+						    : 0xffffffffU))
+						  : 
+						 ((1U 
+						   & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
+						   ? 
+						  (vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__3__KET____DOT__vx_alu__DOT__ALU_in2 
+						   & vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data
+						   [3U])
+						   : 
+						  (vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data
+						   [3U] 
+						   | vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__3__KET____DOT__vx_alu__DOT__ALU_in2))))
+	        : ((4U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
+		    ? ((2U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
+		        ? ((1U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
+			    ? VL_SHIFTRS_III(32,32,5, 
+					     vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data
+					     [3U], 
+					     (0x1fU 
+					      & vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__3__KET____DOT__vx_alu__DOT__ALU_in2))
+			    : (vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data
+			       [3U] >> (0x1fU & vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__3__KET____DOT__vx_alu__DOT__ALU_in2)))
+		        : ((1U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
+			    ? (vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data
+			       [3U] ^ vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__3__KET____DOT__vx_alu__DOT__ALU_in2)
+			    : ((vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data
+				[3U] < vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__3__KET____DOT__vx_alu__DOT__ALU_in2)
+			        ? 1U : 0U))) : ((2U 
+						 & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
+						 ? 
+						((1U 
+						  & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
+						  ? 
+						 (VL_LTS_III(1,32,32, 
+							     vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data
+							     [3U], vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__3__KET____DOT__vx_alu__DOT__ALU_in2)
+						   ? 1U
+						   : 0U)
+						  : 
+						 (vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data
+						  [3U] 
+						  << 
+						  (0x1fU 
+						   & vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__3__KET____DOT__vx_alu__DOT__ALU_in2)))
+						 : 
+						((1U 
+						  & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
+						  ? 
+						 (vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data
+						  [3U] 
+						  - vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__3__KET____DOT__vx_alu__DOT__ALU_in2)
+						  : 
+						 (vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data
+						  [3U] 
+						  + vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__3__KET____DOT__vx_alu__DOT__ALU_in2)))));
+    }
+    // ALWAYS at VX_alu.v:48
+    if ((0x10U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))) {
+	if ((8U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))) {
+	    vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellout__genblk1__BRA__4__KET____DOT__vx_alu__out_alu_result = 0U;
+	} else {
+	    if ((4U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))) {
+		vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellout__genblk1__BRA__4__KET____DOT__vx_alu__out_alu_result 
+		    = ((2U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
+		        ? ((1U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
+			    ? ((0U == vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__4__KET____DOT__vx_alu__DOT__ALU_in2)
+			        ? vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data
+			       [4U] : VL_MODDIV_III(32, 
+						    vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data
+						    [4U], vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__4__KET____DOT__vx_alu__DOT__ALU_in2))
+			    : ((0U == vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__4__KET____DOT__vx_alu__DOT__ALU_in2)
+			        ? vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data
+			       [4U] : VL_MODDIVS_III(32, 
+						     vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data
+						     [4U], vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__4__KET____DOT__vx_alu__DOT__ALU_in2)))
+		        : ((1U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
+			    ? ((0U == vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__4__KET____DOT__vx_alu__DOT__ALU_in2)
+			        ? 0xffffffffU : VL_DIV_III(32, 
+							   vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data
+							   [4U], vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__4__KET____DOT__vx_alu__DOT__ALU_in2))
+			    : ((0U == vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__4__KET____DOT__vx_alu__DOT__ALU_in2)
+			        ? 0xffffffffU : VL_DIVS_III(32, 
+							    vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data
+							    [4U], vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__4__KET____DOT__vx_alu__DOT__ALU_in2))));
+	    } else {
+		if ((2U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))) {
+		    vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellout__genblk1__BRA__4__KET____DOT__vx_alu__out_alu_result 
+			= ((1U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
+			    ? (IData)((((QData)((IData)(
+							vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data
+							[4U])) 
+					* (QData)((IData)(vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__4__KET____DOT__vx_alu__DOT__ALU_in2))) 
+				       >> 0x20U)) : (IData)(
+							    (((((QData)((IData)(
+										VL_NEGATE_I((IData)(
+										(1U 
+										& (vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data
+										[4U] 
+										>> 0x1fU)))))) 
+								<< 0x20U) 
+							       | (QData)((IData)(
+										vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data
+										[4U]))) 
+							      * (QData)((IData)(vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__4__KET____DOT__vx_alu__DOT__ALU_in2))) 
+							     >> 0x20U)));
+		} else {
+		    if (VL_LIKELY((1U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)))) {
+			vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellout__genblk1__BRA__4__KET____DOT__vx_alu__out_alu_result 
+			    = (IData)((vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__4__KET____DOT__vx_alu__DOT__mult_signed_result 
+				       >> 0x20U));
+		    } else {
+			vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellout__genblk1__BRA__4__KET____DOT__vx_alu__out_alu_result 
+			    = (IData)(vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__4__KET____DOT__vx_alu__DOT__mult_signed_result);
+			VL_WRITEF("(%x) %x * %x = %x\n",
+				  32,vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__curr_PC,
+				  32,vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data
+				  [4U],32,vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__4__KET____DOT__vx_alu__DOT__ALU_in2,
+				  32,vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellout__genblk1__BRA__4__KET____DOT__vx_alu__out_alu_result);
+		    }
+		}
+	    }
+	}
+    } else {
+	vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellout__genblk1__BRA__4__KET____DOT__vx_alu__out_alu_result 
+	    = ((8U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
+	        ? ((4U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
+		    ? ((2U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
+		        ? vlTOPp->Vortex__DOT__csr_decode_csr_data
+		        : ((1U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
+			    ? vlTOPp->Vortex__DOT__csr_decode_csr_data
+			    : (vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__curr_PC 
+			       + (vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__upper_immed 
+				  << 0xcU)))) : ((2U 
+						  & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
+						  ? 
+						 ((1U 
+						   & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
+						   ? 
+						  (vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__upper_immed 
+						   << 0xcU)
+						   : 
+						  ((vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data
+						    [4U] 
+						    >= vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__4__KET____DOT__vx_alu__DOT__ALU_in2)
+						    ? 0U
+						    : 0xffffffffU))
+						  : 
+						 ((1U 
+						   & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
+						   ? 
+						  (vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__4__KET____DOT__vx_alu__DOT__ALU_in2 
+						   & vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data
+						   [4U])
+						   : 
+						  (vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data
+						   [4U] 
+						   | vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__4__KET____DOT__vx_alu__DOT__ALU_in2))))
+	        : ((4U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
+		    ? ((2U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
+		        ? ((1U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
+			    ? VL_SHIFTRS_III(32,32,5, 
+					     vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data
+					     [4U], 
+					     (0x1fU 
+					      & vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__4__KET____DOT__vx_alu__DOT__ALU_in2))
+			    : (vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data
+			       [4U] >> (0x1fU & vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__4__KET____DOT__vx_alu__DOT__ALU_in2)))
+		        : ((1U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
+			    ? (vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data
+			       [4U] ^ vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__4__KET____DOT__vx_alu__DOT__ALU_in2)
+			    : ((vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data
+				[4U] < vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__4__KET____DOT__vx_alu__DOT__ALU_in2)
+			        ? 1U : 0U))) : ((2U 
+						 & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
+						 ? 
+						((1U 
+						  & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
+						  ? 
+						 (VL_LTS_III(1,32,32, 
+							     vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data
+							     [4U], vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__4__KET____DOT__vx_alu__DOT__ALU_in2)
+						   ? 1U
+						   : 0U)
+						  : 
+						 (vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data
+						  [4U] 
+						  << 
+						  (0x1fU 
+						   & vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__4__KET____DOT__vx_alu__DOT__ALU_in2)))
+						 : 
+						((1U 
+						  & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
+						  ? 
+						 (vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data
+						  [4U] 
+						  - vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__4__KET____DOT__vx_alu__DOT__ALU_in2)
+						  : 
+						 (vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data
+						  [4U] 
+						  + vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__4__KET____DOT__vx_alu__DOT__ALU_in2)))));
     }
     vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_alu_result[0U] 
-	= vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellout__vx_alu_0__out_alu_result;
+	= vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellout__genblk1__BRA__0__KET____DOT__vx_alu__out_alu_result;
     vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_alu_result[1U] 
-	= vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellout__vx_alu_1__out_alu_result;
+	= vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellout__genblk1__BRA__1__KET____DOT__vx_alu__out_alu_result;
+    vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_alu_result[2U] 
+	= vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellout__genblk1__BRA__2__KET____DOT__vx_alu__out_alu_result;
+    vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_alu_result[3U] 
+	= vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellout__genblk1__BRA__3__KET____DOT__vx_alu__out_alu_result;
+    vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_alu_result[4U] 
+	= vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellout__genblk1__BRA__4__KET____DOT__vx_alu__out_alu_result;
     vlTOPp->Vortex__DOT__execute_alu_result[4U] = vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_alu_result
 	[4U];
     vlTOPp->Vortex__DOT__execute_alu_result[3U] = vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_alu_result
@@ -2007,33 +2547,75 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__3(VVortex__Syms* __restrict vlSymsp)
 		  [1U]);
     }
     // ALWAYS at VX_register_file.v:43
-    vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__vx_register_file_1__out_src2_data 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT__vx_register_file_1__DOT__registers
+    vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__gen_code_label__BRA__4__KET____DOT__vx_register_file__out_src2_data 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__gen_code_label__BRA__4__KET____DOT__vx_register_file__DOT__registers
 	[(0x1fU & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction 
 		   >> 0x14U))];
     // ALWAYS at VX_register_file.v:43
-    vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__vx_register_file_0__out_src2_data 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT__vx_register_file_0__DOT__registers
+    vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__gen_code_label__BRA__3__KET____DOT__vx_register_file__out_src2_data 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__gen_code_label__BRA__3__KET____DOT__vx_register_file__DOT__registers
 	[(0x1fU & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction 
 		   >> 0x14U))];
     // ALWAYS at VX_register_file.v:43
-    vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__vx_register_file_1__out_src1_data 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT__vx_register_file_1__DOT__registers
+    vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__gen_code_label__BRA__2__KET____DOT__vx_register_file__out_src2_data 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__gen_code_label__BRA__2__KET____DOT__vx_register_file__DOT__registers
+	[(0x1fU & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction 
+		   >> 0x14U))];
+    // ALWAYS at VX_register_file.v:43
+    vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__gen_code_label__BRA__1__KET____DOT__vx_register_file__out_src2_data 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file__DOT__registers
+	[(0x1fU & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction 
+		   >> 0x14U))];
+    // ALWAYS at VX_register_file.v:43
+    vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__gen_code_label__BRA__0__KET____DOT__vx_register_file__out_src2_data 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__gen_code_label__BRA__0__KET____DOT__vx_register_file__DOT__registers
+	[(0x1fU & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction 
+		   >> 0x14U))];
+    // ALWAYS at VX_register_file.v:43
+    vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__gen_code_label__BRA__4__KET____DOT__vx_register_file__out_src1_data 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__gen_code_label__BRA__4__KET____DOT__vx_register_file__DOT__registers
 	[(0x1fU & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction 
 		   >> 0xfU))];
     // ALWAYS at VX_register_file.v:43
-    vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__vx_register_file_0__out_src1_data 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT__vx_register_file_0__DOT__registers
+    vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__gen_code_label__BRA__3__KET____DOT__vx_register_file__out_src1_data 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__gen_code_label__BRA__3__KET____DOT__vx_register_file__DOT__registers
 	[(0x1fU & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction 
 		   >> 0xfU))];
+    // ALWAYS at VX_register_file.v:43
+    vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__gen_code_label__BRA__2__KET____DOT__vx_register_file__out_src1_data 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__gen_code_label__BRA__2__KET____DOT__vx_register_file__DOT__registers
+	[(0x1fU & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction 
+		   >> 0xfU))];
+    // ALWAYS at VX_register_file.v:43
+    vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__gen_code_label__BRA__1__KET____DOT__vx_register_file__out_src1_data 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file__DOT__registers
+	[(0x1fU & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction 
+		   >> 0xfU))];
+    // ALWAYS at VX_register_file.v:43
+    vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__gen_code_label__BRA__0__KET____DOT__vx_register_file__out_src1_data 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__gen_code_label__BRA__0__KET____DOT__vx_register_file__DOT__registers
+	[(0x1fU & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction 
+		   >> 0xfU))];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__rd2_register[4U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__gen_code_label__BRA__4__KET____DOT__vx_register_file__out_src2_data;
+    vlTOPp->Vortex__DOT__vx_decode__DOT__rd2_register[3U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__gen_code_label__BRA__3__KET____DOT__vx_register_file__out_src2_data;
+    vlTOPp->Vortex__DOT__vx_decode__DOT__rd2_register[2U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__gen_code_label__BRA__2__KET____DOT__vx_register_file__out_src2_data;
     vlTOPp->Vortex__DOT__vx_decode__DOT__rd2_register[1U] 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__vx_register_file_1__out_src2_data;
+	= vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__gen_code_label__BRA__1__KET____DOT__vx_register_file__out_src2_data;
     vlTOPp->Vortex__DOT__vx_decode__DOT__rd2_register[0U] 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__vx_register_file_0__out_src2_data;
+	= vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__gen_code_label__BRA__0__KET____DOT__vx_register_file__out_src2_data;
+    vlTOPp->Vortex__DOT__vx_decode__DOT__rd1_register[4U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__gen_code_label__BRA__4__KET____DOT__vx_register_file__out_src1_data;
+    vlTOPp->Vortex__DOT__vx_decode__DOT__rd1_register[3U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__gen_code_label__BRA__3__KET____DOT__vx_register_file__out_src1_data;
+    vlTOPp->Vortex__DOT__vx_decode__DOT__rd1_register[2U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__gen_code_label__BRA__2__KET____DOT__vx_register_file__out_src1_data;
     vlTOPp->Vortex__DOT__vx_decode__DOT__rd1_register[1U] 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__vx_register_file_1__out_src1_data;
+	= vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__gen_code_label__BRA__1__KET____DOT__vx_register_file__out_src1_data;
     vlTOPp->Vortex__DOT__vx_decode__DOT__rd1_register[0U] 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__vx_register_file_0__out_src1_data;
+	= vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__gen_code_label__BRA__0__KET____DOT__vx_register_file__out_src1_data;
 }
 
 VL_INLINE_OPT void VVortex::_combo__TOP__4(VVortex__Syms* __restrict vlSymsp) {
@@ -2142,13 +2724,25 @@ void VVortex::_settle__TOP__5(VVortex__Syms* __restrict vlSymsp) {
 	= vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__valid
 	[0U];
     vlTOPp->Vortex__DOT__vx_decode__DOT__rd2_register[0U] 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__vx_register_file_0__out_src2_data;
+	= vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__gen_code_label__BRA__0__KET____DOT__vx_register_file__out_src2_data;
     vlTOPp->Vortex__DOT__vx_decode__DOT__rd2_register[1U] 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__vx_register_file_1__out_src2_data;
+	= vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__gen_code_label__BRA__1__KET____DOT__vx_register_file__out_src2_data;
+    vlTOPp->Vortex__DOT__vx_decode__DOT__rd2_register[2U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__gen_code_label__BRA__2__KET____DOT__vx_register_file__out_src2_data;
+    vlTOPp->Vortex__DOT__vx_decode__DOT__rd2_register[3U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__gen_code_label__BRA__3__KET____DOT__vx_register_file__out_src2_data;
+    vlTOPp->Vortex__DOT__vx_decode__DOT__rd2_register[4U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__gen_code_label__BRA__4__KET____DOT__vx_register_file__out_src2_data;
     vlTOPp->Vortex__DOT__vx_decode__DOT__rd1_register[0U] 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__vx_register_file_0__out_src1_data;
+	= vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__gen_code_label__BRA__0__KET____DOT__vx_register_file__out_src1_data;
     vlTOPp->Vortex__DOT__vx_decode__DOT__rd1_register[1U] 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__vx_register_file_1__out_src1_data;
+	= vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__gen_code_label__BRA__1__KET____DOT__vx_register_file__out_src1_data;
+    vlTOPp->Vortex__DOT__vx_decode__DOT__rd1_register[2U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__gen_code_label__BRA__2__KET____DOT__vx_register_file__out_src1_data;
+    vlTOPp->Vortex__DOT__vx_decode__DOT__rd1_register[3U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__gen_code_label__BRA__3__KET____DOT__vx_register_file__out_src1_data;
+    vlTOPp->Vortex__DOT__vx_decode__DOT__rd1_register[4U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__gen_code_label__BRA__4__KET____DOT__vx_register_file__out_src1_data;
     vlTOPp->Vortex__DOT____Vcellout__vx_f_d_reg__out_valid[4U] 
 	= vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__valid
 	[4U];
@@ -2212,7 +2806,7 @@ void VVortex::_settle__TOP__5(VVortex__Syms* __restrict vlSymsp) {
 						  (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction 
 						   >> 0x14U)
 						   : 0x55U));
-    // ALWAYS at VX_decode.v:392
+    // ALWAYS at VX_decode.v:367
     vlTOPp->__Vtableidx1 = (7U & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction 
 				  >> 0xcU));
     vlTOPp->Vortex__DOT__vx_decode__DOT__mul_alu = 
@@ -2238,7 +2832,7 @@ void VVortex::_settle__TOP__5(VVortex__Syms* __restrict vlSymsp) {
 						      (7U 
 						       & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction 
 							  >> 0xcU))));
-    // ALWAYS at VX_decode.v:342
+    // ALWAYS at VX_decode.v:317
     vlTOPp->Vortex__DOT__decode_branch_type = ((0x63U 
 						== 
 						(0x7fU 
@@ -2331,7 +2925,7 @@ void VVortex::_settle__TOP__5(VVortex__Syms* __restrict vlSymsp) {
 	[1U];
     vlTOPp->Vortex__DOT__m_w_mem_result[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_m_w_reg__out_mem_result
 	[0U];
-    // ALWAYS at VX_decode.v:331
+    // ALWAYS at VX_decode.v:306
     vlTOPp->Vortex__DOT__decode_itype_immed = ((0x40U 
 						& vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)
 					        ? (
@@ -2826,7 +3420,7 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__7(VVortex__Syms* __restrict vlSymsp)
 		    ? 0U : vlTOPp->fe_instruction);
 	}
     }
-    // ALWAYS at VX_fetch.v:113
+    // ALWAYS at VX_fetch.v:112
     vlTOPp->Vortex__DOT__vx_fetch__DOT__temp_PC = (
 						   ((IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__jal) 
 						    & (~ (IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__delay_reg)))
@@ -2855,7 +3449,7 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__7(VVortex__Syms* __restrict vlSymsp)
 						  (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction 
 						   >> 0x14U)
 						   : 0x55U));
-    // ALWAYS at VX_decode.v:392
+    // ALWAYS at VX_decode.v:367
     vlTOPp->__Vtableidx1 = (7U & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction 
 				  >> 0xcU));
     vlTOPp->Vortex__DOT__vx_decode__DOT__mul_alu = 
@@ -2881,7 +3475,7 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__7(VVortex__Syms* __restrict vlSymsp)
 						      (7U 
 						       & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction 
 							  >> 0xcU))));
-    // ALWAYS at VX_decode.v:342
+    // ALWAYS at VX_decode.v:317
     vlTOPp->Vortex__DOT__decode_branch_type = ((0x63U 
 						== 
 						(0x7fU 
@@ -2922,7 +3516,7 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__7(VVortex__Syms* __restrict vlSymsp)
 		       >> 0xfU)) == (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__rd)) 
 	    & (0U != (0x1fU & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction 
 			       >> 0xfU)))) & (0U != (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__wb)));
-    // ALWAYS at VX_decode.v:331
+    // ALWAYS at VX_decode.v:306
     vlTOPp->Vortex__DOT__decode_itype_immed = ((0x40U 
 						& vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)
 					        ? (
@@ -3244,7 +3838,7 @@ void VVortex::_settle__TOP__8(VVortex__Syms* __restrict vlSymsp) {
     VL_DEBUG_IF(VL_DBG_MSGF("+    VVortex::_settle__TOP__8\n"); );
     VVortex* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
     // Body
-    // ALWAYS at VX_fetch.v:82
+    // ALWAYS at VX_fetch.v:81
     vlTOPp->Vortex__DOT__vx_fetch__DOT__PC_to_use = 
 	((IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__delay_reg)
 	  ? vlTOPp->Vortex__DOT__vx_fetch__DOT__old
@@ -3810,16 +4404,31 @@ void VVortex::_settle__TOP__8(VVortex__Syms* __restrict vlSymsp) {
     vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_b_reg_data[0U] 
 	= vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_b_reg_data
 	[0U];
-    vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_0__DOT__ALU_in2 
+    vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__0__KET____DOT__vx_alu__DOT__ALU_in2 
 	= ((IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__rs2_src)
 	    ? vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__itype_immed
 	    : vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_b_reg_data
 	   [0U]);
-    vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_1__DOT__ALU_in2 
+    vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__1__KET____DOT__vx_alu__DOT__ALU_in2 
 	= ((IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__rs2_src)
 	    ? vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__itype_immed
 	    : vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_b_reg_data
 	   [1U]);
+    vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__2__KET____DOT__vx_alu__DOT__ALU_in2 
+	= ((IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__rs2_src)
+	    ? vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__itype_immed
+	    : vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_b_reg_data
+	   [2U]);
+    vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__3__KET____DOT__vx_alu__DOT__ALU_in2 
+	= ((IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__rs2_src)
+	    ? vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__itype_immed
+	    : vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_b_reg_data
+	   [3U]);
+    vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__4__KET____DOT__vx_alu__DOT__ALU_in2 
+	= ((IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__rs2_src)
+	    ? vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__itype_immed
+	    : vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_b_reg_data
+	   [4U]);
     vlTOPp->Vortex__DOT__forwarding_src2_fwd = (((IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src2_exe_fwd) 
 						 | (IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src2_mem_fwd)) 
 						| (IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src2_wb_fwd));
@@ -3874,7 +4483,7 @@ void VVortex::_settle__TOP__8(VVortex__Syms* __restrict vlSymsp) {
 	[1U];
     vlTOPp->Vortex__DOT__memory_valid[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_valid
 	[0U];
-    // ALWAYS at VX_fetch.v:113
+    // ALWAYS at VX_fetch.v:112
     vlTOPp->Vortex__DOT__vx_fetch__DOT__temp_PC = (
 						   ((IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__jal) 
 						    & (~ (IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__delay_reg)))
@@ -3924,16 +4533,31 @@ void VVortex::_settle__TOP__8(VVortex__Syms* __restrict vlSymsp) {
 	[1U];
     vlTOPp->Vortex__DOT__execute_b_reg_data[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_b_reg_data
 	[0U];
-    vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_0__DOT__mult_signed_result 
+    vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__0__KET____DOT__vx_alu__DOT__mult_signed_result 
 	= VL_MULS_QQQ(64,64,64, VL_EXTENDS_QI(64,32, 
 					      vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data
 					      [0U]), 
-		      VL_EXTENDS_QI(64,32, vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_0__DOT__ALU_in2));
-    vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_1__DOT__mult_signed_result 
+		      VL_EXTENDS_QI(64,32, vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__0__KET____DOT__vx_alu__DOT__ALU_in2));
+    vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__1__KET____DOT__vx_alu__DOT__mult_signed_result 
 	= VL_MULS_QQQ(64,64,64, VL_EXTENDS_QI(64,32, 
 					      vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data
 					      [1U]), 
-		      VL_EXTENDS_QI(64,32, vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_1__DOT__ALU_in2));
+		      VL_EXTENDS_QI(64,32, vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__1__KET____DOT__vx_alu__DOT__ALU_in2));
+    vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__2__KET____DOT__vx_alu__DOT__mult_signed_result 
+	= VL_MULS_QQQ(64,64,64, VL_EXTENDS_QI(64,32, 
+					      vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data
+					      [2U]), 
+		      VL_EXTENDS_QI(64,32, vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__2__KET____DOT__vx_alu__DOT__ALU_in2));
+    vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__3__KET____DOT__vx_alu__DOT__mult_signed_result 
+	= VL_MULS_QQQ(64,64,64, VL_EXTENDS_QI(64,32, 
+					      vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data
+					      [3U]), 
+		      VL_EXTENDS_QI(64,32, vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__3__KET____DOT__vx_alu__DOT__ALU_in2));
+    vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__4__KET____DOT__vx_alu__DOT__mult_signed_result 
+	= VL_MULS_QQQ(64,64,64, VL_EXTENDS_QI(64,32, 
+					      vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data
+					      [4U]), 
+		      VL_EXTENDS_QI(64,32, vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__4__KET____DOT__vx_alu__DOT__ALU_in2));
     vlTOPp->Vortex__DOT____Vcellout__vx_fetch__out_valid[0U] 
 	= (1U & ((~ (IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__stall)) 
 		 & (IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__valid)));
@@ -4007,39 +4631,39 @@ void VVortex::_settle__TOP__8(VVortex__Syms* __restrict vlSymsp) {
     // ALWAYS at VX_alu.v:48
     if ((0x10U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))) {
 	if ((8U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))) {
-	    vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellout__vx_alu_0__out_alu_result = 0U;
+	    vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellout__genblk1__BRA__0__KET____DOT__vx_alu__out_alu_result = 0U;
 	} else {
 	    if ((4U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))) {
-		vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellout__vx_alu_0__out_alu_result 
+		vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellout__genblk1__BRA__0__KET____DOT__vx_alu__out_alu_result 
 		    = ((2U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
 		        ? ((1U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
-			    ? ((0U == vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_0__DOT__ALU_in2)
+			    ? ((0U == vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__0__KET____DOT__vx_alu__DOT__ALU_in2)
 			        ? vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data
 			       [0U] : VL_MODDIV_III(32, 
 						    vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data
-						    [0U], vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_0__DOT__ALU_in2))
-			    : ((0U == vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_0__DOT__ALU_in2)
+						    [0U], vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__0__KET____DOT__vx_alu__DOT__ALU_in2))
+			    : ((0U == vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__0__KET____DOT__vx_alu__DOT__ALU_in2)
 			        ? vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data
 			       [0U] : VL_MODDIVS_III(32, 
 						     vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data
-						     [0U], vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_0__DOT__ALU_in2)))
+						     [0U], vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__0__KET____DOT__vx_alu__DOT__ALU_in2)))
 		        : ((1U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
-			    ? ((0U == vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_0__DOT__ALU_in2)
+			    ? ((0U == vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__0__KET____DOT__vx_alu__DOT__ALU_in2)
 			        ? 0xffffffffU : VL_DIV_III(32, 
 							   vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data
-							   [0U], vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_0__DOT__ALU_in2))
-			    : ((0U == vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_0__DOT__ALU_in2)
+							   [0U], vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__0__KET____DOT__vx_alu__DOT__ALU_in2))
+			    : ((0U == vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__0__KET____DOT__vx_alu__DOT__ALU_in2)
 			        ? 0xffffffffU : VL_DIVS_III(32, 
 							    vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data
-							    [0U], vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_0__DOT__ALU_in2))));
+							    [0U], vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__0__KET____DOT__vx_alu__DOT__ALU_in2))));
 	    } else {
 		if ((2U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))) {
-		    vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellout__vx_alu_0__out_alu_result 
+		    vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellout__genblk1__BRA__0__KET____DOT__vx_alu__out_alu_result 
 			= ((1U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
 			    ? (IData)((((QData)((IData)(
 							vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data
 							[0U])) 
-					* (QData)((IData)(vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_0__DOT__ALU_in2))) 
+					* (QData)((IData)(vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__0__KET____DOT__vx_alu__DOT__ALU_in2))) 
 				       >> 0x20U)) : (IData)(
 							    (((((QData)((IData)(
 										VL_NEGATE_I((IData)(
@@ -4051,27 +4675,27 @@ void VVortex::_settle__TOP__8(VVortex__Syms* __restrict vlSymsp) {
 							       | (QData)((IData)(
 										vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data
 										[0U]))) 
-							      * (QData)((IData)(vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_0__DOT__ALU_in2))) 
+							      * (QData)((IData)(vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__0__KET____DOT__vx_alu__DOT__ALU_in2))) 
 							     >> 0x20U)));
 		} else {
 		    if (VL_LIKELY((1U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)))) {
-			vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellout__vx_alu_0__out_alu_result 
-			    = (IData)((vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_0__DOT__mult_signed_result 
+			vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellout__genblk1__BRA__0__KET____DOT__vx_alu__out_alu_result 
+			    = (IData)((vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__0__KET____DOT__vx_alu__DOT__mult_signed_result 
 				       >> 0x20U));
 		    } else {
-			vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellout__vx_alu_0__out_alu_result 
-			    = (IData)(vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_0__DOT__mult_signed_result);
+			vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellout__genblk1__BRA__0__KET____DOT__vx_alu__out_alu_result 
+			    = (IData)(vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__0__KET____DOT__vx_alu__DOT__mult_signed_result);
 			VL_WRITEF("(%x) %x * %x = %x\n",
 				  32,vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__curr_PC,
 				  32,vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data
-				  [0U],32,vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_0__DOT__ALU_in2,
-				  32,vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellout__vx_alu_0__out_alu_result);
+				  [0U],32,vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__0__KET____DOT__vx_alu__DOT__ALU_in2,
+				  32,vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellout__genblk1__BRA__0__KET____DOT__vx_alu__out_alu_result);
 		    }
 		}
 	    }
 	}
     } else {
-	vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellout__vx_alu_0__out_alu_result 
+	vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellout__genblk1__BRA__0__KET____DOT__vx_alu__out_alu_result 
 	    = ((8U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
 	        ? ((4U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
 		    ? ((2U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
@@ -4091,20 +4715,20 @@ void VVortex::_settle__TOP__8(VVortex__Syms* __restrict vlSymsp) {
 						   : 
 						  ((vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data
 						    [0U] 
-						    >= vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_0__DOT__ALU_in2)
+						    >= vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__0__KET____DOT__vx_alu__DOT__ALU_in2)
 						    ? 0U
 						    : 0xffffffffU))
 						  : 
 						 ((1U 
 						   & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
 						   ? 
-						  (vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_0__DOT__ALU_in2 
+						  (vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__0__KET____DOT__vx_alu__DOT__ALU_in2 
 						   & vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data
 						   [0U])
 						   : 
 						  (vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data
 						   [0U] 
-						   | vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_0__DOT__ALU_in2))))
+						   | vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__0__KET____DOT__vx_alu__DOT__ALU_in2))))
 	        : ((4U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
 		    ? ((2U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
 		        ? ((1U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
@@ -4112,14 +4736,14 @@ void VVortex::_settle__TOP__8(VVortex__Syms* __restrict vlSymsp) {
 					     vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data
 					     [0U], 
 					     (0x1fU 
-					      & vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_0__DOT__ALU_in2))
+					      & vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__0__KET____DOT__vx_alu__DOT__ALU_in2))
 			    : (vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data
-			       [0U] >> (0x1fU & vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_0__DOT__ALU_in2)))
+			       [0U] >> (0x1fU & vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__0__KET____DOT__vx_alu__DOT__ALU_in2)))
 		        : ((1U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
 			    ? (vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data
-			       [0U] ^ vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_0__DOT__ALU_in2)
+			       [0U] ^ vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__0__KET____DOT__vx_alu__DOT__ALU_in2)
 			    : ((vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data
-				[0U] < vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_0__DOT__ALU_in2)
+				[0U] < vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__0__KET____DOT__vx_alu__DOT__ALU_in2)
 			        ? 1U : 0U))) : ((2U 
 						 & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
 						 ? 
@@ -4128,7 +4752,7 @@ void VVortex::_settle__TOP__8(VVortex__Syms* __restrict vlSymsp) {
 						  ? 
 						 (VL_LTS_III(1,32,32, 
 							     vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data
-							     [0U], vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_0__DOT__ALU_in2)
+							     [0U], vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__0__KET____DOT__vx_alu__DOT__ALU_in2)
 						   ? 1U
 						   : 0U)
 						  : 
@@ -4136,55 +4760,55 @@ void VVortex::_settle__TOP__8(VVortex__Syms* __restrict vlSymsp) {
 						  [0U] 
 						  << 
 						  (0x1fU 
-						   & vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_0__DOT__ALU_in2)))
+						   & vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__0__KET____DOT__vx_alu__DOT__ALU_in2)))
 						 : 
 						((1U 
 						  & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
 						  ? 
 						 (vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data
 						  [0U] 
-						  - vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_0__DOT__ALU_in2)
+						  - vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__0__KET____DOT__vx_alu__DOT__ALU_in2)
 						  : 
 						 (vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data
 						  [0U] 
-						  + vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_0__DOT__ALU_in2)))));
+						  + vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__0__KET____DOT__vx_alu__DOT__ALU_in2)))));
     }
     // ALWAYS at VX_alu.v:48
     if ((0x10U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))) {
 	if ((8U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))) {
-	    vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellout__vx_alu_1__out_alu_result = 0U;
+	    vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellout__genblk1__BRA__1__KET____DOT__vx_alu__out_alu_result = 0U;
 	} else {
 	    if ((4U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))) {
-		vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellout__vx_alu_1__out_alu_result 
+		vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellout__genblk1__BRA__1__KET____DOT__vx_alu__out_alu_result 
 		    = ((2U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
 		        ? ((1U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
-			    ? ((0U == vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_1__DOT__ALU_in2)
+			    ? ((0U == vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__1__KET____DOT__vx_alu__DOT__ALU_in2)
 			        ? vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data
 			       [1U] : VL_MODDIV_III(32, 
 						    vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data
-						    [1U], vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_1__DOT__ALU_in2))
-			    : ((0U == vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_1__DOT__ALU_in2)
+						    [1U], vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__1__KET____DOT__vx_alu__DOT__ALU_in2))
+			    : ((0U == vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__1__KET____DOT__vx_alu__DOT__ALU_in2)
 			        ? vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data
 			       [1U] : VL_MODDIVS_III(32, 
 						     vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data
-						     [1U], vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_1__DOT__ALU_in2)))
+						     [1U], vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__1__KET____DOT__vx_alu__DOT__ALU_in2)))
 		        : ((1U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
-			    ? ((0U == vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_1__DOT__ALU_in2)
+			    ? ((0U == vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__1__KET____DOT__vx_alu__DOT__ALU_in2)
 			        ? 0xffffffffU : VL_DIV_III(32, 
 							   vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data
-							   [1U], vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_1__DOT__ALU_in2))
-			    : ((0U == vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_1__DOT__ALU_in2)
+							   [1U], vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__1__KET____DOT__vx_alu__DOT__ALU_in2))
+			    : ((0U == vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__1__KET____DOT__vx_alu__DOT__ALU_in2)
 			        ? 0xffffffffU : VL_DIVS_III(32, 
 							    vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data
-							    [1U], vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_1__DOT__ALU_in2))));
+							    [1U], vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__1__KET____DOT__vx_alu__DOT__ALU_in2))));
 	    } else {
 		if ((2U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))) {
-		    vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellout__vx_alu_1__out_alu_result 
+		    vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellout__genblk1__BRA__1__KET____DOT__vx_alu__out_alu_result 
 			= ((1U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
 			    ? (IData)((((QData)((IData)(
 							vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data
 							[1U])) 
-					* (QData)((IData)(vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_1__DOT__ALU_in2))) 
+					* (QData)((IData)(vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__1__KET____DOT__vx_alu__DOT__ALU_in2))) 
 				       >> 0x20U)) : (IData)(
 							    (((((QData)((IData)(
 										VL_NEGATE_I((IData)(
@@ -4196,27 +4820,27 @@ void VVortex::_settle__TOP__8(VVortex__Syms* __restrict vlSymsp) {
 							       | (QData)((IData)(
 										vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data
 										[1U]))) 
-							      * (QData)((IData)(vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_1__DOT__ALU_in2))) 
+							      * (QData)((IData)(vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__1__KET____DOT__vx_alu__DOT__ALU_in2))) 
 							     >> 0x20U)));
 		} else {
 		    if (VL_LIKELY((1U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)))) {
-			vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellout__vx_alu_1__out_alu_result 
-			    = (IData)((vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_1__DOT__mult_signed_result 
+			vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellout__genblk1__BRA__1__KET____DOT__vx_alu__out_alu_result 
+			    = (IData)((vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__1__KET____DOT__vx_alu__DOT__mult_signed_result 
 				       >> 0x20U));
 		    } else {
-			vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellout__vx_alu_1__out_alu_result 
-			    = (IData)(vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_1__DOT__mult_signed_result);
+			vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellout__genblk1__BRA__1__KET____DOT__vx_alu__out_alu_result 
+			    = (IData)(vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__1__KET____DOT__vx_alu__DOT__mult_signed_result);
 			VL_WRITEF("(%x) %x * %x = %x\n",
 				  32,vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__curr_PC,
 				  32,vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data
-				  [1U],32,vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_1__DOT__ALU_in2,
-				  32,vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellout__vx_alu_1__out_alu_result);
+				  [1U],32,vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__1__KET____DOT__vx_alu__DOT__ALU_in2,
+				  32,vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellout__genblk1__BRA__1__KET____DOT__vx_alu__out_alu_result);
 		    }
 		}
 	    }
 	}
     } else {
-	vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellout__vx_alu_1__out_alu_result 
+	vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellout__genblk1__BRA__1__KET____DOT__vx_alu__out_alu_result 
 	    = ((8U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
 	        ? ((4U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
 		    ? ((2U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
@@ -4236,20 +4860,20 @@ void VVortex::_settle__TOP__8(VVortex__Syms* __restrict vlSymsp) {
 						   : 
 						  ((vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data
 						    [1U] 
-						    >= vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_1__DOT__ALU_in2)
+						    >= vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__1__KET____DOT__vx_alu__DOT__ALU_in2)
 						    ? 0U
 						    : 0xffffffffU))
 						  : 
 						 ((1U 
 						   & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
 						   ? 
-						  (vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_1__DOT__ALU_in2 
+						  (vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__1__KET____DOT__vx_alu__DOT__ALU_in2 
 						   & vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data
 						   [1U])
 						   : 
 						  (vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data
 						   [1U] 
-						   | vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_1__DOT__ALU_in2))))
+						   | vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__1__KET____DOT__vx_alu__DOT__ALU_in2))))
 	        : ((4U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
 		    ? ((2U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
 		        ? ((1U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
@@ -4257,14 +4881,14 @@ void VVortex::_settle__TOP__8(VVortex__Syms* __restrict vlSymsp) {
 					     vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data
 					     [1U], 
 					     (0x1fU 
-					      & vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_1__DOT__ALU_in2))
+					      & vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__1__KET____DOT__vx_alu__DOT__ALU_in2))
 			    : (vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data
-			       [1U] >> (0x1fU & vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_1__DOT__ALU_in2)))
+			       [1U] >> (0x1fU & vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__1__KET____DOT__vx_alu__DOT__ALU_in2)))
 		        : ((1U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
 			    ? (vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data
-			       [1U] ^ vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_1__DOT__ALU_in2)
+			       [1U] ^ vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__1__KET____DOT__vx_alu__DOT__ALU_in2)
 			    : ((vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data
-				[1U] < vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_1__DOT__ALU_in2)
+				[1U] < vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__1__KET____DOT__vx_alu__DOT__ALU_in2)
 			        ? 1U : 0U))) : ((2U 
 						 & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
 						 ? 
@@ -4273,7 +4897,7 @@ void VVortex::_settle__TOP__8(VVortex__Syms* __restrict vlSymsp) {
 						  ? 
 						 (VL_LTS_III(1,32,32, 
 							     vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data
-							     [1U], vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_1__DOT__ALU_in2)
+							     [1U], vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__1__KET____DOT__vx_alu__DOT__ALU_in2)
 						   ? 1U
 						   : 0U)
 						  : 
@@ -4281,18 +4905,453 @@ void VVortex::_settle__TOP__8(VVortex__Syms* __restrict vlSymsp) {
 						  [1U] 
 						  << 
 						  (0x1fU 
-						   & vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_1__DOT__ALU_in2)))
+						   & vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__1__KET____DOT__vx_alu__DOT__ALU_in2)))
 						 : 
 						((1U 
 						  & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
 						  ? 
 						 (vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data
 						  [1U] 
-						  - vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_1__DOT__ALU_in2)
+						  - vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__1__KET____DOT__vx_alu__DOT__ALU_in2)
 						  : 
 						 (vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data
 						  [1U] 
-						  + vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_1__DOT__ALU_in2)))));
+						  + vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__1__KET____DOT__vx_alu__DOT__ALU_in2)))));
+    }
+    // ALWAYS at VX_alu.v:48
+    if ((0x10U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))) {
+	if ((8U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))) {
+	    vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellout__genblk1__BRA__2__KET____DOT__vx_alu__out_alu_result = 0U;
+	} else {
+	    if ((4U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))) {
+		vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellout__genblk1__BRA__2__KET____DOT__vx_alu__out_alu_result 
+		    = ((2U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
+		        ? ((1U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
+			    ? ((0U == vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__2__KET____DOT__vx_alu__DOT__ALU_in2)
+			        ? vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data
+			       [2U] : VL_MODDIV_III(32, 
+						    vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data
+						    [2U], vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__2__KET____DOT__vx_alu__DOT__ALU_in2))
+			    : ((0U == vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__2__KET____DOT__vx_alu__DOT__ALU_in2)
+			        ? vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data
+			       [2U] : VL_MODDIVS_III(32, 
+						     vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data
+						     [2U], vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__2__KET____DOT__vx_alu__DOT__ALU_in2)))
+		        : ((1U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
+			    ? ((0U == vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__2__KET____DOT__vx_alu__DOT__ALU_in2)
+			        ? 0xffffffffU : VL_DIV_III(32, 
+							   vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data
+							   [2U], vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__2__KET____DOT__vx_alu__DOT__ALU_in2))
+			    : ((0U == vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__2__KET____DOT__vx_alu__DOT__ALU_in2)
+			        ? 0xffffffffU : VL_DIVS_III(32, 
+							    vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data
+							    [2U], vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__2__KET____DOT__vx_alu__DOT__ALU_in2))));
+	    } else {
+		if ((2U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))) {
+		    vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellout__genblk1__BRA__2__KET____DOT__vx_alu__out_alu_result 
+			= ((1U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
+			    ? (IData)((((QData)((IData)(
+							vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data
+							[2U])) 
+					* (QData)((IData)(vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__2__KET____DOT__vx_alu__DOT__ALU_in2))) 
+				       >> 0x20U)) : (IData)(
+							    (((((QData)((IData)(
+										VL_NEGATE_I((IData)(
+										(1U 
+										& (vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data
+										[2U] 
+										>> 0x1fU)))))) 
+								<< 0x20U) 
+							       | (QData)((IData)(
+										vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data
+										[2U]))) 
+							      * (QData)((IData)(vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__2__KET____DOT__vx_alu__DOT__ALU_in2))) 
+							     >> 0x20U)));
+		} else {
+		    if (VL_LIKELY((1U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)))) {
+			vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellout__genblk1__BRA__2__KET____DOT__vx_alu__out_alu_result 
+			    = (IData)((vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__2__KET____DOT__vx_alu__DOT__mult_signed_result 
+				       >> 0x20U));
+		    } else {
+			vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellout__genblk1__BRA__2__KET____DOT__vx_alu__out_alu_result 
+			    = (IData)(vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__2__KET____DOT__vx_alu__DOT__mult_signed_result);
+			VL_WRITEF("(%x) %x * %x = %x\n",
+				  32,vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__curr_PC,
+				  32,vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data
+				  [2U],32,vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__2__KET____DOT__vx_alu__DOT__ALU_in2,
+				  32,vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellout__genblk1__BRA__2__KET____DOT__vx_alu__out_alu_result);
+		    }
+		}
+	    }
+	}
+    } else {
+	vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellout__genblk1__BRA__2__KET____DOT__vx_alu__out_alu_result 
+	    = ((8U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
+	        ? ((4U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
+		    ? ((2U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
+		        ? vlTOPp->Vortex__DOT__csr_decode_csr_data
+		        : ((1U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
+			    ? vlTOPp->Vortex__DOT__csr_decode_csr_data
+			    : (vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__curr_PC 
+			       + (vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__upper_immed 
+				  << 0xcU)))) : ((2U 
+						  & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
+						  ? 
+						 ((1U 
+						   & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
+						   ? 
+						  (vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__upper_immed 
+						   << 0xcU)
+						   : 
+						  ((vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data
+						    [2U] 
+						    >= vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__2__KET____DOT__vx_alu__DOT__ALU_in2)
+						    ? 0U
+						    : 0xffffffffU))
+						  : 
+						 ((1U 
+						   & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
+						   ? 
+						  (vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__2__KET____DOT__vx_alu__DOT__ALU_in2 
+						   & vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data
+						   [2U])
+						   : 
+						  (vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data
+						   [2U] 
+						   | vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__2__KET____DOT__vx_alu__DOT__ALU_in2))))
+	        : ((4U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
+		    ? ((2U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
+		        ? ((1U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
+			    ? VL_SHIFTRS_III(32,32,5, 
+					     vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data
+					     [2U], 
+					     (0x1fU 
+					      & vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__2__KET____DOT__vx_alu__DOT__ALU_in2))
+			    : (vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data
+			       [2U] >> (0x1fU & vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__2__KET____DOT__vx_alu__DOT__ALU_in2)))
+		        : ((1U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
+			    ? (vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data
+			       [2U] ^ vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__2__KET____DOT__vx_alu__DOT__ALU_in2)
+			    : ((vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data
+				[2U] < vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__2__KET____DOT__vx_alu__DOT__ALU_in2)
+			        ? 1U : 0U))) : ((2U 
+						 & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
+						 ? 
+						((1U 
+						  & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
+						  ? 
+						 (VL_LTS_III(1,32,32, 
+							     vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data
+							     [2U], vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__2__KET____DOT__vx_alu__DOT__ALU_in2)
+						   ? 1U
+						   : 0U)
+						  : 
+						 (vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data
+						  [2U] 
+						  << 
+						  (0x1fU 
+						   & vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__2__KET____DOT__vx_alu__DOT__ALU_in2)))
+						 : 
+						((1U 
+						  & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
+						  ? 
+						 (vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data
+						  [2U] 
+						  - vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__2__KET____DOT__vx_alu__DOT__ALU_in2)
+						  : 
+						 (vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data
+						  [2U] 
+						  + vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__2__KET____DOT__vx_alu__DOT__ALU_in2)))));
+    }
+    // ALWAYS at VX_alu.v:48
+    if ((0x10U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))) {
+	if ((8U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))) {
+	    vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellout__genblk1__BRA__3__KET____DOT__vx_alu__out_alu_result = 0U;
+	} else {
+	    if ((4U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))) {
+		vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellout__genblk1__BRA__3__KET____DOT__vx_alu__out_alu_result 
+		    = ((2U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
+		        ? ((1U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
+			    ? ((0U == vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__3__KET____DOT__vx_alu__DOT__ALU_in2)
+			        ? vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data
+			       [3U] : VL_MODDIV_III(32, 
+						    vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data
+						    [3U], vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__3__KET____DOT__vx_alu__DOT__ALU_in2))
+			    : ((0U == vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__3__KET____DOT__vx_alu__DOT__ALU_in2)
+			        ? vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data
+			       [3U] : VL_MODDIVS_III(32, 
+						     vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data
+						     [3U], vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__3__KET____DOT__vx_alu__DOT__ALU_in2)))
+		        : ((1U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
+			    ? ((0U == vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__3__KET____DOT__vx_alu__DOT__ALU_in2)
+			        ? 0xffffffffU : VL_DIV_III(32, 
+							   vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data
+							   [3U], vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__3__KET____DOT__vx_alu__DOT__ALU_in2))
+			    : ((0U == vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__3__KET____DOT__vx_alu__DOT__ALU_in2)
+			        ? 0xffffffffU : VL_DIVS_III(32, 
+							    vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data
+							    [3U], vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__3__KET____DOT__vx_alu__DOT__ALU_in2))));
+	    } else {
+		if ((2U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))) {
+		    vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellout__genblk1__BRA__3__KET____DOT__vx_alu__out_alu_result 
+			= ((1U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
+			    ? (IData)((((QData)((IData)(
+							vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data
+							[3U])) 
+					* (QData)((IData)(vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__3__KET____DOT__vx_alu__DOT__ALU_in2))) 
+				       >> 0x20U)) : (IData)(
+							    (((((QData)((IData)(
+										VL_NEGATE_I((IData)(
+										(1U 
+										& (vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data
+										[3U] 
+										>> 0x1fU)))))) 
+								<< 0x20U) 
+							       | (QData)((IData)(
+										vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data
+										[3U]))) 
+							      * (QData)((IData)(vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__3__KET____DOT__vx_alu__DOT__ALU_in2))) 
+							     >> 0x20U)));
+		} else {
+		    if (VL_LIKELY((1U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)))) {
+			vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellout__genblk1__BRA__3__KET____DOT__vx_alu__out_alu_result 
+			    = (IData)((vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__3__KET____DOT__vx_alu__DOT__mult_signed_result 
+				       >> 0x20U));
+		    } else {
+			vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellout__genblk1__BRA__3__KET____DOT__vx_alu__out_alu_result 
+			    = (IData)(vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__3__KET____DOT__vx_alu__DOT__mult_signed_result);
+			VL_WRITEF("(%x) %x * %x = %x\n",
+				  32,vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__curr_PC,
+				  32,vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data
+				  [3U],32,vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__3__KET____DOT__vx_alu__DOT__ALU_in2,
+				  32,vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellout__genblk1__BRA__3__KET____DOT__vx_alu__out_alu_result);
+		    }
+		}
+	    }
+	}
+    } else {
+	vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellout__genblk1__BRA__3__KET____DOT__vx_alu__out_alu_result 
+	    = ((8U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
+	        ? ((4U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
+		    ? ((2U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
+		        ? vlTOPp->Vortex__DOT__csr_decode_csr_data
+		        : ((1U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
+			    ? vlTOPp->Vortex__DOT__csr_decode_csr_data
+			    : (vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__curr_PC 
+			       + (vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__upper_immed 
+				  << 0xcU)))) : ((2U 
+						  & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
+						  ? 
+						 ((1U 
+						   & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
+						   ? 
+						  (vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__upper_immed 
+						   << 0xcU)
+						   : 
+						  ((vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data
+						    [3U] 
+						    >= vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__3__KET____DOT__vx_alu__DOT__ALU_in2)
+						    ? 0U
+						    : 0xffffffffU))
+						  : 
+						 ((1U 
+						   & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
+						   ? 
+						  (vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__3__KET____DOT__vx_alu__DOT__ALU_in2 
+						   & vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data
+						   [3U])
+						   : 
+						  (vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data
+						   [3U] 
+						   | vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__3__KET____DOT__vx_alu__DOT__ALU_in2))))
+	        : ((4U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
+		    ? ((2U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
+		        ? ((1U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
+			    ? VL_SHIFTRS_III(32,32,5, 
+					     vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data
+					     [3U], 
+					     (0x1fU 
+					      & vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__3__KET____DOT__vx_alu__DOT__ALU_in2))
+			    : (vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data
+			       [3U] >> (0x1fU & vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__3__KET____DOT__vx_alu__DOT__ALU_in2)))
+		        : ((1U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
+			    ? (vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data
+			       [3U] ^ vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__3__KET____DOT__vx_alu__DOT__ALU_in2)
+			    : ((vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data
+				[3U] < vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__3__KET____DOT__vx_alu__DOT__ALU_in2)
+			        ? 1U : 0U))) : ((2U 
+						 & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
+						 ? 
+						((1U 
+						  & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
+						  ? 
+						 (VL_LTS_III(1,32,32, 
+							     vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data
+							     [3U], vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__3__KET____DOT__vx_alu__DOT__ALU_in2)
+						   ? 1U
+						   : 0U)
+						  : 
+						 (vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data
+						  [3U] 
+						  << 
+						  (0x1fU 
+						   & vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__3__KET____DOT__vx_alu__DOT__ALU_in2)))
+						 : 
+						((1U 
+						  & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
+						  ? 
+						 (vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data
+						  [3U] 
+						  - vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__3__KET____DOT__vx_alu__DOT__ALU_in2)
+						  : 
+						 (vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data
+						  [3U] 
+						  + vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__3__KET____DOT__vx_alu__DOT__ALU_in2)))));
+    }
+    // ALWAYS at VX_alu.v:48
+    if ((0x10U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))) {
+	if ((8U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))) {
+	    vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellout__genblk1__BRA__4__KET____DOT__vx_alu__out_alu_result = 0U;
+	} else {
+	    if ((4U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))) {
+		vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellout__genblk1__BRA__4__KET____DOT__vx_alu__out_alu_result 
+		    = ((2U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
+		        ? ((1U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
+			    ? ((0U == vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__4__KET____DOT__vx_alu__DOT__ALU_in2)
+			        ? vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data
+			       [4U] : VL_MODDIV_III(32, 
+						    vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data
+						    [4U], vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__4__KET____DOT__vx_alu__DOT__ALU_in2))
+			    : ((0U == vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__4__KET____DOT__vx_alu__DOT__ALU_in2)
+			        ? vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data
+			       [4U] : VL_MODDIVS_III(32, 
+						     vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data
+						     [4U], vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__4__KET____DOT__vx_alu__DOT__ALU_in2)))
+		        : ((1U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
+			    ? ((0U == vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__4__KET____DOT__vx_alu__DOT__ALU_in2)
+			        ? 0xffffffffU : VL_DIV_III(32, 
+							   vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data
+							   [4U], vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__4__KET____DOT__vx_alu__DOT__ALU_in2))
+			    : ((0U == vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__4__KET____DOT__vx_alu__DOT__ALU_in2)
+			        ? 0xffffffffU : VL_DIVS_III(32, 
+							    vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data
+							    [4U], vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__4__KET____DOT__vx_alu__DOT__ALU_in2))));
+	    } else {
+		if ((2U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))) {
+		    vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellout__genblk1__BRA__4__KET____DOT__vx_alu__out_alu_result 
+			= ((1U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
+			    ? (IData)((((QData)((IData)(
+							vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data
+							[4U])) 
+					* (QData)((IData)(vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__4__KET____DOT__vx_alu__DOT__ALU_in2))) 
+				       >> 0x20U)) : (IData)(
+							    (((((QData)((IData)(
+										VL_NEGATE_I((IData)(
+										(1U 
+										& (vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data
+										[4U] 
+										>> 0x1fU)))))) 
+								<< 0x20U) 
+							       | (QData)((IData)(
+										vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data
+										[4U]))) 
+							      * (QData)((IData)(vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__4__KET____DOT__vx_alu__DOT__ALU_in2))) 
+							     >> 0x20U)));
+		} else {
+		    if (VL_LIKELY((1U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)))) {
+			vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellout__genblk1__BRA__4__KET____DOT__vx_alu__out_alu_result 
+			    = (IData)((vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__4__KET____DOT__vx_alu__DOT__mult_signed_result 
+				       >> 0x20U));
+		    } else {
+			vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellout__genblk1__BRA__4__KET____DOT__vx_alu__out_alu_result 
+			    = (IData)(vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__4__KET____DOT__vx_alu__DOT__mult_signed_result);
+			VL_WRITEF("(%x) %x * %x = %x\n",
+				  32,vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__curr_PC,
+				  32,vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data
+				  [4U],32,vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__4__KET____DOT__vx_alu__DOT__ALU_in2,
+				  32,vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellout__genblk1__BRA__4__KET____DOT__vx_alu__out_alu_result);
+		    }
+		}
+	    }
+	}
+    } else {
+	vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellout__genblk1__BRA__4__KET____DOT__vx_alu__out_alu_result 
+	    = ((8U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
+	        ? ((4U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
+		    ? ((2U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
+		        ? vlTOPp->Vortex__DOT__csr_decode_csr_data
+		        : ((1U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
+			    ? vlTOPp->Vortex__DOT__csr_decode_csr_data
+			    : (vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__curr_PC 
+			       + (vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__upper_immed 
+				  << 0xcU)))) : ((2U 
+						  & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
+						  ? 
+						 ((1U 
+						   & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
+						   ? 
+						  (vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__upper_immed 
+						   << 0xcU)
+						   : 
+						  ((vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data
+						    [4U] 
+						    >= vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__4__KET____DOT__vx_alu__DOT__ALU_in2)
+						    ? 0U
+						    : 0xffffffffU))
+						  : 
+						 ((1U 
+						   & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
+						   ? 
+						  (vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__4__KET____DOT__vx_alu__DOT__ALU_in2 
+						   & vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data
+						   [4U])
+						   : 
+						  (vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data
+						   [4U] 
+						   | vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__4__KET____DOT__vx_alu__DOT__ALU_in2))))
+	        : ((4U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
+		    ? ((2U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
+		        ? ((1U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
+			    ? VL_SHIFTRS_III(32,32,5, 
+					     vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data
+					     [4U], 
+					     (0x1fU 
+					      & vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__4__KET____DOT__vx_alu__DOT__ALU_in2))
+			    : (vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data
+			       [4U] >> (0x1fU & vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__4__KET____DOT__vx_alu__DOT__ALU_in2)))
+		        : ((1U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
+			    ? (vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data
+			       [4U] ^ vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__4__KET____DOT__vx_alu__DOT__ALU_in2)
+			    : ((vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data
+				[4U] < vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__4__KET____DOT__vx_alu__DOT__ALU_in2)
+			        ? 1U : 0U))) : ((2U 
+						 & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
+						 ? 
+						((1U 
+						  & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
+						  ? 
+						 (VL_LTS_III(1,32,32, 
+							     vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data
+							     [4U], vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__4__KET____DOT__vx_alu__DOT__ALU_in2)
+						   ? 1U
+						   : 0U)
+						  : 
+						 (vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data
+						  [4U] 
+						  << 
+						  (0x1fU 
+						   & vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__4__KET____DOT__vx_alu__DOT__ALU_in2)))
+						 : 
+						((1U 
+						  & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
+						  ? 
+						 (vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data
+						  [4U] 
+						  - vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__4__KET____DOT__vx_alu__DOT__ALU_in2)
+						  : 
+						 (vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data
+						  [4U] 
+						  + vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__4__KET____DOT__vx_alu__DOT__ALU_in2)))));
     }
     vlTOPp->Vortex__DOT__fetch_valid[4U] = vlTOPp->Vortex__DOT____Vcellout__vx_fetch__out_valid
 	[4U];
@@ -4305,9 +5364,15 @@ void VVortex::_settle__TOP__8(VVortex__Syms* __restrict vlSymsp) {
     vlTOPp->Vortex__DOT__fetch_valid[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_fetch__out_valid
 	[0U];
     vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_alu_result[0U] 
-	= vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellout__vx_alu_0__out_alu_result;
+	= vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellout__genblk1__BRA__0__KET____DOT__vx_alu__out_alu_result;
     vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_alu_result[1U] 
-	= vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellout__vx_alu_1__out_alu_result;
+	= vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellout__genblk1__BRA__1__KET____DOT__vx_alu__out_alu_result;
+    vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_alu_result[2U] 
+	= vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellout__genblk1__BRA__2__KET____DOT__vx_alu__out_alu_result;
+    vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_alu_result[3U] 
+	= vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellout__genblk1__BRA__3__KET____DOT__vx_alu__out_alu_result;
+    vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_alu_result[4U] 
+	= vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellout__genblk1__BRA__4__KET____DOT__vx_alu__out_alu_result;
     vlTOPp->Vortex__DOT____Vcellinp__vx_f_d_reg__in_valid[4U] 
 	= vlTOPp->Vortex__DOT__fetch_valid[4U];
     vlTOPp->Vortex__DOT____Vcellinp__vx_f_d_reg__in_valid[3U] 
@@ -5600,16 +6665,31 @@ void VVortex::_ctor_var_reset() {
     Vortex__DOT__vx_decode__DOT__is_csr = VL_RAND_RESET_I(1);
     Vortex__DOT__vx_decode__DOT__alu_tempp = VL_RAND_RESET_I(12);
     Vortex__DOT__vx_decode__DOT__mul_alu = VL_RAND_RESET_I(5);
-    Vortex__DOT__vx_decode__DOT____Vcellout__vx_register_file_0__out_src2_data = VL_RAND_RESET_I(32);
-    Vortex__DOT__vx_decode__DOT____Vcellout__vx_register_file_0__out_src1_data = VL_RAND_RESET_I(32);
-    Vortex__DOT__vx_decode__DOT____Vcellout__vx_register_file_1__out_src2_data = VL_RAND_RESET_I(32);
-    Vortex__DOT__vx_decode__DOT____Vcellout__vx_register_file_1__out_src1_data = VL_RAND_RESET_I(32);
     Vortex__DOT__vx_decode__DOT__temp_final_alu = VL_RAND_RESET_I(5);
+    Vortex__DOT__vx_decode__DOT____Vcellout__gen_code_label__BRA__0__KET____DOT__vx_register_file__out_src2_data = VL_RAND_RESET_I(32);
+    Vortex__DOT__vx_decode__DOT____Vcellout__gen_code_label__BRA__0__KET____DOT__vx_register_file__out_src1_data = VL_RAND_RESET_I(32);
+    Vortex__DOT__vx_decode__DOT____Vcellout__gen_code_label__BRA__1__KET____DOT__vx_register_file__out_src2_data = VL_RAND_RESET_I(32);
+    Vortex__DOT__vx_decode__DOT____Vcellout__gen_code_label__BRA__1__KET____DOT__vx_register_file__out_src1_data = VL_RAND_RESET_I(32);
+    Vortex__DOT__vx_decode__DOT____Vcellout__gen_code_label__BRA__2__KET____DOT__vx_register_file__out_src2_data = VL_RAND_RESET_I(32);
+    Vortex__DOT__vx_decode__DOT____Vcellout__gen_code_label__BRA__2__KET____DOT__vx_register_file__out_src1_data = VL_RAND_RESET_I(32);
+    Vortex__DOT__vx_decode__DOT____Vcellout__gen_code_label__BRA__3__KET____DOT__vx_register_file__out_src2_data = VL_RAND_RESET_I(32);
+    Vortex__DOT__vx_decode__DOT____Vcellout__gen_code_label__BRA__3__KET____DOT__vx_register_file__out_src1_data = VL_RAND_RESET_I(32);
+    Vortex__DOT__vx_decode__DOT____Vcellout__gen_code_label__BRA__4__KET____DOT__vx_register_file__out_src2_data = VL_RAND_RESET_I(32);
+    Vortex__DOT__vx_decode__DOT____Vcellout__gen_code_label__BRA__4__KET____DOT__vx_register_file__out_src1_data = VL_RAND_RESET_I(32);
     { int __Vi0=0; for (; __Vi0<32; ++__Vi0) {
-	    Vortex__DOT__vx_decode__DOT__vx_register_file_0__DOT__registers[__Vi0] = VL_RAND_RESET_I(32);
+	    Vortex__DOT__vx_decode__DOT__gen_code_label__BRA__0__KET____DOT__vx_register_file__DOT__registers[__Vi0] = VL_RAND_RESET_I(32);
     }}
     { int __Vi0=0; for (; __Vi0<32; ++__Vi0) {
-	    Vortex__DOT__vx_decode__DOT__vx_register_file_1__DOT__registers[__Vi0] = VL_RAND_RESET_I(32);
+	    Vortex__DOT__vx_decode__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file__DOT__registers[__Vi0] = VL_RAND_RESET_I(32);
+    }}
+    { int __Vi0=0; for (; __Vi0<32; ++__Vi0) {
+	    Vortex__DOT__vx_decode__DOT__gen_code_label__BRA__2__KET____DOT__vx_register_file__DOT__registers[__Vi0] = VL_RAND_RESET_I(32);
+    }}
+    { int __Vi0=0; for (; __Vi0<32; ++__Vi0) {
+	    Vortex__DOT__vx_decode__DOT__gen_code_label__BRA__3__KET____DOT__vx_register_file__DOT__registers[__Vi0] = VL_RAND_RESET_I(32);
+    }}
+    { int __Vi0=0; for (; __Vi0<32; ++__Vi0) {
+	    Vortex__DOT__vx_decode__DOT__gen_code_label__BRA__4__KET____DOT__vx_register_file__DOT__registers[__Vi0] = VL_RAND_RESET_I(32);
     }}
     Vortex__DOT__vx_d_e_reg__DOT__rd = VL_RAND_RESET_I(5);
     { int __Vi0=0; for (; __Vi0<5; ++__Vi0) {
@@ -5643,12 +6723,21 @@ void VVortex::_ctor_var_reset() {
 	    Vortex__DOT__vx_d_e_reg__DOT__valid_z[__Vi0] = VL_RAND_RESET_I(1);
     }}
     Vortex__DOT__vx_d_e_reg__DOT__stalling = VL_RAND_RESET_I(1);
-    Vortex__DOT__vx_execute__DOT____Vcellout__vx_alu_0__out_alu_result = VL_RAND_RESET_I(32);
-    Vortex__DOT__vx_execute__DOT____Vcellout__vx_alu_1__out_alu_result = VL_RAND_RESET_I(32);
-    Vortex__DOT__vx_execute__DOT__vx_alu_0__DOT__ALU_in2 = VL_RAND_RESET_I(32);
-    Vortex__DOT__vx_execute__DOT__vx_alu_0__DOT__mult_signed_result = VL_RAND_RESET_Q(64);
-    Vortex__DOT__vx_execute__DOT__vx_alu_1__DOT__ALU_in2 = VL_RAND_RESET_I(32);
-    Vortex__DOT__vx_execute__DOT__vx_alu_1__DOT__mult_signed_result = VL_RAND_RESET_Q(64);
+    Vortex__DOT__vx_execute__DOT____Vcellout__genblk1__BRA__0__KET____DOT__vx_alu__out_alu_result = VL_RAND_RESET_I(32);
+    Vortex__DOT__vx_execute__DOT____Vcellout__genblk1__BRA__1__KET____DOT__vx_alu__out_alu_result = VL_RAND_RESET_I(32);
+    Vortex__DOT__vx_execute__DOT____Vcellout__genblk1__BRA__2__KET____DOT__vx_alu__out_alu_result = VL_RAND_RESET_I(32);
+    Vortex__DOT__vx_execute__DOT____Vcellout__genblk1__BRA__3__KET____DOT__vx_alu__out_alu_result = VL_RAND_RESET_I(32);
+    Vortex__DOT__vx_execute__DOT____Vcellout__genblk1__BRA__4__KET____DOT__vx_alu__out_alu_result = VL_RAND_RESET_I(32);
+    Vortex__DOT__vx_execute__DOT__genblk1__BRA__0__KET____DOT__vx_alu__DOT__ALU_in2 = VL_RAND_RESET_I(32);
+    Vortex__DOT__vx_execute__DOT__genblk1__BRA__0__KET____DOT__vx_alu__DOT__mult_signed_result = VL_RAND_RESET_Q(64);
+    Vortex__DOT__vx_execute__DOT__genblk1__BRA__1__KET____DOT__vx_alu__DOT__ALU_in2 = VL_RAND_RESET_I(32);
+    Vortex__DOT__vx_execute__DOT__genblk1__BRA__1__KET____DOT__vx_alu__DOT__mult_signed_result = VL_RAND_RESET_Q(64);
+    Vortex__DOT__vx_execute__DOT__genblk1__BRA__2__KET____DOT__vx_alu__DOT__ALU_in2 = VL_RAND_RESET_I(32);
+    Vortex__DOT__vx_execute__DOT__genblk1__BRA__2__KET____DOT__vx_alu__DOT__mult_signed_result = VL_RAND_RESET_Q(64);
+    Vortex__DOT__vx_execute__DOT__genblk1__BRA__3__KET____DOT__vx_alu__DOT__ALU_in2 = VL_RAND_RESET_I(32);
+    Vortex__DOT__vx_execute__DOT__genblk1__BRA__3__KET____DOT__vx_alu__DOT__mult_signed_result = VL_RAND_RESET_Q(64);
+    Vortex__DOT__vx_execute__DOT__genblk1__BRA__4__KET____DOT__vx_alu__DOT__ALU_in2 = VL_RAND_RESET_I(32);
+    Vortex__DOT__vx_execute__DOT__genblk1__BRA__4__KET____DOT__vx_alu__DOT__mult_signed_result = VL_RAND_RESET_Q(64);
     { int __Vi0=0; for (; __Vi0<5; ++__Vi0) {
 	    Vortex__DOT__vx_e_m_reg__DOT__alu_result[__Vi0] = VL_RAND_RESET_I(32);
     }}
diff --git a/rtl/obj_dir/VVortex.h b/rtl/obj_dir/VVortex.h
index 7b456d55..8f29b43b 100644
--- a/rtl/obj_dir/VVortex.h
+++ b/rtl/obj_dir/VVortex.h
@@ -100,18 +100,24 @@ VL_MODULE(VVortex) {
 	VL_SIG(Vortex__DOT__vx_d_e_reg__DOT__csr_mask,31,0);
 	VL_SIG(Vortex__DOT__vx_d_e_reg__DOT__curr_PC,31,0);
 	VL_SIG(Vortex__DOT__vx_d_e_reg__DOT__jal_offset,31,0);
-	VL_SIG(Vortex__DOT__vx_execute__DOT__vx_alu_0__DOT__ALU_in2,31,0);
+	VL_SIG(Vortex__DOT__vx_execute__DOT__genblk1__BRA__0__KET____DOT__vx_alu__DOT__ALU_in2,31,0);
     };
     struct {
-	VL_SIG(Vortex__DOT__vx_execute__DOT__vx_alu_1__DOT__ALU_in2,31,0);
+	VL_SIG(Vortex__DOT__vx_execute__DOT__genblk1__BRA__1__KET____DOT__vx_alu__DOT__ALU_in2,31,0);
+	VL_SIG(Vortex__DOT__vx_execute__DOT__genblk1__BRA__2__KET____DOT__vx_alu__DOT__ALU_in2,31,0);
+	VL_SIG(Vortex__DOT__vx_execute__DOT__genblk1__BRA__3__KET____DOT__vx_alu__DOT__ALU_in2,31,0);
+	VL_SIG(Vortex__DOT__vx_execute__DOT__genblk1__BRA__4__KET____DOT__vx_alu__DOT__ALU_in2,31,0);
 	VL_SIG(Vortex__DOT__vx_e_m_reg__DOT__PC_next,31,0);
 	VL_SIG(Vortex__DOT__vx_e_m_reg__DOT__csr_result,31,0);
 	VL_SIG(Vortex__DOT__vx_e_m_reg__DOT__curr_PC,31,0);
 	VL_SIG(Vortex__DOT__vx_e_m_reg__DOT__branch_offset,31,0);
 	VL_SIG(Vortex__DOT__vx_e_m_reg__DOT__jal_dest,31,0);
 	VL_SIG(Vortex__DOT__vx_m_w_reg__DOT__PC_next,31,0);
-	VL_SIG64(Vortex__DOT__vx_execute__DOT__vx_alu_0__DOT__mult_signed_result,63,0);
-	VL_SIG64(Vortex__DOT__vx_execute__DOT__vx_alu_1__DOT__mult_signed_result,63,0);
+	VL_SIG64(Vortex__DOT__vx_execute__DOT__genblk1__BRA__0__KET____DOT__vx_alu__DOT__mult_signed_result,63,0);
+	VL_SIG64(Vortex__DOT__vx_execute__DOT__genblk1__BRA__1__KET____DOT__vx_alu__DOT__mult_signed_result,63,0);
+	VL_SIG64(Vortex__DOT__vx_execute__DOT__genblk1__BRA__2__KET____DOT__vx_alu__DOT__mult_signed_result,63,0);
+	VL_SIG64(Vortex__DOT__vx_execute__DOT__genblk1__BRA__3__KET____DOT__vx_alu__DOT__mult_signed_result,63,0);
+	VL_SIG64(Vortex__DOT__vx_execute__DOT__genblk1__BRA__4__KET____DOT__vx_alu__DOT__mult_signed_result,63,0);
 	VL_SIG64(Vortex__DOT__vx_csr_handler__DOT__cycle,63,0);
 	VL_SIG64(Vortex__DOT__vx_csr_handler__DOT__instret,63,0);
 	VL_SIG8(Vortex__DOT__fetch_valid[5],0,0);
@@ -140,8 +146,11 @@ VL_MODULE(VVortex) {
 	VL_SIG8(Vortex__DOT__vx_f_d_reg__DOT__valid[5],0,0);
 	VL_SIG(Vortex__DOT__vx_decode__DOT__rd1_register[5],31,0);
 	VL_SIG(Vortex__DOT__vx_decode__DOT__rd2_register[5],31,0);
-	VL_SIG(Vortex__DOT__vx_decode__DOT__vx_register_file_0__DOT__registers[32],31,0);
-	VL_SIG(Vortex__DOT__vx_decode__DOT__vx_register_file_1__DOT__registers[32],31,0);
+	VL_SIG(Vortex__DOT__vx_decode__DOT__gen_code_label__BRA__0__KET____DOT__vx_register_file__DOT__registers[32],31,0);
+	VL_SIG(Vortex__DOT__vx_decode__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file__DOT__registers[32],31,0);
+	VL_SIG(Vortex__DOT__vx_decode__DOT__gen_code_label__BRA__2__KET____DOT__vx_register_file__DOT__registers[32],31,0);
+	VL_SIG(Vortex__DOT__vx_decode__DOT__gen_code_label__BRA__3__KET____DOT__vx_register_file__DOT__registers[32],31,0);
+	VL_SIG(Vortex__DOT__vx_decode__DOT__gen_code_label__BRA__4__KET____DOT__vx_register_file__DOT__registers[32],31,0);
 	VL_SIG(Vortex__DOT__vx_d_e_reg__DOT__a_reg_data[5],31,0);
 	VL_SIG(Vortex__DOT__vx_d_e_reg__DOT__b_reg_data[5],31,0);
 	VL_SIG8(Vortex__DOT__vx_d_e_reg__DOT__valid[5],0,0);
@@ -158,6 +167,8 @@ VL_MODULE(VVortex) {
 	VL_SIG(Vortex__DOT__vx_forwarding__DOT__use_execute_PC_next[5],31,0);
 	VL_SIG(Vortex__DOT__vx_forwarding__DOT__use_memory_PC_next[5],31,0);
 	VL_SIG(Vortex__DOT__vx_forwarding__DOT__use_writeback_PC_next[5],31,0);
+    };
+    struct {
 	VL_SIG16(Vortex__DOT__vx_csr_handler__DOT__csr[4096],11,0);
     };
     
@@ -169,12 +180,21 @@ VL_MODULE(VVortex) {
 	VL_SIG8(__Vtableidx1,2,0);
 	VL_SIG8(__Vclklast__TOP__clk,0,0);
 	VL_SIG8(__Vclklast__TOP__reset,0,0);
-	VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellout__vx_register_file_0__out_src2_data,31,0);
-	VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellout__vx_register_file_0__out_src1_data,31,0);
-	VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellout__vx_register_file_1__out_src2_data,31,0);
-	VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellout__vx_register_file_1__out_src1_data,31,0);
-	VL_SIG(Vortex__DOT__vx_execute__DOT____Vcellout__vx_alu_0__out_alu_result,31,0);
-	VL_SIG(Vortex__DOT__vx_execute__DOT____Vcellout__vx_alu_1__out_alu_result,31,0);
+	VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellout__gen_code_label__BRA__0__KET____DOT__vx_register_file__out_src2_data,31,0);
+	VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellout__gen_code_label__BRA__0__KET____DOT__vx_register_file__out_src1_data,31,0);
+	VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellout__gen_code_label__BRA__1__KET____DOT__vx_register_file__out_src2_data,31,0);
+	VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellout__gen_code_label__BRA__1__KET____DOT__vx_register_file__out_src1_data,31,0);
+	VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellout__gen_code_label__BRA__2__KET____DOT__vx_register_file__out_src2_data,31,0);
+	VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellout__gen_code_label__BRA__2__KET____DOT__vx_register_file__out_src1_data,31,0);
+	VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellout__gen_code_label__BRA__3__KET____DOT__vx_register_file__out_src2_data,31,0);
+	VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellout__gen_code_label__BRA__3__KET____DOT__vx_register_file__out_src1_data,31,0);
+	VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellout__gen_code_label__BRA__4__KET____DOT__vx_register_file__out_src2_data,31,0);
+	VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellout__gen_code_label__BRA__4__KET____DOT__vx_register_file__out_src1_data,31,0);
+	VL_SIG(Vortex__DOT__vx_execute__DOT____Vcellout__genblk1__BRA__0__KET____DOT__vx_alu__out_alu_result,31,0);
+	VL_SIG(Vortex__DOT__vx_execute__DOT____Vcellout__genblk1__BRA__1__KET____DOT__vx_alu__out_alu_result,31,0);
+	VL_SIG(Vortex__DOT__vx_execute__DOT____Vcellout__genblk1__BRA__2__KET____DOT__vx_alu__out_alu_result,31,0);
+	VL_SIG(Vortex__DOT__vx_execute__DOT____Vcellout__genblk1__BRA__3__KET____DOT__vx_alu__out_alu_result,31,0);
+	VL_SIG(Vortex__DOT__vx_execute__DOT____Vcellout__genblk1__BRA__4__KET____DOT__vx_alu__out_alu_result,31,0);
 	VL_SIG8(Vortex__DOT____Vcellout__vx_fetch__out_valid[5],0,0);
 	VL_SIG8(Vortex__DOT____Vcellout__vx_f_d_reg__out_valid[5],0,0);
 	VL_SIG8(Vortex__DOT____Vcellinp__vx_f_d_reg__in_valid[5],0,0);
@@ -221,6 +241,8 @@ VL_MODULE(VVortex) {
 	VL_SIG(Vortex__DOT____Vcellinp__vx_m_w_reg__in_mem_result[5],31,0);
 	VL_SIG(Vortex__DOT____Vcellinp__vx_m_w_reg__in_alu_result[5],31,0);
 	VL_SIG(Vortex__DOT____Vcellout__vx_writeback__out_write_data[5],31,0);
+    };
+    struct {
 	VL_SIG8(Vortex__DOT____Vcellinp__vx_writeback__in_valid[5],0,0);
 	VL_SIG(Vortex__DOT____Vcellinp__vx_writeback__in_mem_result[5],31,0);
 	VL_SIG(Vortex__DOT____Vcellinp__vx_writeback__in_alu_result[5],31,0);
@@ -230,8 +252,6 @@ VL_MODULE(VVortex) {
 	VL_SIG(Vortex__DOT____Vcellinp__vx_forwarding__in_writeback_alu_result[5],31,0);
 	VL_SIG(Vortex__DOT____Vcellinp__vx_forwarding__in_memory_mem_data[5],31,0);
 	VL_SIG(Vortex__DOT____Vcellinp__vx_forwarding__in_memory_alu_result[5],31,0);
-    };
-    struct {
 	VL_SIG(Vortex__DOT____Vcellinp__vx_forwarding__in_execute_alu_result[5],31,0);
     };
     static VL_ST_SIG8(__Vtable1_Vortex__DOT__vx_decode__DOT__mul_alu[8],4,0);
diff --git a/rtl/obj_dir/VVortex__ALL.a b/rtl/obj_dir/VVortex__ALL.a
index 3065c98d..595ff947 100644
Binary files a/rtl/obj_dir/VVortex__ALL.a and b/rtl/obj_dir/VVortex__ALL.a differ
diff --git a/rtl/obj_dir/VVortex__ALLcls.o b/rtl/obj_dir/VVortex__ALLcls.o
index 01499726..98597450 100644
Binary files a/rtl/obj_dir/VVortex__ALLcls.o and b/rtl/obj_dir/VVortex__ALLcls.o differ
diff --git a/rtl/obj_dir/VVortex__verFiles.dat b/rtl/obj_dir/VVortex__verFiles.dat
index c2ed054e..054804cf 100644
--- a/rtl/obj_dir/VVortex__verFiles.dat
+++ b/rtl/obj_dir/VVortex__verFiles.dat
@@ -4,23 +4,23 @@ S   4608404 12889046060  1553037052           0  1548678579           0 "/usr/lo
 S      2862 12889318286  1553966962           0  1553966962           0 "VX_alu.v"
 S      1495 12889087229  1553211178           0  1553211178           0 "VX_csr_handler.v"
 S      5040 12889318287  1553995422           0  1553995422           0 "VX_d_e_reg.v"
-S     11888 12889419225  1553995767           0  1553995767           0 "VX_decode.v"
+S     11230 12889419225  1554000860           0  1554000860           0 "VX_decode.v"
 S      1532 12889419227  1553998396           0  1553998396           0 "VX_define.v"
 S      4077 12889318289  1553997299           0  1553997299           0 "VX_e_m_reg.v"
-S      4908 12889318290  1553997136           0  1553997136           0 "VX_execute.v"
+S      3288 12889318290  1554000824           0  1554000824           0 "VX_execute.v"
 S      1382 12889050060  1553673124           0  1553673124           0 "VX_f_d_reg.v"
-S      4042 12889419228  1553998456           0  1553998456           0 "VX_fetch.v"
+S      4020 12889419228  1554000776           0  1554000776           0 "VX_fetch.v"
 S      5632 12889086478  1553672336           0  1553672336           0 "VX_forwarding.v"
 S      1677 12889085814  1553673165           0  1553673165           0 "VX_m_w_reg.v"
 S      3002 12889084513  1553997670           0  1553997670           0 "VX_memory.v"
 S      1003 12889419229  1553930745           0  1553930745           0 "VX_register_file.v"
 S      1173 12889419230  1553930874           0  1553930874           0 "VX_writeback.v"
 S     16452 12889419231  1553997933           0  1553997933           0 "Vortex.v"
-T    276821 12889432530  1553998459           0  1553998459           0 "obj_dir/VVortex.cpp"
-T     14673 12889432529  1553998459           0  1553998459           0 "obj_dir/VVortex.h"
-T      1800 12889432532  1553998459           0  1553998459           0 "obj_dir/VVortex.mk"
-T       530 12889432528  1553998459           0  1553998459           0 "obj_dir/VVortex__Syms.cpp"
-T       717 12889432527  1553998459           0  1553998459           0 "obj_dir/VVortex__Syms.h"
-T       464 12889432533  1553998459           0  1553998459           0 "obj_dir/VVortex__ver.d"
-T         0        0  1553998459           0  1553998459           0 "obj_dir/VVortex__verFiles.dat"
-T      1159 12889432531  1553998459           0  1553998459           0 "obj_dir/VVortex_classes.mk"
+T    347293 12889432530  1554000904           0  1554000904           0 "obj_dir/VVortex.cpp"
+T     17090 12889432529  1554000904           0  1554000904           0 "obj_dir/VVortex.h"
+T      1800 12889432532  1554000904           0  1554000904           0 "obj_dir/VVortex.mk"
+T       530 12889432528  1554000904           0  1554000904           0 "obj_dir/VVortex__Syms.cpp"
+T       717 12889432527  1554000904           0  1554000904           0 "obj_dir/VVortex__Syms.h"
+T       464 12889432533  1554000904           0  1554000904           0 "obj_dir/VVortex__ver.d"
+T         0        0  1554000904           0  1554000904           0 "obj_dir/VVortex__verFiles.dat"
+T      1159 12889432531  1554000904           0  1554000904           0 "obj_dir/VVortex_classes.mk"
diff --git a/rtl/obj_dir/debug.txt b/rtl/obj_dir/debug.txt
index e55f0191..315ddda4 100644
--- a/rtl/obj_dir/debug.txt
+++ b/rtl/obj_dir/debug.txt
@@ -98567,6 +98567,9 @@ RF: Writing 00008000 to  1
 RF: Writing 00007e00 to  1
 (800000cc) 00007e00 * b6db6db7 = 00001200
 (800000cc) 00007e00 * b6db6db7 = 00001200
+(800000cc) 00007e00 * b6db6db7 = 00001200
+(800000cc) 00007e00 * b6db6db7 = 00001200
+(800000cc) 00007e00 * b6db6db7 = 00001200
 ----
 ******
 [800000c4] WB Data: b6db7000 {babebabe}, to register:  2 [1 0]
@@ -98640,6 +98643,9 @@ RF: Writing 00008000 to  1
 RF: Writing 00007fc0 to  1
 (800000f0) 00007fc0 * b6db6db7 = 00001240
 (800000f0) 00007fc0 * b6db6db7 = 00001240
+(800000f0) 00007fc0 * b6db6db7 = 00001240
+(800000f0) 00007fc0 * b6db6db7 = 00001240
+(800000f0) 00007fc0 * b6db6db7 = 00001240
 ----
 ******
 [800000e8] WB Data: b6db7000 {babebabe}, to register:  2 [1 0]
@@ -98699,6 +98705,9 @@ RF: Writing 00000021 to 28
 ******
 (8000010c) 00000000 * 00000000 = 00000000
 (8000010c) 00000000 * 00000000 = 00000000
+(8000010c) 00000000 * 00000000 = 00000000
+(8000010c) 00000000 * 00000000 = 00000000
+(8000010c) 00000000 * 00000000 = 00000000
 ----
 ******
 [80000104] WB Data: 00000000 {babebabe}, to register:  1 [1 0]
@@ -98751,6 +98760,9 @@ RF: Writing 00000002 to 28
 ******
 (80000124) 00000001 * 00000001 = 00000001
 (80000124) 00000001 * 00000001 = 00000001
+(80000124) 00000001 * 00000001 = 00000001
+(80000124) 00000001 * 00000001 = 00000001
+(80000124) 00000001 * 00000001 = 00000001
 ----
 ******
 [8000011c] WB Data: 00000001 {babebabe}, to register:  1 [1 0]
@@ -98803,6 +98815,9 @@ RF: Writing 00000003 to 28
 ******
 (8000013c) 00000003 * 00000007 = 00000015
 (8000013c) 00000003 * 00000007 = 00000015
+(8000013c) 00000003 * 00000007 = 00000015
+(8000013c) 00000003 * 00000007 = 00000015
+(8000013c) 00000003 * 00000007 = 00000015
 ----
 ******
 [80000134] WB Data: 00000003 {babebabe}, to register:  1 [1 0]
@@ -98855,6 +98870,9 @@ RF: Writing 00000004 to 28
 ******
 (80000154) 00000000 * ffff8000 = 00000000
 (80000154) 00000000 * ffff8000 = 00000000
+(80000154) 00000000 * ffff8000 = 00000000
+(80000154) 00000000 * ffff8000 = 00000000
+(80000154) 00000000 * ffff8000 = 00000000
 ----
 ******
 [8000014c] WB Data: 00000000 {babebabe}, to register:  1 [1 0]
@@ -98907,6 +98925,9 @@ RF: Writing 00000005 to 28
 ******
 (8000016c) 80000000 * 00000000 = 00000000
 (8000016c) 80000000 * 00000000 = 00000000
+(8000016c) 80000000 * 00000000 = 00000000
+(8000016c) 80000000 * 00000000 = 00000000
+(8000016c) 80000000 * 00000000 = 00000000
 ----
 ******
 [80000164] WB Data: 80000000 {babebabe}, to register:  1 [1 0]
@@ -98959,6 +98980,9 @@ RF: Writing 00000006 to 28
 ******
 (80000184) 80000000 * ffff8000 = 00000000
 (80000184) 80000000 * ffff8000 = 00000000
+(80000184) 80000000 * ffff8000 = 00000000
+(80000184) 80000000 * ffff8000 = 00000000
+(80000184) 80000000 * ffff8000 = 00000000
 ----
 ******
 [8000017c] WB Data: 80000000 {babebabe}, to register:  1 [1 0]
@@ -99025,6 +99049,9 @@ RF: Writing aaaab000 to  1
 RF: Writing aaaaaaab to  1
 (800001a4) aaaaaaab * 0002fe7d = 0000ff7f
 (800001a4) aaaaaaab * 0002fe7d = 0000ff7f
+(800001a4) aaaaaaab * 0002fe7d = 0000ff7f
+(800001a4) aaaaaaab * 0002fe7d = 0000ff7f
+(800001a4) aaaaaaab * 0002fe7d = 0000ff7f
 ----
 ******
 [8000019c] WB Data: 00030000 {babebabe}, to register:  2 [1 0]
@@ -99098,6 +99125,9 @@ RF: Writing 00030000 to  1
 RF: Writing 0002fe7d to  1
 (800001c8) 0002fe7d * aaaaaaab = 0000ff7f
 (800001c8) 0002fe7d * aaaaaaab = 0000ff7f
+(800001c8) 0002fe7d * aaaaaaab = 0000ff7f
+(800001c8) 0002fe7d * aaaaaaab = 0000ff7f
+(800001c8) 0002fe7d * aaaaaaab = 0000ff7f
 ----
 ******
 [800001c0] WB Data: aaaab000 {babebabe}, to register:  2 [1 0]
@@ -99157,6 +99187,9 @@ RF: Writing 0000001f to 28
 ******
 (800001e4) ff000000 * ff000000 = 00000000
 (800001e4) ff000000 * ff000000 = 00000000
+(800001e4) ff000000 * ff000000 = 00000000
+(800001e4) ff000000 * ff000000 = 00000000
+(800001e4) ff000000 * ff000000 = 00000000
 ----
 ******
 [800001dc] WB Data: ff000000 {babebabe}, to register:  1 [1 0]
@@ -99209,6 +99242,9 @@ RF: Writing 00000022 to 28
 ******
 (800001fc) ffffffff * ffffffff = 00000001
 (800001fc) ffffffff * ffffffff = 00000001
+(800001fc) ffffffff * ffffffff = 00000001
+(800001fc) ffffffff * ffffffff = 00000001
+(800001fc) ffffffff * ffffffff = 00000001
 ----
 ******
 [800001f4] WB Data: ffffffff {babebabe}, to register:  1 [1 0]
@@ -99261,6 +99297,9 @@ RF: Writing 00000023 to 28
 ******
 (80000214) ffffffff * 00000001 = ffffffff
 (80000214) ffffffff * 00000001 = ffffffff
+(80000214) ffffffff * 00000001 = ffffffff
+(80000214) ffffffff * 00000001 = ffffffff
+(80000214) ffffffff * 00000001 = ffffffff
 ----
 ******
 [8000020c] WB Data: ffffffff {babebabe}, to register:  1 [1 0]
@@ -99313,6 +99352,9 @@ RF: Writing 00000024 to 28
 ******
 (8000022c) 00000001 * ffffffff = ffffffff
 (8000022c) 00000001 * ffffffff = ffffffff
+(8000022c) 00000001 * ffffffff = ffffffff
+(8000022c) 00000001 * ffffffff = ffffffff
+(8000022c) 00000001 * ffffffff = ffffffff
 ----
 ******
 [80000224] WB Data: 00000001 {babebabe}, to register:  1 [1 0]
@@ -99365,6 +99407,9 @@ RF: Writing 00000025 to 28
 ******
 (80000244) 0000000d * 0000000b = 0000008f
 (80000244) 0000000d * 0000000b = 0000008f
+(80000244) 0000000d * 0000000b = 0000008f
+(80000244) 0000000d * 0000000b = 0000008f
+(80000244) 0000000d * 0000000b = 0000008f
 ----
 ******
 [8000023c] WB Data: 0000000d {babebabe}, to register:  1 [1 0]
@@ -99417,6 +99462,9 @@ RF: Writing 00000008 to 28
 ******
 (8000025c) 0000000e * 0000000b = 0000009a
 (8000025c) 0000000e * 0000000b = 0000009a
+(8000025c) 0000000e * 0000000b = 0000009a
+(8000025c) 0000000e * 0000000b = 0000009a
+(8000025c) 0000000e * 0000000b = 0000009a
 ----
 ******
 [80000254] WB Data: 0000000e {babebabe}, to register:  1 [1 0]
@@ -99464,6 +99512,9 @@ RF: Writing 00000009 to 28
 ******
 (80000270) 0000000d * 0000000d = 000000a9
 (80000270) 0000000d * 0000000d = 000000a9
+(80000270) 0000000d * 0000000d = 000000a9
+(80000270) 0000000d * 0000000d = 000000a9
+(80000270) 0000000d * 0000000d = 000000a9
 ----
 ******
 
@@ -99521,6 +99572,9 @@ RF: Writing 0000000a to 28
 RF: Writing 00000000 to  4
 (8000028c) 0000000d * 0000000b = 0000008f
 (8000028c) 0000000d * 0000000b = 0000008f
+(8000028c) 0000000d * 0000000b = 0000008f
+(8000028c) 0000000d * 0000000b = 0000008f
+(8000028c) 0000000d * 0000000b = 0000008f
 ----
 ******
 [80000284] WB Data: 0000000d {babebabe}, to register:  1 [1 0]
@@ -99580,6 +99634,9 @@ RF: Writing 00000002 to  5
 ******
 (8000028c) 0000000d * 0000000b = 0000008f
 (8000028c) 0000000d * 0000000b = 0000008f
+(8000028c) 0000000d * 0000000b = 0000008f
+(8000028c) 0000000d * 0000000b = 0000008f
+(8000028c) 0000000d * 0000000b = 0000008f
 ----
 ******
 [80000284] WB Data: 0000000d {babebabe}, to register:  1 [1 0]
@@ -99675,6 +99732,9 @@ RF: Writing 0000000b to 28
 RF: Writing 00000000 to  4
 (800002b8) 0000000e * 0000000b = 0000009a
 (800002b8) 0000000e * 0000000b = 0000009a
+(800002b8) 0000000e * 0000000b = 0000009a
+(800002b8) 0000000e * 0000000b = 0000009a
+(800002b8) 0000000e * 0000000b = 0000009a
 ----
 ******
 [800002b0] WB Data: 0000000e {babebabe}, to register:  1 [1 0]
@@ -99740,6 +99800,9 @@ RF: Writing 00000002 to  5
 ******
 (800002b8) 0000000e * 0000000b = 0000009a
 (800002b8) 0000000e * 0000000b = 0000009a
+(800002b8) 0000000e * 0000000b = 0000009a
+(800002b8) 0000000e * 0000000b = 0000009a
+(800002b8) 0000000e * 0000000b = 0000009a
 ----
 ******
 [800002b0] WB Data: 0000000e {babebabe}, to register:  1 [1 0]
@@ -99841,6 +99904,9 @@ RF: Writing 0000000c to 28
 RF: Writing 00000000 to  4
 (800002e8) 0000000f * 0000000b = 000000a5
 (800002e8) 0000000f * 0000000b = 000000a5
+(800002e8) 0000000f * 0000000b = 000000a5
+(800002e8) 0000000f * 0000000b = 000000a5
+(800002e8) 0000000f * 0000000b = 000000a5
 ----
 ******
 [800002e0] WB Data: 0000000f {babebabe}, to register:  1 [1 0]
@@ -99912,6 +99978,9 @@ RF: Writing 00000002 to  5
 ******
 (800002e8) 0000000f * 0000000b = 000000a5
 (800002e8) 0000000f * 0000000b = 000000a5
+(800002e8) 0000000f * 0000000b = 000000a5
+(800002e8) 0000000f * 0000000b = 000000a5
+(800002e8) 0000000f * 0000000b = 000000a5
 ----
 ******
 [800002e0] WB Data: 0000000f {babebabe}, to register:  1 [1 0]
@@ -100019,6 +100088,9 @@ RF: Writing 0000000d to 28
 RF: Writing 00000000 to  4
 (8000031c) 0000000d * 0000000b = 0000008f
 (8000031c) 0000000d * 0000000b = 0000008f
+(8000031c) 0000000d * 0000000b = 0000008f
+(8000031c) 0000000d * 0000000b = 0000008f
+(8000031c) 0000000d * 0000000b = 0000008f
 ----
 ******
 [80000314] WB Data: 0000000d {babebabe}, to register:  1 [1 0]
@@ -100071,6 +100143,9 @@ RF: Writing 00000002 to  5
 ******
 (8000031c) 0000000d * 0000000b = 0000008f
 (8000031c) 0000000d * 0000000b = 0000008f
+(8000031c) 0000000d * 0000000b = 0000008f
+(8000031c) 0000000d * 0000000b = 0000008f
+(8000031c) 0000000d * 0000000b = 0000008f
 ----
 ******
 [80000314] WB Data: 0000000d {babebabe}, to register:  1 [1 0]
@@ -100166,6 +100241,9 @@ RF: Writing 00000000 to  4
 RF: Writing 0000000e to  1
 (80000348) 0000000e * 0000000b = 0000009a
 (80000348) 0000000e * 0000000b = 0000009a
+(80000348) 0000000e * 0000000b = 0000009a
+(80000348) 0000000e * 0000000b = 0000009a
+(80000348) 0000000e * 0000000b = 0000009a
 ----
 ******
 [80000340] WB Data: 0000000b {babebabe}, to register:  2 [1 0]
@@ -100224,6 +100302,9 @@ RF: Writing 00000002 to  5
 RF: Writing 0000000e to  1
 (80000348) 0000000e * 0000000b = 0000009a
 (80000348) 0000000e * 0000000b = 0000009a
+(80000348) 0000000e * 0000000b = 0000009a
+(80000348) 0000000e * 0000000b = 0000009a
+(80000348) 0000000e * 0000000b = 0000009a
 ----
 ******
 [80000340] WB Data: 0000000b {babebabe}, to register:  2 [1 0]
@@ -100325,6 +100406,9 @@ RF: Writing 0000000f to  1
 RF: Writing 0000000b to  2
 (80000378) 0000000f * 0000000b = 000000a5
 (80000378) 00000000 * 0000000b = 00000000
+(80000378) 00000000 * 0000000b = 00000000
+(80000378) 00000000 * 0000000b = 00000000
+(80000378) 00000000 * 0000000b = 00000000
 ----
 ******
 [80000370] WB Data: 00000000 {babebabe}, to register:  0 [1 0]
@@ -100389,6 +100473,9 @@ RF: Writing 0000000f to  1
 RF: Writing 0000000b to  2
 (80000378) 0000000f * 0000000b = 000000a5
 (80000378) 00000000 * 0000000b = 00000000
+(80000378) 00000000 * 0000000b = 00000000
+(80000378) 00000000 * 0000000b = 00000000
+(80000378) 00000000 * 0000000b = 00000000
 ----
 ******
 [80000370] WB Data: 00000000 {babebabe}, to register:  0 [1 0]
@@ -100482,6 +100569,9 @@ RF: Writing 00000000 to  4
 RF: Writing 0000000d to  1
 (800003a4) 0000000d * 0000000b = 0000008f
 (800003a4) 0000000d * 0000000b = 0000008f
+(800003a4) 0000000d * 0000000b = 0000008f
+(800003a4) 0000000d * 0000000b = 0000008f
+(800003a4) 0000000d * 0000000b = 0000008f
 ----
 ******
 [8000039c] WB Data: 00000000 {babebabe}, to register:  0 [1 0]
@@ -100540,6 +100630,9 @@ RF: Writing 00000002 to  5
 RF: Writing 0000000d to  1
 (800003a4) 0000000d * 0000000b = 0000008f
 (800003a4) 0000000d * 0000000b = 0000008f
+(800003a4) 0000000d * 0000000b = 0000008f
+(800003a4) 0000000d * 0000000b = 0000008f
+(800003a4) 0000000d * 0000000b = 0000008f
 ----
 ******
 [8000039c] WB Data: 00000000 {babebabe}, to register:  0 [1 0]
@@ -100640,6 +100733,9 @@ RF: Writing 0000000e to  1
 ******
 (800003d4) 0000000e * 0000000b = 0000009a
 (800003d4) 00000000 * 0000000b = 00000000
+(800003d4) 00000000 * 0000000b = 00000000
+(800003d4) 00000000 * 0000000b = 00000000
+(800003d4) 00000000 * 0000000b = 00000000
 ----
 ******
 [800003cc] WB Data: 0000000b {babebabe}, to register:  2 [1 0]
@@ -100704,6 +100800,9 @@ RF: Writing 0000000e to  1
 ******
 (800003d4) 0000000e * 0000000b = 0000009a
 (800003d4) 00000000 * 0000000b = 00000000
+(800003d4) 00000000 * 0000000b = 00000000
+(800003d4) 00000000 * 0000000b = 00000000
+(800003d4) 00000000 * 0000000b = 00000000
 ----
 ******
 [800003cc] WB Data: 0000000b {babebabe}, to register:  2 [1 0]
@@ -100804,6 +100903,9 @@ RF: Writing 0000000f to  1
 ******
 (80000404) 0000000f * 0000000b = 000000a5
 (80000404) 00000000 * 0000000b = 00000000
+(80000404) 00000000 * 0000000b = 00000000
+(80000404) 00000000 * 0000000b = 00000000
+(80000404) 00000000 * 0000000b = 00000000
 ----
 ******
 [800003fc] WB Data: 00000000 {babebabe}, to register:  0 [1 0]
@@ -100868,6 +100970,9 @@ RF: Writing 0000000f to  1
 ******
 (80000404) 0000000f * 0000000b = 000000a5
 (80000404) 00000000 * 0000000b = 00000000
+(80000404) 00000000 * 0000000b = 00000000
+(80000404) 00000000 * 0000000b = 00000000
+(80000404) 00000000 * 0000000b = 00000000
 ----
 ******
 [800003fc] WB Data: 00000000 {babebabe}, to register:  0 [1 0]
@@ -100955,6 +101060,9 @@ RF: Writing 00000013 to 28
 RF: Writing 00000000 to  4
 (8000042c) 0000000d * 0000000b = 0000008f
 (8000042c) 0000000d * 0000000b = 0000008f
+(8000042c) 0000000d * 0000000b = 0000008f
+(8000042c) 0000000d * 0000000b = 0000008f
+(8000042c) 0000000d * 0000000b = 0000008f
 ----
 ******
 [80000424] WB Data: 0000000b {babebabe}, to register:  2 [1 0]
@@ -101007,6 +101115,9 @@ RF: Writing 00000002 to  5
 ******
 (8000042c) 0000000d * 0000000b = 0000008f
 (8000042c) 0000000d * 0000000b = 0000008f
+(8000042c) 0000000d * 0000000b = 0000008f
+(8000042c) 0000000d * 0000000b = 0000008f
+(8000042c) 0000000d * 0000000b = 0000008f
 ----
 ******
 [80000424] WB Data: 0000000b {babebabe}, to register:  2 [1 0]
@@ -101102,6 +101213,9 @@ RF: Writing 00000000 to  4
 RF: Writing 0000000b to  2
 (80000458) 0000000e * 0000000b = 0000009a
 (80000458) 0000000e * 0000000b = 0000009a
+(80000458) 0000000e * 0000000b = 0000009a
+(80000458) 0000000e * 0000000b = 0000009a
+(80000458) 0000000e * 0000000b = 0000009a
 ----
 ******
 [80000450] WB Data: 0000000e {babebabe}, to register:  1 [1 0]
@@ -101160,6 +101274,9 @@ RF: Writing 00000002 to  5
 RF: Writing 0000000b to  2
 (80000458) 0000000e * 0000000b = 0000009a
 (80000458) 0000000e * 0000000b = 0000009a
+(80000458) 0000000e * 0000000b = 0000009a
+(80000458) 0000000e * 0000000b = 0000009a
+(80000458) 0000000e * 0000000b = 0000009a
 ----
 ******
 [80000450] WB Data: 0000000e {babebabe}, to register:  1 [1 0]
@@ -101261,6 +101378,9 @@ RF: Writing 0000000b to  2
 RF: Writing 0000000f to  1
 (80000488) 0000000f * 0000000b = 000000a5
 (80000488) 0000000f * 00000000 = 00000000
+(80000488) 0000000f * 00000000 = 00000000
+(80000488) 0000000f * 00000000 = 00000000
+(80000488) 0000000f * 00000000 = 00000000
 ----
 ******
 [80000480] WB Data: 00000000 {babebabe}, to register:  0 [1 0]
@@ -101325,6 +101445,9 @@ RF: Writing 0000000b to  2
 RF: Writing 0000000f to  1
 (80000488) 0000000f * 0000000b = 000000a5
 (80000488) 0000000f * 00000000 = 00000000
+(80000488) 0000000f * 00000000 = 00000000
+(80000488) 0000000f * 00000000 = 00000000
+(80000488) 0000000f * 00000000 = 00000000
 ----
 ******
 [80000480] WB Data: 00000000 {babebabe}, to register:  0 [1 0]
@@ -101418,6 +101541,9 @@ RF: Writing 00000000 to  4
 RF: Writing 0000000b to  2
 (800004b4) 0000000d * 0000000b = 0000008f
 (800004b4) 0000000d * 0000000b = 0000008f
+(800004b4) 0000000d * 0000000b = 0000008f
+(800004b4) 0000000d * 0000000b = 0000008f
+(800004b4) 0000000d * 0000000b = 0000008f
 ----
 ******
 [800004ac] WB Data: 00000000 {babebabe}, to register:  0 [1 0]
@@ -101476,6 +101602,9 @@ RF: Writing 00000002 to  5
 RF: Writing 0000000b to  2
 (800004b4) 0000000d * 0000000b = 0000008f
 (800004b4) 0000000d * 0000000b = 0000008f
+(800004b4) 0000000d * 0000000b = 0000008f
+(800004b4) 0000000d * 0000000b = 0000008f
+(800004b4) 0000000d * 0000000b = 0000008f
 ----
 ******
 [800004ac] WB Data: 00000000 {babebabe}, to register:  0 [1 0]
@@ -101576,6 +101705,9 @@ RF: Writing 0000000b to  2
 ******
 (800004e4) 0000000e * 0000000b = 0000009a
 (800004e4) 0000000e * 00000000 = 00000000
+(800004e4) 0000000e * 00000000 = 00000000
+(800004e4) 0000000e * 00000000 = 00000000
+(800004e4) 0000000e * 00000000 = 00000000
 ----
 ******
 [800004dc] WB Data: 0000000e {babebabe}, to register:  1 [1 0]
@@ -101640,6 +101772,9 @@ RF: Writing 0000000b to  2
 ******
 (800004e4) 0000000e * 0000000b = 0000009a
 (800004e4) 0000000e * 00000000 = 00000000
+(800004e4) 0000000e * 00000000 = 00000000
+(800004e4) 0000000e * 00000000 = 00000000
+(800004e4) 0000000e * 00000000 = 00000000
 ----
 ******
 [800004dc] WB Data: 0000000e {babebabe}, to register:  1 [1 0]
@@ -101740,6 +101875,9 @@ RF: Writing 0000000b to  2
 ******
 (80000514) 0000000f * 0000000b = 000000a5
 (80000514) 0000000f * 00000000 = 00000000
+(80000514) 0000000f * 00000000 = 00000000
+(80000514) 0000000f * 00000000 = 00000000
+(80000514) 0000000f * 00000000 = 00000000
 ----
 ******
 [8000050c] WB Data: 00000000 {babebabe}, to register:  0 [1 0]
@@ -101804,6 +101942,9 @@ RF: Writing 0000000b to  2
 ******
 (80000514) 0000000f * 0000000b = 000000a5
 (80000514) 0000000f * 00000000 = 00000000
+(80000514) 0000000f * 00000000 = 00000000
+(80000514) 0000000f * 00000000 = 00000000
+(80000514) 0000000f * 00000000 = 00000000
 ----
 ******
 [8000050c] WB Data: 00000000 {babebabe}, to register:  0 [1 0]
@@ -101879,6 +102020,9 @@ RF: Writing 00000019 to 28
 ******
 (80000534) 00000000 * 0000001f = 00000000
 (80000534) 00000000 * 0000001f = 00000000
+(80000534) 00000000 * 0000001f = 00000000
+(80000534) 00000000 * 0000001f = 00000000
+(80000534) 00000000 * 0000001f = 00000000
 ----
 ******
 
@@ -101924,6 +102068,9 @@ RF: Writing 0000001a to 28
 ******
 (80000548) 00000020 * 00000000 = 00000000
 (80000548) 00000020 * 00000000 = 00000000
+(80000548) 00000020 * 00000000 = 00000000
+(80000548) 00000020 * 00000000 = 00000000
+(80000548) 00000020 * 00000000 = 00000000
 ----
 ******
 
@@ -101964,6 +102111,9 @@ RF: Writing 0000001b to 28
 ******
 (80000558) 00000000 * 00000000 = 00000000
 (80000558) 00000000 * 00000000 = 00000000
+(80000558) 00000000 * 00000000 = 00000000
+(80000558) 00000000 * 00000000 = 00000000
+(80000558) 00000000 * 00000000 = 00000000
 ----
 ******
 
@@ -102012,6 +102162,9 @@ RF: Writing 0000001c to 28
 ******
 (80000570) 00000021 * 00000022 = 00000462
 (80000570) 00000021 * 00000022 = 00000462
+(80000570) 00000021 * 00000022 = 00000462
+(80000570) 00000021 * 00000022 = 00000462
+(80000570) 00000021 * 00000022 = 00000462
 ----
 ******
 [80000568] WB Data: 00000021 {babebabe}, to register:  1 [1 0]
diff --git a/rtl/obj_dir/test_bench.o b/rtl/obj_dir/test_bench.o
index a5d3fdc1..0a3a181b 100644
Binary files a/rtl/obj_dir/test_bench.o and b/rtl/obj_dir/test_bench.o differ