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performance refactoring - rebalanced stream buffers accross the device to enforce output buffering rule at compoments boudaries, finally resolved block ram R/W collusion discrepencies,

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This commit is contained in:
Blaise Tine
2020-12-19 02:45:06 -08:00
parent 29cd2f5dff
commit 4bbd7bf408
76 changed files with 1313 additions and 1098 deletions
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20
hw/rtl/afu/VX_avs_wrapper.v
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@@ -59,20 +59,25 @@ module VX_avs_wrapper #(
+ RD_QUEUE_ADDRW'((avs_reqq_push && !avs_rspq_pop) ? 1 :
(avs_rspq_pop && !avs_reqq_push) ? -1 : 0);
reg rsp_queue_ready;
always @(posedge clk) begin
if (reset) begin
avs_burstcount_r <= 1;
avs_bankselect_r <= 0;
avs_pending_reads <= 0;
rsp_queue_ready <= 1;
end else begin
avs_pending_reads <= avs_pending_reads_n;
rsp_queue_ready <= (avs_pending_reads_n != RD_QUEUE_SIZE);
end
end
VX_generic_queue #(
.DATAW (REQ_TAGW),
.SIZE (RD_QUEUE_SIZE),
.BUFFERED (1)
.DATAW (REQ_TAGW),
.SIZE (RD_QUEUE_SIZE),
.BUFFERED(1),
.FASTRAM (1)
) rd_req_queue (
.clk (clk),
.reset (reset),
@@ -86,9 +91,10 @@ module VX_avs_wrapper #(
);
VX_generic_queue #(
.DATAW (AVS_DATAW),
.SIZE (RD_QUEUE_SIZE),
.BUFFERED (1)
.DATAW (AVS_DATAW),
.SIZE (RD_QUEUE_SIZE),
.BUFFERED(1),
.FASTRAM (1)
) rd_rsp_queue (
.clk (clk),
.reset (reset),
@@ -101,8 +107,6 @@ module VX_avs_wrapper #(
`UNUSED_PIN (size)
);
wire rsp_queue_ready = (avs_pending_reads != RD_QUEUE_SIZE);
assign avs_read = dram_req_valid && !dram_req_rw && rsp_queue_ready;
assign avs_write = dram_req_valid && dram_req_rw && rsp_queue_ready;
assign avs_address = dram_req_addr;

11
hw/rtl/afu/vortex_afu.sv
View File

@@ -700,8 +700,8 @@ always @(posedge clk) begin
end
cci_rd_req_enable <= (STATE_WRITE == state)
&& (cci_rd_req_ctr_next < cmd_data_size)
&& (cci_pending_reads_next < CCI_RD_QUEUE_SIZE)
&& (cci_rd_req_ctr_next != cmd_data_size)
&& (cci_pending_reads_next != CCI_RD_QUEUE_SIZE)
&& !cp2af_sRxPort.c0TxAlmFull;
if (cci_rd_req_fire) begin
@@ -741,8 +741,9 @@ always @(posedge clk) begin
end
VX_generic_queue #(
.DATAW(CCI_RD_RQ_DATAW),
.SIZE(CCI_RD_QUEUE_SIZE)
.DATAW (CCI_RD_RQ_DATAW),
.SIZE (CCI_RD_QUEUE_SIZE),
.FASTRAM (1)
) cci_rd_req_queue (
.clk (clk),
.reset (reset),
@@ -898,7 +899,7 @@ always @(posedge clk) begin
end
if ((STATE_CLFLUSH == state)
&& (snp_req_ctr_next >= snp_req_size)) begin
&& (snp_req_ctr_next == snp_req_size)) begin
vx_snp_req_valid <= 0;
end