performance refactoring - rebalanced stream buffers accross the device to enforce output buffering rule at compoments boudaries, finally resolved block ram R/W collusion discrepencies,

2020-12-19 02:45:06 -08:00
parent 29cd2f5dff
commit 4bbd7bf408
76 changed files with 1313 additions and 1098 deletions
--- a/hw/rtl/interfaces/VX_csr_req_if.v
+++ b/hw/rtl/interfaces/VX_csr_req_if.v
@@ -6,7 +6,6 @@
 interface VX_csr_req_if ();

    wire                    valid;
-
    wire [`NW_BITS-1:0]     wid;
    wire [`NUM_THREADS-1:0] tmask;
    wire [31:0]             PC;
@@ -16,8 +15,7 @@ interface VX_csr_req_if ();
    wire                    rs2_is_imm;
    wire [`NR_BITS-1:0]     rs1;
    wire [`NR_BITS-1:0]     rd;
-    wire                    wb;
-    
+    wire                    wb;    
    wire                    ready;
    
 endinterface