fixed rtlsim regression

2020-10-26 12:59:58 -04:00
parent d319ae3b97
commit 4bd5ee2673
2 changed files with 8 additions and 8 deletions
--- a/driver/rtlsim/Makefile
+++ b/driver/rtlsim/Makefile
@@ -55,7 +55,7 @@ VL_FLAGS += verilator.vlt

 # Debugigng
 ifdef DEBUG
-	VL_FLAGS += -DVCD_OUTPUT --assert --trace $(DBG_FLAGS)
+	VL_FLAGS += -DVCD_OUTPUT --assert --trace-fst --trace-threads 1 $(DBG_FLAGS)
 	CFLAGS   += -DVCD_OUTPUT $(DBG_FLAGS)
 else    
 	VL_FLAGS += -DNDEBUG