pipeline refactoring
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@@ -16,7 +16,7 @@ module VX_lsu_unit #(
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VX_lsu_req_if lsu_req_if,
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// outputs
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VX_wb_if lsu_wb_if
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VX_commit_if lsu_commit_if
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);
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wire [`NUM_THREADS-1:0] use_valid;
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@@ -108,7 +108,7 @@ module VX_lsu_unit #(
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.full (mrq_full),
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.pop (mrq_pop),
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.read_addr (mrq_read_addr),
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.read_data ({dbg_mrq_write_addr, lsu_wb_if.curr_PC, lsu_wb_if.wb, mem_rsp_offset, core_rsp_mem_read, lsu_wb_if.rd, lsu_wb_if.warp_num}),
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.read_data ({dbg_mrq_write_addr, lsu_commit_if.curr_PC, lsu_commit_if.wb, mem_rsp_offset, core_rsp_mem_read, lsu_commit_if.rd, lsu_commit_if.warp_num}),
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`UNUSED_PIN (empty)
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);
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@@ -151,11 +151,11 @@ module VX_lsu_unit #(
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end
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end
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assign lsu_wb_if.valid = dcache_rsp_if.valid;
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assign lsu_wb_if.data = core_rsp_data;
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assign lsu_commit_if.valid = dcache_rsp_if.valid;
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assign lsu_commit_if.data = core_rsp_data;
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// Can accept new cache response
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assign dcache_rsp_if.ready = lsu_wb_if.ready;
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assign dcache_rsp_if.ready = lsu_commit_if.ready;
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`SCOPE_ASSIGN(scope_dcache_req_valid, dcache_req_if.valid);
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`SCOPE_ASSIGN(scope_dcache_req_warp_num, use_warp_num);
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@@ -180,7 +180,7 @@ module VX_lsu_unit #(
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end
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if ((| dcache_rsp_if.valid) && dcache_rsp_if.ready) begin
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$display("%t: D$%0d rsp: valid=%b, warp=%0d, PC=%0h, tag=%0h, rd=%0d, data=%0h",
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$time, CORE_ID, lsu_wb_if.valid, lsu_wb_if.warp_num, lsu_wb_if.curr_PC, mrq_read_addr, lsu_wb_if.rd, lsu_wb_if.data);
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$time, CORE_ID, lsu_commit_if.valid, lsu_commit_if.warp_num, lsu_commit_if.curr_PC, mrq_read_addr, lsu_commit_if.rd, lsu_commit_if.data);
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end
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end
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`endif
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