From 5798cf6e15330b687048251374830fe320acb4cf Mon Sep 17 00:00:00 2001 From: Blaise Tine Date: Tue, 21 Apr 2020 07:13:56 -0700 Subject: [PATCH] RTL refactoring --- hw/opae/README | 9 ++++++++- hw/opae/sources.txt | 2 +- hw/rtl/VX_alu.v | 2 +- hw/rtl/VX_back_end.v | 4 ++-- hw/rtl/VX_front_end.v | 30 +++++++++++++++--------------- hw/rtl/{VX_lsu.v => VX_lsu_unit.v} | 0 hw/rtl/Vortex.v | 24 ++++++++++++------------ 7 files changed, 39 insertions(+), 32 deletions(-) rename hw/rtl/{VX_lsu.v => VX_lsu_unit.v} (100%) diff --git a/hw/opae/README b/hw/opae/README index 0d673a8c..18baa83b 100644 --- a/hw/opae/README +++ b/hw/opae/README @@ -36,4 +36,11 @@ export LD_LIBRARY_PATH=${PWD}:$LD_LIBRARY_PATH cd /driver/tests/basic make clean make -./basic \ No newline at end of file +./basic + + +ASE build instructions + +vcd file vortex.vcd +vcd add -r /*/Vortex/hw/rtl/* +run -all \ No newline at end of file diff --git a/hw/opae/sources.txt b/hw/opae/sources.txt index fc16d66c..f6433ca7 100644 --- a/hw/opae/sources.txt +++ b/hw/opae/sources.txt @@ -70,7 +70,7 @@ vortex_afu.json ../rtl/VX_gpr.v ../rtl/VX_gpr_stage.v ../rtl/VX_dmem_ctrl.v -../rtl/VX_alu.v +../rtl/VX_alu_unit.v ../rtl/VX_csr_data.v ../rtl/VX_lsu.v ../rtl/VX_decode.v diff --git a/hw/rtl/VX_alu.v b/hw/rtl/VX_alu.v index d36bc0b5..2dc59a6d 100644 --- a/hw/rtl/VX_alu.v +++ b/hw/rtl/VX_alu.v @@ -1,6 +1,6 @@ `include "VX_define.vh" -module VX_alu ( +module VX_alu_unit ( input wire clk, input wire reset, input wire[31:0] src_a, diff --git a/hw/rtl/VX_back_end.v b/hw/rtl/VX_back_end.v index ba32cfd4..07edc90d 100644 --- a/hw/rtl/VX_back_end.v +++ b/hw/rtl/VX_back_end.v @@ -70,7 +70,7 @@ VX_gpr_stage gpr_stage ( .gpr_stage_delay (gpr_stage_delay) ); -VX_lsu load_store_unit ( +VX_lsu_unit lsu_unit ( .clk (clk), .reset (reset), .lsu_req_if (lsu_req_if), @@ -109,7 +109,7 @@ VX_csr_pipe #( .stall_gpr_csr(stall_gpr_csr) ); -VX_writeback wb ( +VX_writeback writeback ( .clk (clk), .reset (reset), .mem_wb_if (mem_wb_if), diff --git a/hw/rtl/VX_front_end.v b/hw/rtl/VX_front_end.v index ca5a19f4..8e5720ab 100644 --- a/hw/rtl/VX_front_end.v +++ b/hw/rtl/VX_front_end.v @@ -37,8 +37,8 @@ module VX_front_end ( assign fetch_ebreak = vortex_ebreak || terminate_sim; - VX_wstall_if wstall_if(); - VX_join_if join_if(); + VX_wstall_if wstall_if(); + VX_join_if join_if(); VX_fetch fetch( .clk (clk), @@ -59,11 +59,11 @@ module VX_front_end ( wire freeze_fi_reg = total_freeze || icache_stage_delay; VX_f_d_reg f_i_reg( - .clk (clk), - .reset (reset), - .freeze (freeze_fi_reg), - .fe_inst_meta_fd(fe_inst_meta_fi), - .fd_inst_meta_de(fe_inst_meta_fi2) + .clk (clk), + .reset (reset), + .freeze (freeze_fi_reg), + .fe_inst_meta_fd (fe_inst_meta_fi), + .fd_inst_meta_de (fe_inst_meta_fi2) ); VX_icache_stage icache_stage( @@ -88,11 +88,11 @@ module VX_front_end ( ); VX_decode decode( - .fd_inst_meta_de (fd_inst_meta_de), - .frE_to_bckE_req_if (frE_to_bckE_req_if), - .wstall_if (wstall_if), - .join_if (join_if), - .terminate_sim (terminate_sim) + .fd_inst_meta_de (fd_inst_meta_de), + .frE_to_bckE_req_if (frE_to_bckE_req_if), + .wstall_if (wstall_if), + .join_if (join_if), + .terminate_sim (terminate_sim) ); wire no_br_stall = 0; @@ -101,9 +101,9 @@ module VX_front_end ( .clk (clk), .reset (reset), .branch_stall (no_br_stall), - .freeze (total_freeze), - .frE_to_bckE_req_if (frE_to_bckE_req_if), - .bckE_req_if (bckE_req_if) + .freeze (total_freeze), + .frE_to_bckE_req_if (frE_to_bckE_req_if), + .bckE_req_if (bckE_req_if) ); endmodule diff --git a/hw/rtl/VX_lsu.v b/hw/rtl/VX_lsu_unit.v similarity index 100% rename from hw/rtl/VX_lsu.v rename to hw/rtl/VX_lsu_unit.v diff --git a/hw/rtl/Vortex.v b/hw/rtl/Vortex.v index b7e25408..bc96636f 100644 --- a/hw/rtl/Vortex.v +++ b/hw/rtl/Vortex.v @@ -147,28 +147,28 @@ assign gpu_dcache_snp_req_if.snp_req_addr = llc_snp_req_addr; assign llc_snp_req_ready = gpu_dcache_snp_req_if.snp_req_ready; VX_front_end front_end ( - .clk (clk), + .clk (clk), .reset (reset), .warp_ctl_if (warp_ctl_if), .bckE_req_if (bckE_req_if), .schedule_delay (schedule_delay), .icache_rsp_if (icache_rsp_if), .icache_req_if (icache_req_if), - .jal_rsp_if (jal_rsp_if), + .jal_rsp_if (jal_rsp_if), .branch_rsp_if (branch_rsp_if), .fetch_ebreak (ebreak) ); -VX_scheduler schedule ( +VX_scheduler scheduler ( .clk (clk), - .reset (reset), - .memory_delay (memory_delay), - .exec_delay (exec_delay), - .gpr_stage_delay (gpr_stage_delay), - .bckE_req_if (bckE_req_if), - .writeback_if (writeback_if), - .schedule_delay (schedule_delay), - .is_empty (scheduler_empty) + .reset (reset), + .memory_delay (memory_delay), + .exec_delay (exec_delay), + .gpr_stage_delay (gpr_stage_delay), + .bckE_req_if (bckE_req_if), + .writeback_if (writeback_if), + .schedule_delay (schedule_delay), + .is_empty (scheduler_empty) ); VX_back_end #( @@ -189,7 +189,7 @@ VX_back_end #( .gpr_stage_delay (gpr_stage_delay) ); -VX_dmem_ctrl dmem_controller ( +VX_dmem_ctrl dmem_ctrl ( .clk (clk), .reset (reset),