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scope fixes ...

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This commit is contained in:
Blaise Tine
2020-10-13 17:09:22 -04:00
parent 4bfc4ee78f
commit 58b8e82908
5 changed files with 79 additions and 76 deletions
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29
driver/opae/vx_scope.cpp
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@@ -44,10 +44,10 @@
static constexpr int num_modules = sizeof(scope_modules) / sizeof(scope_module_t); static constexpr int num_modules = sizeof(scope_modules) / sizeof(scope_module_t);
static constexpr int num_signals = sizeof(scope_taps) / sizeof(scope_tap_t); static constexpr int num_taps = sizeof(scope_taps) / sizeof(scope_tap_t);
constexpr int calcFrameWidth(int index = 0) { constexpr int calcFrameWidth(int index = 0) {
return (index < num_signals) ? (scope_taps[index].width + calcFrameWidth(index + 1)) : 0; return (index < num_taps) ? (scope_taps[index].width + calcFrameWidth(index + 1)) : 0;
} }
static constexpr int fwidth = calcFrameWidth(); static constexpr int fwidth = calcFrameWidth();
@@ -77,13 +77,12 @@ uint64_t print_clock(std::ofstream& ofs, uint64_t delta, uint64_t timestamp) {
return timestamp; return timestamp;
} }
void dump_taps(std::ofstream& ofs, int module) { void dump_taps(std::ofstream& ofs, int module) {
int i = 1; for (int i = 0; i < num_taps; ++i) {
for (auto& tap : scope_taps) { auto& tap = scope_taps[i];
if (tap.module != module) if (tap.module != module)
continue; continue;
ofs << "$var reg " << tap.width << " " << i << " " << tap.name << " $end" << std::endl; ofs << "$var reg " << tap.width << " " << (i + 1) << " " << tap.name << " $end" << std::endl;
i += 1;
} }
} }
@@ -91,10 +90,16 @@ void dump_module(std::ofstream& ofs, int parent) {
for (auto& module : scope_modules) { for (auto& module : scope_modules) {
if (module.parent != parent) if (module.parent != parent)
continue; continue;
ofs << "$scope module " << module.name << " $end" << std::endl; if (module.name[0] == '*') {
ofs << "$var reg 1 0 clk $end" << std::endl;
} else {
ofs << "$scope module " << module.name << " $end" << std::endl;
}
dump_module(ofs, module.index); dump_module(ofs, module.index);
dump_taps(ofs, module.index); dump_taps(ofs, module.index);
ofs << "$upscope $end" << std::endl; if (module.name[0] != '*') {
ofs << "$upscope $end" << std::endl;
}
} }
} }
@@ -138,7 +143,7 @@ int vx_scope_stop(fpga_handle hfpga, uint64_t delay) {
ofs << "$version Generated by Vortex Scope $end" << std::endl; ofs << "$version Generated by Vortex Scope $end" << std::endl;
ofs << "$timescale 1 ns $end" << std::endl; ofs << "$timescale 1 ns $end" << std::endl;
ofs << "$scope module TOP $end" << std::endl; ofs << "$scope module TOP $end" << std::endl;
ofs << "$var reg 1 0 clk $end" << std::endl;
dump_module(ofs, -1); dump_module(ofs, -1);
dump_taps(ofs, -1); dump_taps(ofs, -1);
ofs << "$upscope $end" << std::endl; ofs << "$upscope $end" << std::endl;
@@ -187,7 +192,7 @@ int vx_scope_stop(fpga_handle hfpga, uint64_t delay) {
// print clock header // print clock header
CHECK_RES(fpgaReadMMIO64(hfpga, 0, MMIO_SCOPE_READ, &delta)); CHECK_RES(fpgaReadMMIO64(hfpga, 0, MMIO_SCOPE_READ, &delta));
timestamp = print_clock(ofs, offset + delta + 2, timestamp); timestamp = print_clock(ofs, offset + delta + 2, timestamp);
signal_id = num_signals; signal_id = num_taps;
std::vector<char> signal_data(frame_width+1); std::vector<char> signal_data(frame_width+1);
@@ -229,7 +234,7 @@ int vx_scope_stop(fpga_handle hfpga, uint64_t delay) {
// print clock header // print clock header
CHECK_RES(fpgaReadMMIO64(hfpga, 0, MMIO_SCOPE_READ, &delta)); CHECK_RES(fpgaReadMMIO64(hfpga, 0, MMIO_SCOPE_READ, &delta));
timestamp = print_clock(ofs, delta + 1, timestamp); timestamp = print_clock(ofs, delta + 1, timestamp);
signal_id = num_signals; signal_id = num_taps;
if (0 == (frame_no % 100)) { if (0 == (frame_no % 100)) {
std::cout << "*** " << frame_no << " frames, timestamp=" << timestamp << std::endl; std::cout << "*** " << frame_no << " frames, timestamp=" << timestamp << std::endl;
} }

4
hw/opae/vortex_afu.sv
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@@ -954,7 +954,7 @@ end
assign cmd_run_done = !vx_busy; assign cmd_run_done = !vx_busy;
Vortex #() vortex ( Vortex #() vortex (
`SCOPE_BIND_vortex_afu_vortex `SCOPE_BIND_top_vortex
.clk (clk), .clk (clk),
.reset (reset | vx_reset), .reset (reset | vx_reset),
@@ -1066,7 +1066,7 @@ wire scope_changed = `SCOPE_TRIGGER;
VX_scope #( VX_scope #(
.DATAW ($bits({`SCOPE_DATA_LIST,`SCOPE_UPDATE_LIST})), .DATAW ($bits({`SCOPE_DATA_LIST,`SCOPE_UPDATE_LIST})),
.BUSW (64), .BUSW (64),
.SIZE (4096), .SIZE (100),
.UPDW ($bits({`SCOPE_UPDATE_LIST})) .UPDW ($bits({`SCOPE_UPDATE_LIST}))
) scope ( ) scope (
.clk (clk), .clk (clk),

4
hw/rtl/VX_scope.vh
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@@ -9,8 +9,6 @@
`else `else
`define SCOPE_IO_vortex_afu
`define SCOPE_IO_VX_icache_stage `define SCOPE_IO_VX_icache_stage
`define SCOPE_IO_VX_fetch `define SCOPE_IO_VX_fetch
@@ -37,7 +35,7 @@
`define SCOPE_BIND_Vortex_cluster(__i__) `define SCOPE_BIND_Vortex_cluster(__i__)
`define SCOPE_BIND_vortex_afu_vortex `define SCOPE_BIND_top_vortex
`define SCOPE_IO_VX_lsu_unit `define SCOPE_IO_VX_lsu_unit

24
hw/scripts/scope.json
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@@ -7,13 +7,7 @@
"../rtl/cache/VX_cache_config.vh" "../rtl/cache/VX_cache_config.vh"
], ],
"modules": { "modules": {
"*": { "top": {
"enabled": "(`NUM_CLUSTERS > 0)",
"submodules": {
"afu": {"type":"vortex_afu"}
}
},
"vortex_afu": {
"submodules": { "submodules": {
"vortex": {"type":"Vortex"} "vortex": {"type":"Vortex"}
} }
@@ -26,7 +20,7 @@
}, },
"VX_cluster": { "VX_cluster": {
"submodules": { "submodules": {
"core": {"type":"VX_core", "count":"`NUM_CORES"}, "core": {"type":"VX_core", "count":"`NUM_CORES", "enabled":true},
"l2cache": {"type":"VX_cache", "enabled":"`L2_ENABLE", "params":{"NUM_BANKS":"`L2NUM_BANKS"}} "l2cache": {"type":"VX_cache", "enabled":"`L2_ENABLE", "params":{"NUM_BANKS":"`L2NUM_BANKS"}}
} }
}, },
@@ -79,7 +73,7 @@
"VX_bank": {} "VX_bank": {}
}, },
"taps": { "taps": {
"afu": { "top": {
"!reset": 1, "!reset": 1,
"?dram_req_valid": 1, "?dram_req_valid": 1,
"dram_req_addr": 32, "dram_req_addr": 32,
@@ -102,7 +96,7 @@
"?snp_rsp_ready": 1, "?snp_rsp_ready": 1,
"busy": 1 "busy": 1
}, },
"afu/vortex/cluster/core/pipeline/fetch/icache_stage": { "top/vortex/cluster/core/pipeline/fetch/icache_stage": {
"?icache_req_valid": 1, "?icache_req_valid": 1,
"icache_req_wid":"`NW_BITS", "icache_req_wid":"`NW_BITS",
"icache_req_addr": 32, "icache_req_addr": 32,
@@ -113,7 +107,7 @@
"icache_rsp_tag":"`ICORE_TAG_ID_BITS", "icache_rsp_tag":"`ICORE_TAG_ID_BITS",
"?icache_rsp_ready": 1 "?icache_rsp_ready": 1
}, },
"afu/vortex/cluster/core/pipeline/fetch/warp_sched": { "top/vortex/cluster/core/pipeline/fetch/warp_sched": {
"?wsched_scheduled_warp": 1, "?wsched_scheduled_warp": 1,
"wsched_active_warps": "`NUM_WARPS", "wsched_active_warps": "`NUM_WARPS",
"wsched_schedule_table": "`NUM_WARPS", "wsched_schedule_table": "`NUM_WARPS",
@@ -121,7 +115,7 @@
"wsched_warp_to_schedule": "`NW_BITS", "wsched_warp_to_schedule": "`NW_BITS",
"wsched_warp_pc": "32" "wsched_warp_pc": "32"
}, },
"afu/vortex/cluster/core/pipeline/execute/gpu_unit": { "top/vortex/cluster/core/pipeline/execute/gpu_unit": {
"?gpu_req_valid": 1, "?gpu_req_valid": 1,
"gpu_req_wid": "`NW_BITS", "gpu_req_wid": "`NW_BITS",
"gpu_req_tmask": "`NUM_THREADS", "gpu_req_tmask": "`NUM_THREADS",
@@ -136,7 +130,7 @@
"gpu_rsp_split": "`GPU_SPLIT_SIZE", "gpu_rsp_split": "`GPU_SPLIT_SIZE",
"gpu_rsp_barrier": "`GPU_BARRIER_SIZE" "gpu_rsp_barrier": "`GPU_BARRIER_SIZE"
}, },
"afu/vortex/cluster/core/pipeline/execute/lsu_unit": { "top/vortex/cluster/core/pipeline/execute/lsu_unit": {
"?dcache_req_valid":"`NUM_THREADS", "?dcache_req_valid":"`NUM_THREADS",
"dcache_req_wid":"`NW_BITS", "dcache_req_wid":"`NW_BITS",
"dcache_req_pc": 32, "dcache_req_pc": 32,
@@ -151,7 +145,7 @@
"dcache_rsp_tag":"`DCORE_TAG_ID_BITS", "dcache_rsp_tag":"`DCORE_TAG_ID_BITS",
"?dcache_rsp_ready": 1 "?dcache_rsp_ready": 1
}, },
"afu/vortex/cluster/core/pipeline/issue": { "top/vortex/cluster/core/pipeline/issue": {
"?issue_valid": 1, "?issue_valid": 1,
"issue_wid":"`NW_BITS", "issue_wid":"`NW_BITS",
"issue_tmask":"`NUM_THREADS", "issue_tmask":"`NUM_THREADS",
@@ -183,7 +177,7 @@
"!scoreboard_delay": 1, "!scoreboard_delay": 1,
"!execute_delay": 1 "!execute_delay": 1
}, },
"afu/vortex/l3cache/bank, afu/vortex/cluster/l2cache/bank, afu/vortex/cluster/core/mem_unit/dcache/bank, afu/vortex/cluster/core/mem_unit/icache/bank, afu/vortex/cluster/core/mem_unit/smem/bank": { "top/vortex/l3cache/bank, top/vortex/cluster/l2cache/bank, top/vortex/cluster/core/mem_unit/dcache/bank, top/vortex/cluster/core/mem_unit/icache/bank, top/vortex/cluster/core/mem_unit/smem/bank": {
"?valid_st0": 1, "?valid_st0": 1,
"?valid_st1": 1, "?valid_st1": 1,
"?valid_st2": 1, "?valid_st2": 1,

94
hw/scripts/scope.py
View File

@@ -465,23 +465,24 @@ def gen_vl_header(file, modules, taps):
return arr return arr
def visit_path(alltaps, ports, path, node, paths, modules, taps): def visit_path(alltaps, ports, ntype, paths, modules, taps):
ntype = node["type"]
enabled = True
if "enabled" in node:
enabled = eval_node(node["enabled"], None)
curtaps = {} curtaps = {}
if (len(paths) != 0): if (len(paths) != 0):
spath = paths.pop(0) spath = paths.pop(0)
snodes = modules[ntype]["submodules"] snodes = modules[ntype]["submodules"]
if not spath in snodes: if not spath in snodes:
raise Exception("invalid path: " + spath + " in " + path) raise Exception("invalid path: " + spath + " in " + ntype)
snode = snodes[spath] snode = snodes[spath]
subtaps = visit_path(alltaps, ports, spath, snode, paths, modules, taps) stype = snode["type"]
enabled = True
if "enabled" in snode:
enabled = eval_node(snode["enabled"], None)
subtaps = visit_path(alltaps, ports, stype, paths, modules, taps)
scount = 0 scount = 0
if "count" in snode: if "count" in snode:
@@ -495,20 +496,12 @@ def gen_vl_header(file, modules, taps):
nn = "SCOPE_IO_" + ntype nn = "SCOPE_IO_" + ntype
pp = create_signal(nn, ports) pp = create_signal(nn, ports)
for key in subtaps: for key in subtaps:
subtap = subtaps[key] subtap = subtaps[key]
s = subtap[0] s = subtap[0]
a = subtap[1] a = subtap[1]
t = subtap[2] t = subtap[2]
e = subtap[3]
s = eval_node(s, params)
e = eval_node(e, params)
if type(e) == str or type(enabled) == str:
me = str(e) + " and " + str(enabled)
else:
me = e and enabled
aa = [scount] aa = [scount]
sa = signal_size(scount, 0) sa = signal_size(scount, 0)
@@ -518,9 +511,9 @@ def gen_vl_header(file, modules, taps):
aa.append(x) aa.append(x)
sa += signal_size(x, 0) sa += signal_size(x, 0)
if dic_insert(alltaps, curtaps, spath + '/' + key, (s, aa, t, me), e): if dic_insert(alltaps, curtaps, spath + '/' + key, (s, aa, t), enabled):
skey = key.replace('/', '_') skey = key.replace('/', '_')
if e: if enabled:
pp.append("\toutput wire" + sa + signal_size(s, 1) + " scope_" + spath + '_' + skey + ',') pp.append("\toutput wire" + sa + signal_size(s, 1) + " scope_" + spath + '_' + skey + ',')
new_staps.append(skey) new_staps.append(skey)
@@ -529,24 +522,29 @@ def gen_vl_header(file, modules, taps):
if (0 == scount): if (0 == scount):
nn = "SCOPE_BIND_" + ntype + '_' + spath nn = "SCOPE_BIND_" + ntype + '_' + spath
pp = create_signal(nn, ports) pp = create_signal(nn, ports)
for st in new_staps: for st in new_staps:
if e: if enabled:
pp.append("\t.scope_" + st + "(scope_" + spath + '_' + st + "),") pp.append("\t.scope_" + st + "(scope_" + spath + '_' + st + "),")
else: else:
pp.append("\t`UNUSED_PIN (scope_" + st + "),") pp.append("\t`UNUSED_PIN (scope_" + st + "),")
ports[nn] = pp ports[nn] = pp
else: else:
nn = "SCOPE_BIND_" + ntype + '_' + spath + "(__i__)" nn = "SCOPE_BIND_" + ntype + '_' + spath + "(__i__)"
pp = create_signal(nn, ports) pp = create_signal(nn, ports)
for st in new_staps: for st in new_staps:
if e: if enabled:
pp.append("\t.scope_" + st + "(scope_" + spath + '_' + st + "[__i__]),") pp.append("\t.scope_" + st + "(scope_" + spath + '_' + st + "[__i__]),")
else: else:
pp.append("\t`UNUSED_PIN (scope_" + st + "),") pp.append("\t`UNUSED_PIN (scope_" + st + "),")
ports[nn] = pp ports[nn] = pp
else: else:
nn = "SCOPE_IO_" + ntype nn = "SCOPE_IO_" + ntype
pp = create_signal(nn, ports) pp = create_signal(nn, ports)
for tk in taps: for tk in taps:
trigger = 0 trigger = 0
name = tk name = tk
@@ -557,7 +555,7 @@ def gen_vl_header(file, modules, taps):
elif name[0] == '?': elif name[0] == '?':
name = name[1:] name = name[1:]
trigger = 2 trigger = 2
if dic_insert(alltaps, curtaps, name, (size, None, trigger, enabled), True): if dic_insert(alltaps, curtaps, name, (size, None, trigger), True):
pp.append("\toutput wire" + signal_size(size, 1) + " scope_" + name + ',') pp.append("\toutput wire" + signal_size(size, 1) + " scope_" + name + ',')
ports[nn] = pp ports[nn] = pp
@@ -568,9 +566,6 @@ def gen_vl_header(file, modules, taps):
with open(file, 'w') as f: with open(file, 'w') as f:
top = modules['*']
snodes = top["submodules"]
ports = {} ports = {}
alltaps = {} alltaps = {}
@@ -580,11 +575,8 @@ def gen_vl_header(file, modules, taps):
for skey in skey_list: for skey in skey_list:
print('processing node: ' + skey + ' ...') print('processing node: ' + skey + ' ...')
paths = skey.strip().split('/') paths = skey.strip().split('/')
spath = paths.pop(0) ntype = paths.pop(0)
if not spath in snodes: curtaps = visit_path(alltaps, ports, ntype, paths, modules, _taps)
raise Exception("invalid path: " + spath)
snode = snodes[spath]
curtaps = visit_path(alltaps, ports, spath, snode, paths, modules, _taps)
for tk in curtaps: for tk in curtaps:
toptaps[tk] = curtaps[tk] toptaps[tk] = curtaps[tk]
@@ -603,19 +595,13 @@ def gen_vl_header(file, modules, taps):
name = key.replace('/', '_') name = key.replace('/', '_')
size = tap[0] size = tap[0]
asize = tap[1] asize = tap[1]
enabled = tap[3]
sa = "" sa = ""
if asize: if asize:
for a in asize: for a in asize:
sa += signal_size(a, 0) sa += signal_size(a, 0)
if i > 0: if i > 0:
print(" \\", file=f) print(" \\", file=f)
if not enabled: print('\t wire' + sa + signal_size(size, 1) + " scope_" + name + ';', file=f, end='')
print("`IGNORE_WARNINGS_BEGIN \\", file=f)
print('\t wire' + sa + signal_size(size, 1) + " scope_" + name + '; \\', file=f)
print("`IGNORE_WARNINGS_END", file=f, end='')
else:
print('\t wire' + sa + signal_size(size, 1) + " scope_" + name + ';', file=f, end='')
i += 1 i += 1
print("", file=f) print("", file=f)
print("", file=f) print("", file=f)
@@ -624,7 +610,8 @@ def gen_vl_header(file, modules, taps):
i = 0 i = 0
for key in toptaps: for key in toptaps:
tap = toptaps[key] tap = toptaps[key]
if tap[2] != 0: trigger = tap[2]
if trigger != 0:
continue continue
name = key.replace('/', '_') name = key.replace('/', '_')
if i > 0: if i > 0:
@@ -638,7 +625,8 @@ def gen_vl_header(file, modules, taps):
i = 0 i = 0
for key in toptaps: for key in toptaps:
tap = toptaps[key] tap = toptaps[key]
if tap[2] == 0: trigger = tap[2]
if trigger == 0:
continue continue
name = key.replace('/', '_') name = key.replace('/', '_')
if i > 0: if i > 0:
@@ -729,23 +717,41 @@ struct scope_tap_t {
for key in taps: for key in taps:
tap = taps[key] tap = taps[key]
size = str(tap[0]) size = str(tap[0])
trigger = tap[2]
if (trigger != 0):
continue
paths = key.split('/') paths = key.split('/')
if (len(paths) > 1): if (len(paths) > 1):
name = paths.pop(-1) name = paths.pop(-1)
asize = tap[1] asize = tap[1]
for ss in flatten_path(paths, asize): for ss in flatten_path(paths, asize):
fdic[ss + '/' + name ] = [size, -1] fdic[ss + '/' + name ] = [size, 0]
else: else:
fdic[key] = [size, -1] fdic[key] = [size, 0]
for key in taps:
tap = taps[key]
size = str(tap[0])
trigger = tap[2]
if (trigger == 0):
continue
paths = key.split('/')
if (len(paths) > 1):
name = paths.pop(-1)
asize = tap[1]
for ss in flatten_path(paths, asize):
fdic[ss + '/' + name ] = [size, 0]
else:
fdic[key] = [size, 0]
# generate module dic # generate module dic
mdic = {} mdic = {}
mdic["*"] = ("*", 0, -1)
for key in fdic: for key in fdic:
paths = key.split('/') paths = key.split('/')
if len(paths) == 1: if len(paths) == 1:
continue continue
paths.pop(-1) paths.pop(-1)
parent = -1 parent = 0
mk = "" mk = ""
for path in paths: for path in paths:
mk += '/' + path mk += '/' + path